amdsmi.h Source File

• interface

amdsmi.h

Go to the documentation of this file.

1 /*

2  * Copyright (c) Advanced Micro Devices, Inc. All rights reserved.

3  *

4  * Permission is hereby granted, free of charge, to any person obtaining a copy

5  * of this software and associated documentation files (the "Software"), to deal

6  * in the Software without restriction, including without limitation the rights

7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

8  * copies of the Software, and to permit persons to whom the Software is

9  * furnished to do so, subject to the following conditions:

10  *

11  * The above copyright notice and this permission notice shall be included in

12  * all copies or substantial portions of the Software.

13  *

14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

20  * THE SOFTWARE.

21  */

22 

23 #ifndef __AMDSMI_H__

24 #define __AMDSMI_H__

25 

31 #ifndef __KERNEL__

32 #include <stdint.h>

33 #include <stdbool.h>

34 #include <stddef.h>

35 #endif

36 

44 typedef enum {

45  AMDSMI_INIT_ALL_PROCESSORS = 0xFFFFFFFF,

46  AMDSMI_INIT_AMD_CPUS = (1 << 0),

47  AMDSMI_INIT_AMD_GPUS = (1 << 1),

48  AMDSMI_INIT_NON_AMD_CPUS = (1 << 2),

49  AMDSMI_INIT_NON_AMD_GPUS = (1 << 3),

50  AMDSMI_INIT_AMD_APUS = (AMDSMI_INIT_AMD_CPUS | AMDSMI_INIT_AMD_GPUS)

52 } amdsmi_init_flags_t;

53 

59 typedef void *amdsmi_processor_handle;

60 typedef void *amdsmi_socket_handle;

61 

70 typedef enum {

71  AMDSMI_STATUS_SUCCESS = 0,

72  // Library usage errors

73  AMDSMI_STATUS_INVAL = 1,

74  AMDSMI_STATUS_NOT_SUPPORTED = 2,

75  AMDSMI_STATUS_NOT_YET_IMPLEMENTED = 3,

76  AMDSMI_STATUS_FAIL_LOAD_MODULE = 4,

77  AMDSMI_STATUS_FAIL_LOAD_SYMBOL = 5,

78  AMDSMI_STATUS_DRM_ERROR = 6,

79  AMDSMI_STATUS_API_FAILED = 7,

80  AMDSMI_STATUS_TIMEOUT = 8,

81  AMDSMI_STATUS_RETRY = 9,

82  AMDSMI_STATUS_NO_PERM = 10,

83  AMDSMI_STATUS_INTERRUPT = 11,

84  AMDSMI_STATUS_IO = 12,

85  AMDSMI_STATUS_ADDRESS_FAULT = 13,

86  AMDSMI_STATUS_FILE_ERROR = 14,

87  AMDSMI_STATUS_OUT_OF_RESOURCES = 15,

88  AMDSMI_STATUS_INTERNAL_EXCEPTION = 16,

89  AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS = 17,

90  AMDSMI_STATUS_INIT_ERROR = 18,

91  AMDSMI_STATUS_REFCOUNT_OVERFLOW = 19,

92  AMDSMI_STATUS_DIRECTORY_NOT_FOUND = 20,

93  // Processor related errors

94  AMDSMI_STATUS_BUSY = 30,

95  AMDSMI_STATUS_NOT_FOUND = 31,

96  AMDSMI_STATUS_NOT_INIT = 32,

97  AMDSMI_STATUS_NO_SLOT = 33,

98  AMDSMI_STATUS_DRIVER_NOT_LOADED = 34,

99  // Data and size errors

100  AMDSMI_STATUS_MORE_DATA = 39,

101  AMDSMI_STATUS_NO_DATA = 40,

102  AMDSMI_STATUS_INSUFFICIENT_SIZE = 41,

103  AMDSMI_STATUS_UNEXPECTED_SIZE = 42,

104  AMDSMI_STATUS_UNEXPECTED_DATA = 43,

105  //esmi errors

106  AMDSMI_STATUS_NON_AMD_CPU = 44,

107  AMDSMI_STATUS_NO_ENERGY_DRV = 45,

108  AMDSMI_STATUS_NO_MSR_DRV = 46,

109  AMDSMI_STATUS_NO_HSMP_DRV = 47,

110  AMDSMI_STATUS_NO_HSMP_SUP = 48,

111  AMDSMI_STATUS_NO_HSMP_MSG_SUP = 49,

112  AMDSMI_STATUS_HSMP_TIMEOUT = 50,

113  AMDSMI_STATUS_NO_DRV = 51,

114  AMDSMI_STATUS_FILE_NOT_FOUND = 52,

115  AMDSMI_STATUS_ARG_PTR_NULL = 53,

116  AMDSMI_STATUS_AMDGPU_RESTART_ERR = 54,

117  AMDSMI_STATUS_SETTING_UNAVAILABLE = 55,

118  AMDSMI_STATUS_CORRUPTED_EEPROM = 56,

119  // General errors

120  AMDSMI_STATUS_MAP_ERROR = 0xFFFFFFFE,

121  AMDSMI_STATUS_UNKNOWN_ERROR = 0xFFFFFFFF,

122 } amdsmi_status_t;

123 

133 typedef enum {

134  AMDSMI_PROCESSOR_TYPE_UNKNOWN = 0,

135  AMDSMI_PROCESSOR_TYPE_AMD_GPU,

136  AMDSMI_PROCESSOR_TYPE_AMD_CPU,

137  AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU,

138  AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU,

139  AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE,

140  AMDSMI_PROCESSOR_TYPE_AMD_APU,

141  AMDSMI_PROCESSOR_TYPE_AMD_NIC

142 } processor_type_t;

143 

149 #define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK 64

150 #define AMDSMI_MAX_NUM_PM_POLICIES 32

151 #define AMDSMI_MAX_CONTAINER_TYPE 2

152 

158 #define AMDSMI_MAX_MM_IP_COUNT 8

159 #define AMDSMI_MAX_DEVICES 32

160 #define AMDSMI_MAX_STRING_LENGTH 256

161 #define AMDSMI_MAX_CACHE_TYPES 10

162 #define AMDSMI_MAX_CP_PROFILE_RESOURCES 32

163 #define AMDSMI_MAX_ACCELERATOR_PARTITIONS 8

164 #define AMDSMI_MAX_ACCELERATOR_PROFILE 32

165 #define AMDSMI_MAX_NUM_NUMA_NODES 32

166 #define AMDSMI_GPU_UUID_SIZE 38

167 

173 #define MAX_NUMBER_OF_AFIDS_PER_RECORD 12

174 

180 #define AMDSMI_MAX_VF_COUNT 32

181 #define AMDSMI_MAX_DRIVER_NUM 2

182 #define AMDSMI_DFC_FW_NUMBER_OF_ENTRIES 9

183 #define AMDSMI_MAX_WHITE_LIST_ELEMENTS 16

184 #define AMDSMI_MAX_BLACK_LIST_ELEMENTS 64

185 #define AMDSMI_MAX_UUID_ELEMENTS 16

186 #define AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS 8

187 #define AMDSMI_MAX_ERR_RECORDS 10

188 #define AMDSMI_MAX_PROFILE_COUNT 16

189 

195 #define AMDSMI_TIME_FORMAT "%02d:%02d:%02d.%03d"

196 #define AMDSMI_DATE_FORMAT "%04d-%02d-%02d:%02d:%02d:%02d.%03d"

197 

203 typedef void *amdsmi_node_handle;

204 

210 typedef enum {

211  AMDSMI_MEMORY_PARTITION_UNKNOWN = 0,

212  AMDSMI_MEMORY_PARTITION_NPS1 = 1,

214  AMDSMI_MEMORY_PARTITION_NPS2 = 2,

217  AMDSMI_MEMORY_PARTITION_NPS4 = 4,

220  AMDSMI_MEMORY_PARTITION_NPS8 = 8,

225 } amdsmi_memory_partition_type_t;

226 

232 typedef enum {

233  AMDSMI_ACCELERATOR_PARTITION_INVALID = 0,

234  AMDSMI_ACCELERATOR_PARTITION_SPX,

236  AMDSMI_ACCELERATOR_PARTITION_DPX,

238  AMDSMI_ACCELERATOR_PARTITION_TPX,

240  AMDSMI_ACCELERATOR_PARTITION_QPX,

242  AMDSMI_ACCELERATOR_PARTITION_CPX,

244  AMDSMI_ACCELERATOR_PARTITION_MAX

245 } amdsmi_accelerator_partition_type_t;

246 

252 typedef enum {

253  AMDSMI_VRAM_TYPE_UNKNOWN = 0,

254  // HBM

255  AMDSMI_VRAM_TYPE_HBM = 1,

256  AMDSMI_VRAM_TYPE_HBM2 = 2,

257  AMDSMI_VRAM_TYPE_HBM2E = 3,

258  AMDSMI_VRAM_TYPE_HBM3 = 4,

259  AMDSMI_VRAM_TYPE_HBM3E = 5,

260  // DDR

261  AMDSMI_VRAM_TYPE_DDR2 = 10,

262  AMDSMI_VRAM_TYPE_DDR3 = 11,

263  AMDSMI_VRAM_TYPE_DDR4 = 12,

264  // GDDR

265  AMDSMI_VRAM_TYPE_GDDR1 = 17,

266  AMDSMI_VRAM_TYPE_GDDR2 = 18,

267  AMDSMI_VRAM_TYPE_GDDR3 = 19,

268  AMDSMI_VRAM_TYPE_GDDR4 = 20,

269  AMDSMI_VRAM_TYPE_GDDR5 = 21,

270  AMDSMI_VRAM_TYPE_GDDR6 = 22,

271  AMDSMI_VRAM_TYPE_GDDR7 = 23,

272  AMDSMI_VRAM_TYPE__MAX = AMDSMI_VRAM_TYPE_GDDR7

273 } amdsmi_vram_type_t;

274 

280 typedef enum {

281  AMDSMI_ACCELERATOR_XCC,

282  AMDSMI_ACCELERATOR_ENCODER,

283  AMDSMI_ACCELERATOR_DECODER,

284  AMDSMI_ACCELERATOR_DMA,

285  AMDSMI_ACCELERATOR_JPEG,

286  AMDSMI_ACCELERATOR_MAX

287 } amdsmi_accelerator_partition_resource_type_t;

288 

294 typedef enum {

295  AMDSMI_CLK_TYPE_SYS = 0x0,

296  AMDSMI_CLK_TYPE_FIRST = AMDSMI_CLK_TYPE_SYS,

297  AMDSMI_CLK_TYPE_GFX = AMDSMI_CLK_TYPE_SYS,

298  AMDSMI_CLK_TYPE_DF,

300  AMDSMI_CLK_TYPE_DCEF,

302  AMDSMI_CLK_TYPE_SOC,

303  AMDSMI_CLK_TYPE_MEM,

304  AMDSMI_CLK_TYPE_PCIE,

305  AMDSMI_CLK_TYPE_VCLK0,

306  AMDSMI_CLK_TYPE_VCLK1,

307  AMDSMI_CLK_TYPE_DCLK0,

308  AMDSMI_CLK_TYPE_DCLK1,

309  AMDSMI_CLK_TYPE__MAX = AMDSMI_CLK_TYPE_DCLK1

310 } amdsmi_clk_type_t;

311 

318 typedef enum {

319  AMDSMI_TEMPERATURE_TYPE_EDGE,

320  AMDSMI_TEMPERATURE_TYPE_FIRST = AMDSMI_TEMPERATURE_TYPE_EDGE,

321  AMDSMI_TEMPERATURE_TYPE_HOTSPOT,

322  AMDSMI_TEMPERATURE_TYPE_JUNCTION = AMDSMI_TEMPERATURE_TYPE_HOTSPOT,

323  AMDSMI_TEMPERATURE_TYPE_VRAM,

324  AMDSMI_TEMPERATURE_TYPE_HBM_0,

325  AMDSMI_TEMPERATURE_TYPE_HBM_1,

326  AMDSMI_TEMPERATURE_TYPE_HBM_2,

327  AMDSMI_TEMPERATURE_TYPE_HBM_3,

328  AMDSMI_TEMPERATURE_TYPE_PLX,

329 

330  // GPU Board Node temperature

331  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_FIRST = 100,

332  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X

333  = AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_FIRST,

334  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC,

335  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2,

336  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR,

337  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR,

338  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR,

339  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_LAST = 149,

340 

341  // GPU Board VR (Voltage Regulator) temperature

342  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_FIRST = 150,

343  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0

344  = AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_FIRST,

345  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1,

346  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2,

347  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3,

348  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A,

349  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C,

350  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A,

351  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C,

352  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM,

353  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B,

354  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D,

355  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR,

356  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32,

357  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_LAST = 199,

358 

359  // Baseboard System temperature

360  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_FIRST = 200,

361  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA = AMDSMI_TEMPERATURE_TYPE_BASEBOARD_FIRST,

362  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT,

363  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK,

364  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7,

365  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC,

366  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA,

367  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1,

368  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC,

369  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC,

370  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC,

371  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC,

372  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR,

373  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR,

374  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR,

375  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR,

376  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR,

377  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR,

378  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR,

379  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR,

380  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR,

381  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR,

382  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC,

383  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC,

384  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_LAST = 249,

385  AMDSMI_TEMPERATURE_TYPE__MAX = AMDSMI_TEMPERATURE_TYPE_BASEBOARD_LAST

386 } amdsmi_temperature_type_t;

387 

394 typedef enum {

395  AMDSMI_TEMP_CURRENT = 0x0,

396  AMDSMI_TEMP_FIRST = AMDSMI_TEMP_CURRENT,

397  AMDSMI_TEMP_MAX,

398  AMDSMI_TEMP_MIN,

399  AMDSMI_TEMP_MAX_HYST,

401  AMDSMI_TEMP_MIN_HYST,

403  AMDSMI_TEMP_CRITICAL,

405  AMDSMI_TEMP_CRITICAL_HYST,

407  AMDSMI_TEMP_EMERGENCY,

411  AMDSMI_TEMP_EMERGENCY_HYST,

413  AMDSMI_TEMP_CRIT_MIN,

415  AMDSMI_TEMP_CRIT_MIN_HYST,

417  AMDSMI_TEMP_OFFSET,

419  AMDSMI_TEMP_LOWEST,

420  AMDSMI_TEMP_HIGHEST,

421  AMDSMI_TEMP_SHUTDOWN,

422  AMDSMI_TEMP_LAST = AMDSMI_TEMP_SHUTDOWN

423 } amdsmi_temperature_metric_t;

424 

430 typedef enum {

431  AMDSMI_CARD_FORM_FACTOR_PCIE,

432  AMDSMI_CARD_FORM_FACTOR_OAM,

433  AMDSMI_CARD_FORM_FACTOR_CEM,

434  AMDSMI_CARD_FORM_FACTOR_UNKNOWN

435 } amdsmi_card_form_factor_t;

436 

442 typedef enum {

443  AMDSMI_LINK_TYPE_INTERNAL = 0,

444  AMDSMI_LINK_TYPE_PCIE = 1,

445  AMDSMI_LINK_TYPE_XGMI = 2,

446  AMDSMI_LINK_TYPE_NOT_APPLICABLE = 3,

447  AMDSMI_LINK_TYPE_UNKNOWN = 4

448 } amdsmi_link_type_t;

449 

455 typedef enum {

456  AMDSMI_CACHE_PROPERTY_ENABLED = 0x00000001,

457  AMDSMI_CACHE_PROPERTY_DATA_CACHE = 0x00000002,

458  AMDSMI_CACHE_PROPERTY_INST_CACHE = 0x00000004,

459  AMDSMI_CACHE_PROPERTY_CPU_CACHE = 0x00000008,

460  AMDSMI_CACHE_PROPERTY_SIMD_CACHE = 0x00000010

461 } amdsmi_cache_property_type_t;

462 

468 typedef enum {

469  AMDSMI_GPU_BLOCK_INVALID = 0,

470  AMDSMI_GPU_BLOCK_FIRST = (1ULL << 0),

471  AMDSMI_GPU_BLOCK_UMC = AMDSMI_GPU_BLOCK_FIRST,

472  AMDSMI_GPU_BLOCK_SDMA = (1ULL << 1),

473  AMDSMI_GPU_BLOCK_GFX = (1ULL << 2),

474  AMDSMI_GPU_BLOCK_MMHUB = (1ULL << 3),

475  AMDSMI_GPU_BLOCK_ATHUB = (1ULL << 4),

476  AMDSMI_GPU_BLOCK_PCIE_BIF = (1ULL << 5),

477  AMDSMI_GPU_BLOCK_HDP = (1ULL << 6),

478  AMDSMI_GPU_BLOCK_XGMI_WAFL = (1ULL << 7),

479  AMDSMI_GPU_BLOCK_DF = (1ULL << 8),

480  AMDSMI_GPU_BLOCK_SMN = (1ULL << 9),

481  AMDSMI_GPU_BLOCK_SEM = (1ULL << 10),

482  AMDSMI_GPU_BLOCK_MP0 = (1ULL << 11),

483  AMDSMI_GPU_BLOCK_MP1 = (1ULL << 12),

484  AMDSMI_GPU_BLOCK_FUSE = (1ULL << 13),

485  AMDSMI_GPU_BLOCK_MCA = (1ULL << 14),

486  AMDSMI_GPU_BLOCK_VCN = (1ULL << 15),

487  AMDSMI_GPU_BLOCK_JPEG = (1ULL << 16),

488  AMDSMI_GPU_BLOCK_IH = (1ULL << 17),

489  AMDSMI_GPU_BLOCK_MPIO = (1ULL << 18),

490  AMDSMI_GPU_BLOCK_LAST = AMDSMI_GPU_BLOCK_MPIO,

491  AMDSMI_GPU_BLOCK_RESERVED = (1ULL << 63)

492 } amdsmi_gpu_block_t;

493 

500 typedef enum {

501  AMDSMI_FW_ID_SMU = 1,

503  AMDSMI_FW_ID_FIRST = AMDSMI_FW_ID_SMU,

504  AMDSMI_FW_ID_CP_CE,

505  AMDSMI_FW_ID_CP_PFP,

506  AMDSMI_FW_ID_CP_ME,

507  AMDSMI_FW_ID_CP_MEC_JT1,

508  AMDSMI_FW_ID_CP_MEC_JT2,

509  AMDSMI_FW_ID_CP_MEC1,

510  AMDSMI_FW_ID_CP_MEC2,

511  AMDSMI_FW_ID_RLC,

512  AMDSMI_FW_ID_SDMA0,

513  AMDSMI_FW_ID_SDMA1,

514  AMDSMI_FW_ID_SDMA2,

515  AMDSMI_FW_ID_SDMA3,

516  AMDSMI_FW_ID_SDMA4,

517  AMDSMI_FW_ID_SDMA5,

518  AMDSMI_FW_ID_SDMA6,

519  AMDSMI_FW_ID_SDMA7,

520  AMDSMI_FW_ID_VCN,

521  AMDSMI_FW_ID_UVD,

522  AMDSMI_FW_ID_VCE,

523  AMDSMI_FW_ID_ISP,

524  AMDSMI_FW_ID_DMCU_ERAM,

525  AMDSMI_FW_ID_DMCU_ISR,

526  AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM,

527  AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM,

528  AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL,

529  AMDSMI_FW_ID_RLC_V,

530  AMDSMI_FW_ID_MMSCH,

531  AMDSMI_FW_ID_PSP_SYSDRV,

532  AMDSMI_FW_ID_PSP_SOSDRV,

533  AMDSMI_FW_ID_PSP_TOC,

534  AMDSMI_FW_ID_PSP_KEYDB,

535  AMDSMI_FW_ID_DFC,

536  AMDSMI_FW_ID_PSP_SPL,

537  AMDSMI_FW_ID_DRV_CAP,

538  AMDSMI_FW_ID_MC,

539  AMDSMI_FW_ID_PSP_BL,

540  AMDSMI_FW_ID_CP_PM4,

541  AMDSMI_FW_ID_RLC_P,

542  AMDSMI_FW_ID_SEC_POLICY_STAGE2,

543  AMDSMI_FW_ID_REG_ACCESS_WHITELIST,

544  AMDSMI_FW_ID_IMU_DRAM,

545  AMDSMI_FW_ID_IMU_IRAM,

546  AMDSMI_FW_ID_SDMA_TH0,

547  AMDSMI_FW_ID_SDMA_TH1,

548  AMDSMI_FW_ID_CP_MES,

549  AMDSMI_FW_ID_MES_KIQ,

550  AMDSMI_FW_ID_MES_STACK,

551  AMDSMI_FW_ID_MES_THREAD1,

552  AMDSMI_FW_ID_MES_THREAD1_STACK,

553  AMDSMI_FW_ID_RLX6,

554  AMDSMI_FW_ID_RLX6_DRAM_BOOT,

555  AMDSMI_FW_ID_RS64_ME,

556  AMDSMI_FW_ID_RS64_ME_P0_DATA,

557  AMDSMI_FW_ID_RS64_ME_P1_DATA,

558  AMDSMI_FW_ID_RS64_PFP,

559  AMDSMI_FW_ID_RS64_PFP_P0_DATA,

560  AMDSMI_FW_ID_RS64_PFP_P1_DATA,

561  AMDSMI_FW_ID_RS64_MEC,

562  AMDSMI_FW_ID_RS64_MEC_P0_DATA,

563  AMDSMI_FW_ID_RS64_MEC_P1_DATA,

564  AMDSMI_FW_ID_RS64_MEC_P2_DATA,

565  AMDSMI_FW_ID_RS64_MEC_P3_DATA,

566  AMDSMI_FW_ID_PPTABLE,

567  AMDSMI_FW_ID_PSP_SOC,

568  AMDSMI_FW_ID_PSP_DBG,

569  AMDSMI_FW_ID_PSP_INTF,

570  AMDSMI_FW_ID_RLX6_CORE1,

571  AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1,

572  AMDSMI_FW_ID_RLCV_LX7,

573  AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST,

574  AMDSMI_FW_ID_ASD,

575  AMDSMI_FW_ID_TA_RAS,

576  AMDSMI_FW_ID_TA_XGMI,

577  AMDSMI_FW_ID_XGMI,

578  AMDSMI_FW_ID_RLC_SRLG,

579  AMDSMI_FW_ID_RLC_SRLS,

580  AMDSMI_FW_ID_PM,

581  AMDSMI_FW_ID_SMC,

582  AMDSMI_FW_ID_DMCU,

583  AMDSMI_FW_ID_PSP_RAS,

584  AMDSMI_FW_ID_P2S_TABLE,

585  AMDSMI_FW_ID_PLDM_BUNDLE,

586  AMDSMI_FW_ID__MAX

587 } amdsmi_fw_block_t;

588 

597 typedef enum {

598  AMDSMI_VIRTUALIZATION_MODE_UNKNOWN = 0,

599  AMDSMI_VIRTUALIZATION_MODE_BAREMETAL,

600  AMDSMI_VIRTUALIZATION_MODE_HOST,

601  AMDSMI_VIRTUALIZATION_MODE_GUEST,

602  AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH

603 } amdsmi_virtualization_mode_t;

604 

610 typedef enum {

611  AMDSMI_AFFINITY_SCOPE_NODE,

612  AMDSMI_AFFINITY_SCOPE_SOCKET

613 } amdsmi_affinity_scope_t;

614 

620 typedef enum {

621  AMDSMI_NPM_STATUS_DISABLED,

622  AMDSMI_NPM_STATUS_ENABLED

623 } amdsmi_npm_status_t;

624 

630 typedef enum {

631  AMDSMI_LINK_STATUS_ENABLED = 0,

632  AMDSMI_LINK_STATUS_DISABLED = 1,

633  AMDSMI_LINK_STATUS_INACTIVE = 2,

634  AMDSMI_LINK_STATUS_ERROR = 3

635 } amdsmi_link_status_t;

636 

645 typedef enum {

646  AMDSMI_PTL_DATA_FORMAT_I8 = 0x0,

647  AMDSMI_PTL_DATA_FORMAT_F16 = 0x1,

648  AMDSMI_PTL_DATA_FORMAT_BF16 = 0x2,

649  AMDSMI_PTL_DATA_FORMAT_F32 = 0x3,

650  AMDSMI_PTL_DATA_FORMAT_F64 = 0x4,

651  AMDSMI_PTL_DATA_FORMAT_INVALID = 0xFFFFFFFF

652 } amdsmi_ptl_data_format_t;

653 

659 typedef union {

660  struct bdf_ {

661  uint64_t function_number : 3;

662  uint64_t device_number : 5;

663  uint64_t bus_number : 8;

664  uint64_t domain_number : 48;

665  } bdf;

666  struct {

667  uint64_t function_number : 3;

668  uint64_t device_number : 5;

669  uint64_t bus_number : 8;

670  uint64_t domain_number : 48;

671  };

672  uint64_t as_uint;

673 } amdsmi_bdf_t;

674 

680 typedef struct {

681  struct pcie_static_ {

682  uint16_t max_pcie_width;

683  uint32_t max_pcie_speed;

684  uint32_t pcie_interface_version;

685  amdsmi_card_form_factor_t slot_type;

686  uint32_t max_pcie_interface_version;

687  uint64_t reserved[9];

688  } pcie_static;

689  struct pcie_metric_ {

690  uint16_t pcie_width;

691  uint32_t pcie_speed;

692  uint32_t pcie_bandwidth;

693  uint64_t pcie_replay_count;

694  uint64_t pcie_l0_to_recovery_count;

695  uint64_t pcie_replay_roll_over_count;

696  uint64_t pcie_nak_sent_count;

697  uint64_t pcie_nak_received_count;

698  uint32_t pcie_lc_perf_other_end_recovery_count;

699  uint64_t reserved[12];

700  } pcie_metric;

701  uint64_t reserved[32];

702 } amdsmi_pcie_info_t;

703 

709 typedef struct {

710  uint32_t num_links;

711  struct _links {

712  amdsmi_bdf_t bdf;

713  uint32_t bit_rate;

714  uint32_t max_bandwidth;

715  amdsmi_link_type_t link_type;

716  uint64_t read;

717  uint64_t write;

718  amdsmi_link_status_t link_status;

719  uint64_t reserved[1];

720  } links[AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK];

721  uint64_t reserved[7];

722 } amdsmi_link_metrics_t;

723 

729 typedef struct {

730  uint64_t power_cap;

731  uint64_t default_power_cap;

732  uint64_t dpm_cap;

733  uint64_t min_power_cap;

734  uint64_t max_power_cap;

735  uint64_t reserved[3];

736 } amdsmi_power_cap_info_t;

737 

743 typedef struct {

744  char name[AMDSMI_MAX_STRING_LENGTH];

745  char build_date[AMDSMI_MAX_STRING_LENGTH];

746  char part_number[AMDSMI_MAX_STRING_LENGTH];

747  char version[AMDSMI_MAX_STRING_LENGTH];

748  char boot_firmware[AMDSMI_MAX_STRING_LENGTH];

749  uint64_t reserved[36];

750 } amdsmi_vbios_info_t;

751 

757 typedef struct {

758  char market_name[AMDSMI_MAX_STRING_LENGTH];

759  uint32_t vendor_id;

760  char vendor_name[AMDSMI_MAX_STRING_LENGTH];

761  uint32_t subvendor_id;

762  uint64_t device_id;

763  uint32_t rev_id;

764  char asic_serial[AMDSMI_MAX_STRING_LENGTH];

765  uint32_t oam_id;

766  uint32_t num_of_compute_units;

767  uint64_t target_graphics_version;

768  uint32_t subsystem_id;

769  uint32_t reserved[21];

770 } amdsmi_asic_info_t;

771 

777 typedef struct {

778  uint64_t socket_power;

779  uint32_t current_socket_power;

780  uint32_t average_socket_power;

781  uint64_t gfx_voltage;

782  uint64_t soc_voltage;

783  uint64_t mem_voltage;

784  uint32_t power_limit;

785  uint64_t reserved[18];

786 } amdsmi_power_info_t;

787 

793 typedef struct {

794  char driver_version[AMDSMI_MAX_STRING_LENGTH];

795  char driver_date[AMDSMI_MAX_STRING_LENGTH];

796  char driver_name[AMDSMI_MAX_STRING_LENGTH];

797  uint64_t reserved[64];

798 } amdsmi_driver_info_t;

799 

805 typedef struct {

806  amdsmi_vram_type_t vram_type;

807  char vram_vendor[AMDSMI_MAX_STRING_LENGTH];

808  uint64_t vram_size;

809  uint32_t vram_bit_width;

810  uint64_t vram_max_bandwidth;

811  uint64_t reserved[37];

812 } amdsmi_vram_info_t;

813 

823 typedef struct {

824  uint32_t gfx_activity;

825  uint32_t umc_activity;

826  uint32_t mm_activity;

827  uint32_t reserved[13];

828 } amdsmi_engine_usage_t;

829 

835 typedef struct {

836  uint32_t clk;

837  uint32_t min_clk;

838  uint32_t max_clk;

839  uint8_t clk_locked;

840  uint8_t clk_deep_sleep;

841  uint32_t reserved[4];

842 } amdsmi_clk_info_t;

843 

849 typedef struct {

850  uint64_t correctable_count;

851  uint64_t uncorrectable_count;

852  uint64_t deferred_count;

853  uint64_t reserved[5];

854 } amdsmi_error_count_t;

855 

861 typedef union {

862  struct nps_flags_{

863  uint32_t nps1_cap :1;

864  uint32_t nps2_cap :1;

865  uint32_t nps4_cap :1;

866  uint32_t nps8_cap :1;

867  uint32_t reserved :28;

868  } nps_flags;

869  uint32_t nps_cap_mask;

870 } amdsmi_nps_caps_t;

871 

878 typedef struct {

879  amdsmi_nps_caps_t partition_caps;

880  amdsmi_memory_partition_type_t mp_mode;

881  uint32_t num_numa_ranges;

882  struct numa_range_{

883  amdsmi_vram_type_t memory_type;

884  uint64_t start;

885  uint64_t end;

886  } numa_range[AMDSMI_MAX_NUM_NUMA_NODES];

887  uint64_t reserved[11];

888 } amdsmi_memory_partition_config_t;

889 

895 typedef struct {

896  amdsmi_accelerator_partition_type_t profile_type;

897  uint32_t num_partitions;

898  amdsmi_nps_caps_t memory_caps;

899  uint32_t profile_index;

900  uint32_t num_resources;

901  uint32_t resources[AMDSMI_MAX_ACCELERATOR_PARTITIONS][AMDSMI_MAX_CP_PROFILE_RESOURCES];

902  uint64_t reserved[13];

903 } amdsmi_accelerator_partition_profile_t;

904 

911 typedef struct {

912  uint32_t profile_index;

913  amdsmi_accelerator_partition_resource_type_t resource_type;

914  uint32_t partition_resource;

915  uint32_t num_partitions_share_resource;

916  uint64_t reserved[6];

917 } amdsmi_accelerator_partition_resource_profile_t;

918 

924 typedef struct {

925  uint32_t num_profiles;

926  uint32_t num_resource_profiles;

927  amdsmi_accelerator_partition_resource_profile_t resource_profiles[AMDSMI_MAX_CP_PROFILE_RESOURCES];

928  uint32_t default_profile_index;

929  amdsmi_accelerator_partition_profile_t profiles[AMDSMI_MAX_ACCELERATOR_PROFILE];

930  uint64_t reserved[30];

931 } amdsmi_accelerator_partition_profile_config_t;

932 

938 typedef struct {

939  char model_number[AMDSMI_MAX_STRING_LENGTH];

940  char product_serial[AMDSMI_MAX_STRING_LENGTH];

941  char fru_id[AMDSMI_MAX_STRING_LENGTH];

942  char product_name[AMDSMI_MAX_STRING_LENGTH];

943  char manufacturer_name[AMDSMI_MAX_STRING_LENGTH];

944  uint64_t reserved[64];

945 } amdsmi_board_info_t;

946 

952 typedef struct {

953  uint8_t is_iolink_coherent;

954  uint8_t is_iolink_atomics_32bit;

955  uint8_t is_iolink_atomics_64bit;

956  uint8_t is_iolink_dma;

957  uint8_t is_iolink_bi_directional;

958 } amdsmi_p2p_capability_t;

959 

965 typedef struct {

966  amdsmi_npm_status_t status;

967  uint64_t limit;

968  uint64_t reserved[6];

969 } amdsmi_npm_info_t;

970 

976 typedef struct {

977  uint32_t num_cache_types;

978  struct cache_ {

979  uint32_t cache_properties;

980  uint32_t cache_size;

981  uint32_t cache_level;

982  uint32_t max_num_cu_shared;

983  uint32_t num_cache_instance;

984  uint32_t reserved[3];

985  } cache[AMDSMI_MAX_CACHE_TYPES];

986  uint32_t reserved[15];

987 } amdsmi_gpu_cache_info_t;

988 

994 typedef struct {

995  uint8_t num_fw_info;

996  struct {

997  amdsmi_fw_block_t fw_id;

998  uint64_t fw_version;

999  uint64_t reserved[2];

1000  } fw_info_list[AMDSMI_FW_ID__MAX];

1001  uint32_t reserved[7];

1002 } amdsmi_fw_info_t;

1003 

1009 typedef struct {

1010  uint32_t policy_id;

1011  char policy_description[AMDSMI_MAX_STRING_LENGTH];

1012 } amdsmi_dpm_policy_entry_t;

1013 

1021 typedef struct {

1022  uint32_t num_supported;

1023  uint32_t current;

1024  amdsmi_dpm_policy_entry_t policies[AMDSMI_MAX_NUM_PM_POLICIES];

1025 } amdsmi_dpm_policy_t;

1026 

1032 typedef struct {

1033  struct {

1034  uint32_t dram_ecc : 1;

1035  uint32_t sram_ecc : 1;

1036  uint32_t poisoning : 1;

1037  uint32_t rsvd : 29;

1038  } ras_info;

1039  bool needs_reboot;

1040  uint32_t ras_eeprom_version;

1042  uint32_t ecc_correction_schema_flag;

1045  uint32_t reserved[4];

1046 } amdsmi_ras_feature_t;

1047 

1053 typedef enum {

1054  AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED = 0,

1055  AMDSMI_CPER_SEV_FATAL = 1,

1056  AMDSMI_CPER_SEV_NON_FATAL_CORRECTED = 2,

1057  AMDSMI_CPER_SEV_NUM = 3,

1058  AMDSMI_CPER_SEV_UNUSED = 10

1059 } amdsmi_cper_sev_t;

1060 

1066 typedef enum {

1067  AMDSMI_CPER_NOTIFY_TYPE_CMC = 0x450eBDD72DCE8BB1,

1068  AMDSMI_CPER_NOTIFY_TYPE_CPE = 0x4a55D8434E292F96,

1069  AMDSMI_CPER_NOTIFY_TYPE_MCE = 0x4cc5919CE8F56FFE,

1070  AMDSMI_CPER_NOTIFY_TYPE_PCIE = 0x4dfc1A16CF93C01F,

1071  AMDSMI_CPER_NOTIFY_TYPE_INIT = 0x454a9308CC5263E8,

1072  AMDSMI_CPER_NOTIFY_TYPE_NMI = 0x42c9B7E65BAD89FF,

1073  AMDSMI_CPER_NOTIFY_TYPE_BOOT = 0x409aAB403D61A466,

1074  AMDSMI_CPER_NOTIFY_TYPE_DMAR = 0x4c27C6B3667DD791,

1075  AMDSMI_CPER_NOTIFY_TYPE_SEA = 0x11E4BBE89A78788A,

1076  AMDSMI_CPER_NOTIFY_TYPE_SEI = 0x4E87B0AE5C284C81,

1077  AMDSMI_CPER_NOTIFY_TYPE_PEI = 0x4214520409A9D5AC,

1078  AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT = 0x49A341DF69293BC9

1079 } amdsmi_cper_notify_type_t;

1080 

1086 typedef struct {

1087  uint16_t dram_non_critical_region_threshold;

1088  uint16_t dram_critical_region_threshold;

1089 } amdsmi_gpu_ras_policy_v4_0_t;

1090 

1097 typedef struct {

1098  uint8_t major_version;

1099  uint8_t minor_version;

1100  union {

1101  amdsmi_gpu_ras_policy_v4_0_t v4_0;

1102  uint64_t info[5];

1103  } policy_data;

1104 } amdsmi_gpu_ras_policy_info_t;

1105 

1106 #pragma pack(push, 1)

1107 

1113 typedef struct {

1114  unsigned char b[16];

1115 } amdsmi_cper_guid_t;

1116 

1117 typedef struct {

1118  uint8_t seconds;

1119  uint8_t minutes;

1120  uint8_t hours;

1121  uint8_t flag;

1122  uint8_t day;

1123  uint8_t month;

1124  uint8_t year;

1125  uint8_t century;

1126 } amdsmi_cper_timestamp_t;

1127 

1128 typedef union {

1129  struct valid_bits_ {

1130  uint32_t platform_id : 1;

1131  uint32_t timestamp : 1;

1132  uint32_t partition_id : 1;

1133  uint32_t reserved : 29;

1134  } valid_bits;

1135  uint32_t valid_mask;

1136 } amdsmi_cper_valid_bits_t;

1137 

1138 typedef struct {

1139  char signature[4];

1140  uint16_t revision;

1141  uint32_t signature_end;

1142  uint16_t sec_cnt;

1143  amdsmi_cper_sev_t error_severity;

1144  amdsmi_cper_valid_bits_t cper_valid_bits;

1145  uint32_t record_length;

1146  amdsmi_cper_timestamp_t timestamp;

1147  char platform_id[16];

1148  amdsmi_cper_guid_t partition_id;

1149  char creator_id[16];

1150  amdsmi_cper_guid_t notify_type;

1151  char record_id[8];

1152  uint32_t flags;

1153  uint64_t persistence_info;

1154  uint8_t reserved[12];

1155 } amdsmi_cper_hdr_t;

1156 

1157 #pragma pack(pop)

1158 

1164 #define SMI_VERSION_ALPHA_0 0x00000002

1165 #define SMI_VERSION_BETA_0 0x00000003

1166 #define SMI_VERSION_BETA_1 0x00000004

1167 #define SMI_VERSION_BETA_2 0x00000005

1168 #define SMI_VERSION_BETA_3 0x00000006

1169 #define SMI_VERSION_BETA_4 0x00000007

1170 

1178 #define AMDSMI_MASK_ALL (~0ULL)

1179 

1181 #define AMDSMI_MASK_DEFAULT ((1ULL << 62) - 1)

1182 

1184 #define AMDSMI_MASK_INIT (0ULL)

1185 

1187 #define AMDSMI_MASK_HIGH_AND_MED_SEVERITY (~((1ULL << 61) - 1))

1188 

1194 #define AMDSMI_MASK_HIGH_ERROR_SEVERITY_ONLY(mask) (mask & ((1ULL << 60) - 1))

1195 #define AMDSMI_MASK_INCLUDE_MED_ERROR_SEVERITY(mask) (mask | (1ULL << 60))

1196 #define AMDSMI_MASK_INCLUDE_LOW_ERROR_SEVERITY(mask) (mask | (1ULL << 61))

1197 #define AMDSMI_MASK_INCLUDE_WARN_SEVERITY(mask) (mask | (1ULL << 62))

1198 #define AMDSMI_MASK_INCLUDE_INFO_SEVERITY(mask) (mask | (1ULL << 63))

1199 

1205 #define AMDSMI_MASK_HIGH_SEVERITY_ONLY(mask) (mask & ((1ULL << 62) - 1))

1206 #define AMDSMI_MASK_INCLUDE_MED_SEVERITY(mask) AMDSMI_MASK_INCLUDE_WARN_SEVERITY(mask)

1207 #define AMDSMI_MASK_INCLUDE_LOW_SEVERITY(mask) AMDSMI_MASK_INCLUDE_INFO_SEVERITY(mask)

1208 

1209 #define AMDSMI_MASK_INCLUDE_CATEGORY(mask, cate) (mask | (1ULL << cate))

1210 #define AMDSMI_MASK_EXCLUDE_CATEGORY(mask, cate) (mask & (~(1ULL << cate)))

1211 

1212 #define AMDSMI_MAX_FB_SHARING_GROUPS 64

1213 #define AMDSMI_MAX_NUM_CONNECTED_NODES 64

1214 

1215 #define AMDSMI_MAX_NUM_METRICS_V1 255

1216 #define AMDSMI_MAX_NUM_METRICS_V2 512

1217 #define AMDSMI_MAX_NUM_METRICS AMDSMI_MAX_NUM_METRICS_V2

1218 

1219 #define AMDSMI_MAX_BAD_PAGE_RECORD_V1 512

1220 #define AMDSMI_MAX_BAD_PAGE_RECORD_V2 16384

1221 #define AMDSMI_MAX_BAD_PAGE_RECORD AMDSMI_MAX_BAD_PAGE_RECORD_V2

1222 

1228 #define AMDSMI_MAX_DATE_STRING_LENGTH 32

1229 

1235 typedef void *amdsmi_event_set;

1236 

1242 typedef enum {

1243  AMDSMI_EVENT_CATEGORY_NON_USED = 0,

1244  AMDSMI_EVENT_CATEGORY_DRIVER = 1,

1245  AMDSMI_EVENT_CATEGORY_RESET = 2,

1246  AMDSMI_EVENT_CATEGORY_SCHED = 3,

1247  AMDSMI_EVENT_CATEGORY_VBIOS = 4,

1248  AMDSMI_EVENT_CATEGORY_ECC = 5,

1249  AMDSMI_EVENT_CATEGORY_PP = 6,

1250  AMDSMI_EVENT_CATEGORY_IOV = 7,

1251  AMDSMI_EVENT_CATEGORY_VF = 8,

1252  AMDSMI_EVENT_CATEGORY_FW = 9,

1253  AMDSMI_EVENT_CATEGORY_GPU = 10,

1254  AMDSMI_EVENT_CATEGORY_GUARD = 11,

1255  AMDSMI_EVENT_CATEGORY_GPUMON = 12,

1256  AMDSMI_EVENT_CATEGORY_MMSCH = 13,

1257  AMDSMI_EVENT_CATEGORY_XGMI = 14,

1258  AMDSMI_EVENT_CATEGORY__MAX

1259 } amdsmi_event_category_t;

1260 

1266 typedef enum {

1267  AMDSMI_EVENT_GPU_DEVICE_LOST = 0,

1268  AMDSMI_EVENT_GPU_NOT_SUPPORTED,

1269  AMDSMI_EVENT_GPU_RMA,

1270  AMDSMI_EVENT_GPU_NOT_INITIALIZED,

1271  AMDSMI_EVENT_GPU_MMSCH_ABNORMAL_STATE,

1272  AMDSMI_EVENT_GPU_RLCV_ABNORMAL_STATE,

1273  AMDSMI_EVENT_GPU_SDMA_ENGINE_BUSY,

1274  AMDSMI_EVENT_GPU_RLC_ENGINE_BUSY,

1275  AMDSMI_EVENT_GPU_GC_ENGINE_BUSY,

1276  AMDSMI_EVENT_GPU__MAX

1277 } amdsmi_event_gpu_t;

1278 

1284 typedef enum {

1285  AMDSMI_EVENT_DRIVER_SPIN_LOCK_BUSY = 0,

1286  AMDSMI_EVENT_DRIVER_ALLOC_SYSTEM_MEM_FAIL,

1287  AMDSMI_EVENT_DRIVER_CREATE_GFX_WORKQUEUE_FAIL,

1288  AMDSMI_EVENT_DRIVER_CREATE_MM_WORKQUEUE_FAIL,

1289  AMDSMI_EVENT_DRIVER_BUFFER_OVERFLOW,

1290 

1291  AMDSMI_EVENT_DRIVER_DEV_INIT_FAIL,

1292  AMDSMI_EVENT_DRIVER_CREATE_THREAD_FAIL,

1293  AMDSMI_EVENT_DRIVER_NO_ACCESS_PCI_REGION,

1294  AMDSMI_EVENT_DRIVER_MMIO_FAIL,

1295  AMDSMI_EVENT_DRIVER_INTERRUPT_INIT_FAIL,

1296 

1297  AMDSMI_EVENT_DRIVER_INVALID_VALUE,

1298  AMDSMI_EVENT_DRIVER_CREATE_MUTEX_FAIL,

1299  AMDSMI_EVENT_DRIVER_CREATE_TIMER_FAIL,

1300  AMDSMI_EVENT_DRIVER_CREATE_EVENT_FAIL,

1301  AMDSMI_EVENT_DRIVER_CREATE_SPIN_LOCK_FAIL,

1302 

1303  AMDSMI_EVENT_DRIVER_ALLOC_FB_MEM_FAIL,

1304  AMDSMI_EVENT_DRIVER_ALLOC_DMA_MEM_FAIL,

1305  AMDSMI_EVENT_DRIVER_NO_FB_MANAGER,

1306  AMDSMI_EVENT_DRIVER_HW_INIT_FAIL,

1307  AMDSMI_EVENT_DRIVER_SW_INIT_FAIL,

1308 

1309  AMDSMI_EVENT_DRIVER_INIT_CONFIG_ERROR,

1310  AMDSMI_EVENT_DRIVER_ERROR_LOGGING_FAILED,

1311  AMDSMI_EVENT_DRIVER_CREATE_RWLOCK_FAIL,

1312  AMDSMI_EVENT_DRIVER_CREATE_RWSEMA_FAIL,

1313  AMDSMI_EVENT_DRIVER_GET_READ_LOCK_FAIL,

1314 

1315  AMDSMI_EVENT_DRIVER_GET_WRITE_LOCK_FAIL,

1316  AMDSMI_EVENT_DRIVER_GET_READ_SEMA_FAIL,

1317  AMDSMI_EVENT_DRIVER_GET_WRITE_SEMA_FAIL,

1318 

1319  AMDSMI_EVENT_DRIVER_DIAG_DATA_INIT_FAIL,

1320  AMDSMI_EVENT_DRIVER_DIAG_DATA_MEM_REQ_FAIL,

1321  AMDSMI_EVENT_DRIVER_DIAG_DATA_VADDR_REQ_FAIL,

1322  AMDSMI_EVENT_DRIVER_DIAG_DATA_BUS_ADDR_REQ_FAIL,

1323 

1324  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_INIT_FAIL,

1325  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_MEM_REQ_FAIL,

1326  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_VADDR_REQ_FAIL,

1327  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_BUS_ADDR_REQ_FAIL,

1328 

1329  AMDSMI_EVENT_DRIVER_HRTIMER_START_FAIL,

1330  AMDSMI_EVENT_DRIVER_CREATE_DRIVER_FILE_FAIL,

1331  AMDSMI_EVENT_DRIVER_CREATE_DEVICE_FILE_FAIL,

1332  AMDSMI_EVENT_DRIVER_CREATE_DEBUGFS_FILE_FAIL,

1333  AMDSMI_EVENT_DRIVER_CREATE_DEBUGFS_DIR_FAIL,

1334 

1335  AMDSMI_EVENT_DRIVER_PCI_ENABLE_DEVICE_FAIL,

1336  AMDSMI_EVENT_DRIVER_FB_MAP_FAIL,

1337  AMDSMI_EVENT_DRIVER_DOORBELL_MAP_FAIL,

1338  AMDSMI_EVENT_DRIVER_PCI_REGISTER_DRIVER_FAIL,

1339 

1340  AMDSMI_EVENT_DRIVER_ALLOC_IOVA_ALIGN_FAIL,

1341 

1342  AMDSMI_EVENT_DRIVER_ROM_MAP_FAIL,

1343  AMDSMI_EVENT_DRIVER_FULL_ACCESS_TIMEOUT,

1344 

1345  AMDSMI_EVENT_DRIVER__MAX

1346 } amdsmi_event_driver_t;

1347 

1353 typedef enum {

1354  AMDSMI_EVENT_FW_CMD_ALLOC_BUF_FAIL = 0,

1355  AMDSMI_EVENT_FW_CMD_BUF_PREP_FAIL,

1356  AMDSMI_EVENT_FW_RING_INIT_FAIL,

1357  AMDSMI_EVENT_FW_FW_APPLY_SECURITY_POLICY_FAIL,

1358  AMDSMI_EVENT_FW_START_RING_FAIL,

1359 

1360  AMDSMI_EVENT_FW_FW_LOAD_FAIL,

1361  AMDSMI_EVENT_FW_EXIT_FAIL,

1362  AMDSMI_EVENT_FW_INIT_FAIL,

1363  AMDSMI_EVENT_FW_CMD_SUBMIT_FAIL,

1364  AMDSMI_EVENT_FW_CMD_FENCE_WAIT_FAIL,

1365 

1366  AMDSMI_EVENT_FW_TMR_LOAD_FAIL,

1367  AMDSMI_EVENT_FW_TOC_LOAD_FAIL,

1368  AMDSMI_EVENT_FW_RAS_LOAD_FAIL,

1369  AMDSMI_EVENT_FW_RAS_UNLOAD_FAIL,

1370  AMDSMI_EVENT_FW_RAS_TA_INVOKE_FAIL,

1371  AMDSMI_EVENT_FW_RAS_TA_ERR_INJECT_FAIL,

1372 

1373  AMDSMI_EVENT_FW_ASD_LOAD_FAIL,

1374  AMDSMI_EVENT_FW_ASD_UNLOAD_FAIL,

1375  AMDSMI_EVENT_FW_AUTOLOAD_FAIL,

1376  AMDSMI_EVENT_FW_VFGATE_FAIL,

1377 

1378  AMDSMI_EVENT_FW_XGMI_LOAD_FAIL,

1379  AMDSMI_EVENT_FW_XGMI_UNLOAD_FAIL,

1380  AMDSMI_EVENT_FW_XGMI_TA_INVOKE_FAIL,

1381 

1382  AMDSMI_EVENT_FW_TMR_INIT_FAIL,

1383  AMDSMI_EVENT_FW_NOT_SUPPORTED_FEATURE,

1384  AMDSMI_EVENT_FW_GET_PSP_TRACELOG_FAIL,

1385 

1386  AMDSMI_EVENT_FW_SET_SNAPSHOT_ADDR_FAIL,

1387  AMDSMI_EVENT_FW_SNAPSHOT_TRIGGER_FAIL,

1388 

1389  AMDSMI_EVENT_FW_MIGRATION_GET_PSP_INFO_FAIL,

1390  AMDSMI_EVENT_FW_MIGRATION_EXPORT_FAIL,

1391  AMDSMI_EVENT_FW_MIGRATION_IMPORT_FAIL,

1392 

1393  AMDSMI_EVENT_FW_BL_FAIL,

1394  AMDSMI_EVENT_FW_RAS_BOOT_FAIL,

1395  AMDSMI_EVENT_FW_MAILBOX_ERROR,

1396 

1397  AMDSMI_EVENT_FW__MAX

1398 } amdsmi_event_fw_t;

1399 

1400 #define AMDSMI_EVENT_FW_FW_INIT_FAIL AMDSMI_EVENT_FW_RING_INIT_FAIL

1401 

1407 typedef enum {

1408  AMDSMI_EVENT_RESET_GPU = 0,

1409  AMDSMI_EVENT_RESET_GPU_FAILED,

1410  AMDSMI_EVENT_RESET_FLR,

1411  AMDSMI_EVENT_RESET_FLR_FAILED,

1412  AMDSMI_EVENT_RESET__MAX

1413 } amdsmi_event_reset_t;

1414 

1420 typedef enum {

1421  AMDSMI_EVENT_IOV_NO_GPU_IOV_CAP = 0,

1422  AMDSMI_EVENT_IOV_ASIC_NO_SRIOV_SUPPORT,

1423  AMDSMI_EVENT_IOV_ENABLE_SRIOV_FAIL,

1424  AMDSMI_EVENT_IOV_CMD_TIMEOUT,

1425  AMDSMI_EVENT_IOV_CMD_ERROR,

1426 

1427  AMDSMI_EVENT_IOV_INIT_IV_RING_FAIL,

1428  AMDSMI_EVENT_IOV_SRIOV_STRIDE_ERROR,

1429  AMDSMI_EVENT_IOV_WS_SAVE_TIMEOUT,

1430  AMDSMI_EVENT_IOV_WS_IDLE_TIMEOUT,

1431  AMDSMI_EVENT_IOV_WS_RUN_TIMEOUT,

1432  AMDSMI_EVENT_IOV_WS_LOAD_TIMEOUT,

1433  AMDSMI_EVENT_IOV_WS_SHUTDOWN_TIMEOUT,

1434  AMDSMI_EVENT_IOV_WS_ALREADY_SHUTDOWN,

1435  AMDSMI_EVENT_IOV_WS_INFINITE_LOOP,

1436  AMDSMI_EVENT_IOV_WS_REENTRANT_ERROR,

1437  AMDSMI_EVENT_IOV__MAX

1438 } amdsmi_event_iov_t;

1439 

1445 typedef enum {

1446  AMDSMI_EVENT_ECC_UCE = 0,

1447  AMDSMI_EVENT_ECC_CE,

1448  AMDSMI_EVENT_ECC_IN_PF_FB,

1449  AMDSMI_EVENT_ECC_IN_CRI_REG,

1450  AMDSMI_EVENT_ECC_IN_VF_CRI,

1451  AMDSMI_EVENT_ECC_REACH_THD,

1452  AMDSMI_EVENT_ECC_VF_CE,

1453  AMDSMI_EVENT_ECC_VF_UE,

1454  AMDSMI_EVENT_ECC_IN_SAME_ROW,

1455  AMDSMI_EVENT_ECC_UMC_UE,

1456  AMDSMI_EVENT_ECC_GFX_CE,

1457  AMDSMI_EVENT_ECC_GFX_UE,

1458  AMDSMI_EVENT_ECC_SDMA_CE,

1459  AMDSMI_EVENT_ECC_SDMA_UE,

1460  AMDSMI_EVENT_ECC_GFX_CE_TOTAL,

1461  AMDSMI_EVENT_ECC_GFX_UE_TOTAL,

1462  AMDSMI_EVENT_ECC_SDMA_CE_TOTAL,

1463  AMDSMI_EVENT_ECC_SDMA_UE_TOTAL,

1464  AMDSMI_EVENT_ECC_UMC_CE_TOTAL,

1465  AMDSMI_EVENT_ECC_UMC_UE_TOTAL,

1466  AMDSMI_EVENT_ECC_MMHUB_CE,

1467  AMDSMI_EVENT_ECC_MMHUB_UE,

1468  AMDSMI_EVENT_ECC_MMHUB_CE_TOTAL,

1469  AMDSMI_EVENT_ECC_MMHUB_UE_TOTAL,

1470  AMDSMI_EVENT_ECC_XGMI_WAFL_CE,

1471  AMDSMI_EVENT_ECC_XGMI_WAFL_UE,

1472  AMDSMI_EVENT_ECC_XGMI_WAFL_CE_TOTAL,

1473  AMDSMI_EVENT_ECC_XGMI_WAFL_UE_TOTAL,

1474  AMDSMI_EVENT_ECC_FATAL_ERROR,

1475  AMDSMI_EVENT_ECC_POISON_CONSUMPTION,

1476  AMDSMI_EVENT_ECC_ACA_DUMP,

1477  AMDSMI_EVENT_ECC_WRONG_SOCKET_ID,

1478  AMDSMI_EVENT_ECC_ACA_UNKNOWN_BLOCK_INSTANCE,

1479  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_CE,

1480  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_UE,

1481  AMDSMI_EVENT_ECC_UMC_CHIPLET_CE,

1482  AMDSMI_EVENT_ECC_UMC_CHIPLET_UE,

1483  AMDSMI_EVENT_ECC_GFX_CHIPLET_CE,

1484  AMDSMI_EVENT_ECC_GFX_CHIPLET_UE,

1485  AMDSMI_EVENT_ECC_SDMA_CHIPLET_CE,

1486  AMDSMI_EVENT_ECC_SDMA_CHIPLET_UE,

1487  AMDSMI_EVENT_ECC_MMHUB_CHIPLET_CE,

1488  AMDSMI_EVENT_ECC_MMHUB_CHIPLET_UE,

1489  AMDSMI_EVENT_ECC_XGMI_WAFL_CHIPLET_CE,

1490  AMDSMI_EVENT_ECC_XGMI_WAFL_CHIPLET_UE,

1491  AMDSMI_EVENT_ECC_EEPROM_ENTRIES_FOUND,

1492  AMDSMI_EVENT_ECC_UMC_DE,

1493  AMDSMI_EVENT_ECC_UMC_DE_TOTAL,

1494  AMDSMI_EVENT_ECC_UNKNOWN,

1495  AMDSMI_EVENT_ECC_EEPROM_REACH_THD,

1496  AMDSMI_EVENT_ECC_UMC_CHIPLET_DE,

1497  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_DE,

1498  AMDSMI_EVENT_ECC_EEPROM_CHK_MISMATCH,

1499  AMDSMI_EVENT_ECC_EEPROM_RESET,

1500  AMDSMI_EVENT_ECC_EEPROM_RESET_FAILED,

1501  AMDSMI_EVENT_ECC_EEPROM_APPEND,

1502  AMDSMI_EVENT_ECC_THD_CHANGED,

1503  AMDSMI_EVENT_ECC_DUP_ENTRIES,

1504  AMDSMI_EVENT_ECC_EEPROM_WRONG_HDR,

1505  AMDSMI_EVENT_ECC_EEPROM_WRONG_VER,

1506  AMDSMI_EVENT_ECC__MAX

1507 } amdsmi_event_ecc_t;

1508 

1514 typedef enum {

1515  AMDSMI_EVENT_PP_SET_DPM_POLICY_FAIL = 0,

1516  AMDSMI_EVENT_PP_ACTIVATE_DPM_POLICY_FAIL,

1517  AMDSMI_EVENT_PP_I2C_SLAVE_NOT_PRESENT,

1518  AMDSMI_EVENT_PP_THROTTLER_EVENT,

1519  AMDSMI_EVENT_PP__MAX

1520 } amdsmi_event_pp_t;

1521 

1527 typedef enum {

1528  AMDSMI_EVENT_SCHED_WORLD_SWITCH_FAIL = 0,

1529  AMDSMI_EVENT_SCHED_DISABLE_AUTO_HW_SWITCH_FAIL,

1530  AMDSMI_EVENT_SCHED_ENABLE_AUTO_HW_SWITCH_FAIL,

1531  AMDSMI_EVENT_SCHED_GFX_SAVE_REG_FAIL,

1532  AMDSMI_EVENT_SCHED_GFX_IDLE_REG_FAIL,

1533 

1534  AMDSMI_EVENT_SCHED_GFX_RUN_REG_FAIL,

1535  AMDSMI_EVENT_SCHED_GFX_LOAD_REG_FAIL,

1536  AMDSMI_EVENT_SCHED_GFX_INIT_REG_FAIL,

1537  AMDSMI_EVENT_SCHED_MM_SAVE_REG_FAIL,

1538  AMDSMI_EVENT_SCHED_MM_IDLE_REG_FAIL,

1539 

1540  AMDSMI_EVENT_SCHED_MM_RUN_REG_FAIL,

1541  AMDSMI_EVENT_SCHED_MM_LOAD_REG_FAIL,

1542  AMDSMI_EVENT_SCHED_MM_INIT_REG_FAIL,

1543  AMDSMI_EVENT_SCHED_INIT_GPU_FAIL,

1544  AMDSMI_EVENT_SCHED_RUN_GPU_FAIL,

1545 

1546  AMDSMI_EVENT_SCHED_SAVE_GPU_STATE_FAIL,

1547  AMDSMI_EVENT_SCHED_LOAD_GPU_STATE_FAIL,

1548  AMDSMI_EVENT_SCHED_IDLE_GPU_FAIL,

1549  AMDSMI_EVENT_SCHED_FINI_GPU_FAIL,

1550  AMDSMI_EVENT_SCHED_DEAD_VF,

1551 

1552  AMDSMI_EVENT_SCHED_EVENT_QUEUE_FULL,

1553  AMDSMI_EVENT_SCHED_SHUTDOWN_VF_FAIL,

1554  AMDSMI_EVENT_SCHED_RESET_VF_NUM_FAIL,

1555  AMDSMI_EVENT_SCHED_IGNORE_EVENT,

1556  AMDSMI_EVENT_SCHED_PF_SWITCH_FAIL,

1557  AMDSMI_EVENT_SCHED__MAX

1558 } amdsmi_event_sched_t;

1559 

1565 typedef enum {

1566  AMDSMI_EVENT_VF_ATOMBIOS_INIT_FAIL = 0,

1567  AMDSMI_EVENT_VF_NO_VBIOS,

1568  AMDSMI_EVENT_VF_GPU_POST_ERROR,

1569  AMDSMI_EVENT_VF_ATOMBIOS_GET_CLOCK_FAIL,

1570  AMDSMI_EVENT_VF_FENCE_INIT_FAIL,

1571  AMDSMI_EVENT_VF_AMDGPU_INIT_FAIL,

1572  AMDSMI_EVENT_VF_IB_INIT_FAIL,

1573  AMDSMI_EVENT_VF_AMDGPU_LATE_INIT_FAIL,

1574  AMDSMI_EVENT_VF_ASIC_RESUME_FAIL,

1575  AMDSMI_EVENT_VF_GPU_RESET_FAIL,

1576  AMDSMI_EVENT_VF__MAX

1577 } amdsmi_event_vf_max_t;

1578 

1584 typedef enum {

1585  AMDSMI_EVENT_VBIOS_INVALID = 0,

1586  AMDSMI_EVENT_VBIOS_IMAGE_MISSING,

1587  AMDSMI_EVENT_VBIOS_CHECKSUM_ERR,

1588  AMDSMI_EVENT_VBIOS_POST_FAIL,

1589  AMDSMI_EVENT_VBIOS_READ_FAIL,

1590 

1591  AMDSMI_EVENT_VBIOS_READ_IMG_HEADER_FAIL,

1592  AMDSMI_EVENT_VBIOS_READ_IMG_SIZE_FAIL,

1593  AMDSMI_EVENT_VBIOS_GET_FW_INFO_FAIL,

1594  AMDSMI_EVENT_VBIOS_GET_TBL_REVISION_FAIL,

1595  AMDSMI_EVENT_VBIOS_PARSER_TBL_FAIL,

1596 

1597  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_FAIL,

1598  AMDSMI_EVENT_VBIOS_TIMEOUT,

1599  AMDSMI_EVENT_VBIOS_HASH_INVALID,

1600  AMDSMI_EVENT_VBIOS_HASH_UPDATED,

1601  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_BINARY_CHECKSUM_FAIL,

1602  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_TABLE_CHECKSUM_FAIL,

1603  AMDSMI_EVENT_VBIOS__MAX

1604 } amdsmi_event_vbios_t;

1605 

1611 typedef enum {

1612  AMDSMI_EVENT_GUARD_RESET_FAIL = 0,

1613  AMDSMI_EVENT_GUARD_EVENT_OVERFLOW,

1614  AMDSMI_EVENT_GUARD__MAX

1615 } amdsmi_event_guard_t;

1616 

1622 typedef enum {

1623  AMDSMI_EVENT_GPUMON_INVALID_OPTION = 0,

1624  AMDSMI_EVENT_GPUMON_INVALID_VF_INDEX,

1625  AMDSMI_EVENT_GPUMON_INVALID_FB_SIZE,

1626  AMDSMI_EVENT_GPUMON_NO_SUITABLE_SPACE,

1627  AMDSMI_EVENT_GPUMON_NO_AVAILABLE_SLOT,

1628 

1629  AMDSMI_EVENT_GPUMON_OVERSIZE_ALLOCATION,

1630  AMDSMI_EVENT_GPUMON_OVERLAPPING_FB,

1631  AMDSMI_EVENT_GPUMON_INVALID_GFX_TIMESLICE,

1632  AMDSMI_EVENT_GPUMON_INVALID_MM_TIMESLICE,

1633  AMDSMI_EVENT_GPUMON_INVALID_GFX_PART,

1634 

1635  AMDSMI_EVENT_GPUMON_VF_BUSY,

1636  AMDSMI_EVENT_GPUMON_INVALID_VF_NUM,

1637  AMDSMI_EVENT_GPUMON_NOT_SUPPORTED,

1638  AMDSMI_EVENT_GPUMON__MAX

1639 } amdsmi_event_gpumon_t;

1640 

1646 typedef enum {

1647  AMDSMI_EVENT_MMSCH_IGNORED_JOB = 0,

1648  AMDSMI_EVENT_MMSCH_UNSUPPORTED_VCN_FW,

1649  AMDSMI_EVENT_MMSCH__MAX

1650 } amdsmi_event_mmsch_t;

1651 

1657 typedef enum {

1658  AMDSMI_EVENT_XGMI_TOPOLOGY_UPDATE_FAILED = 0,

1659  AMDSMI_EVENT_XGMI_TOPOLOGY_HW_INIT_UPDATE,

1660  AMDSMI_EVENT_XGMI_TOPOLOGY_UPDATE_DONE,

1661  AMDSMI_EVENT_XGMI_FB_SHARING_SETTING_ERROR,

1662  AMDSMI_EVENT_XGMI_FB_SHARING_SETTING_RESET,

1663  AMDSMI_EVENT_XGMI__MAX

1664 } amdsmi_event_xgmi_t;

1665 

1671 typedef enum {

1672  AMDSMI_EVENT_THROTTLER_PROCHOT = 0,

1673  AMDSMI_EVENT_THROTTLER_SOCKET,

1674  AMDSMI_EVENT_THROTTLER_VR,

1675  AMDSMI_EVENT_THROTTLER_HBM

1676 } amdsmi_pp_throttler_type_t;

1677 

1683 typedef enum {

1684  AMDSMI_RAS_ECC_SUPPORT_PARITY = (1 << 0),

1685  AMDSMI_RAS_ECC_SUPPORT_CORRECTABLE = (1 << 1),

1686  AMDSMI_RAS_ECC_SUPPORT_UNCORRECTABLE = (1 << 2),

1687  AMDSMI_RAS_ECC_SUPPORT_POISON = (1 << 3)

1688 } amdsmi_ecc_correction_schema_support_t;

1689 

1695 typedef enum {

1696  AMDSMI_GUEST_FW_ID_VCE = 0,

1697  AMDSMI_GUEST_FW_ID_UVD,

1698  AMDSMI_GUEST_FW_ID_MC,

1699  AMDSMI_GUEST_FW_ID_ME,

1700  AMDSMI_GUEST_FW_ID_PFP,

1701  AMDSMI_GUEST_FW_ID_CE,

1702  AMDSMI_GUEST_FW_ID_RLC,

1703  AMDSMI_GUEST_FW_ID_RLC_SRLC,

1704  AMDSMI_GUEST_FW_ID_RLC_SRLG,

1705  AMDSMI_GUEST_FW_ID_RLC_SRLS,

1706  AMDSMI_GUEST_FW_ID_MEC,

1707  AMDSMI_GUEST_FW_ID_MEC2,

1708  AMDSMI_GUEST_FW_ID_SOS,

1709  AMDSMI_GUEST_FW_ID_ASD,

1710  AMDSMI_GUEST_FW_ID_TA_RAS,

1711  AMDSMI_GUEST_FW_ID_TA_XGMI,

1712  AMDSMI_GUEST_FW_ID_SMC,

1713  AMDSMI_GUEST_FW_ID_SDMA,

1714  AMDSMI_GUEST_FW_ID_SDMA2,

1715  AMDSMI_GUEST_FW_ID_VCN,

1716  AMDSMI_GUEST_FW_ID_DMCU,

1717  AMDSMI_GUEST_FW_ID__MAX

1718 } amdsmi_guest_fw_engine_id_t;

1719 

1725 typedef enum {

1726  AMDSMI_VF_CONFIG_FB_SIZE_SET = 0,

1727  AMDSMI_VF_CONFIG_FB_OFFSET_SET,

1728  AMDSMI_VF_CONFIG_GFX_TIMESLICE_US_SET,

1729  AMDSMI_VF_CONFIG_ENG_COMPUTE_BW_SET,

1730  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_FLR_SET,

1731  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_EXCL_MOD_SET,

1732  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_EXCL_TIMEOUT_SET,

1733  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_ALL_INT_SET,

1734  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_UVD_SET,

1735  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCE_SET,

1736  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_UVD1_SET,

1737  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCN_SET,

1738  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCN1_SET,

1739  AMDSMI_VF_CONFIG__MAX

1740 } amdsmi_vf_config_flags_t;

1741 

1747 typedef enum {

1748  AMDSMI_VF_STATE_UNAVAILABLE,

1749  AMDSMI_VF_STATE_AVAILABLE,

1750  AMDSMI_VF_STATE_ACTIVE,

1751  AMDSMI_VF_STATE_SUSPENDED,

1752  AMDSMI_VF_STATE_FULLACCESS,

1753  AMDSMI_VF_STATE_DEFAULT_AVAILABLE,

1754 } amdsmi_vf_sched_state_t;

1755 

1761 typedef enum {

1762  AMDSMI_GUARD_EVENT_FLR,

1763  AMDSMI_GUARD_EVENT_EXCLUSIVE_MOD,

1764  AMDSMI_GUARD_EVENT_EXCLUSIVE_TIMEOUT,

1765  AMDSMI_GUARD_EVENT_ALL_INT,

1766  AMDSMI_GUARD_EVENT_RAS_ERR_COUNT,

1767  AMDSMI_GUARD_EVENT_RAS_CPER_DUMP,

1768  AMDSMI_GUARD_EVENT_RAS_BAD_PAGES,

1769  AMDSMI_GUARD_EVENT__MAX

1770 } amdsmi_guard_type_t;

1771 

1777 typedef enum {

1778  AMDSMI_DRIVER_LIBGV,

1779  AMDSMI_DRIVER_KMD,

1780  AMDSMI_DRIVER_AMDGPUV,

1781  AMDSMI_DRIVER_AMDGPU,

1782  AMDSMI_DRIVER_VMWGPUV,

1783  AMDSMI_DRIVER__MAX,

1784 } amdsmi_driver_t;

1785 

1791 typedef enum {

1792  AMDSMI_GUARD_STATE_NORMAL = 0,

1793  AMDSMI_GUARD_STATE_FULL = 1,

1794  AMDSMI_GUARD_STATE_OVERFLOW = 2,

1795 } amdsmi_guard_state_t;

1796 

1802 typedef enum {

1803  AMDSMI_SCHED_BLOCK_GFX = 0x0,

1804  AMDSMI_SCHED_BLOCK_UVD = 0x1,

1805  AMDSMI_SCHED_BLOCK_VCE = 0x2,

1806  AMDSMI_SCHED_BLOCK_UVD1 = 0x3,

1807  AMDSMI_SCHED_BLOCK_VCN = 0x4,

1808  AMDSMI_SCHED_BLOCK_VCN1 = 0x5,

1809 } amdsmi_sched_block_t;

1810 

1816 typedef enum {

1817  AMDSMI_GUEST_FW_LOAD_STATUS_OK = 0,

1818  AMDSMI_GUEST_FW_LOAD_STATUS_OBSOLETE_FW = 1,

1819  AMDSMI_GUEST_FW_LOAD_STATUS_BAD_SIG = 2,

1820  AMDSMI_GUEST_FW_LOAD_STATUS_FW_LOAD_FAIL = 3,

1821  AMDSMI_GUEST_FW_LOAD_STATUS_ERR_GENERIC = 4

1822 } amdsmi_guest_fw_load_status_t;

1823 

1829 typedef enum {

1830  AMDSMI_XGMI_FB_SHARING_MODE_CUSTOM = 0,

1831  AMDSMI_XGMI_FB_SHARING_MODE_1 = 1,

1832  AMDSMI_XGMI_FB_SHARING_MODE_2 = 2,

1833  AMDSMI_XGMI_FB_SHARING_MODE_4 = 4,

1834  AMDSMI_XGMI_FB_SHARING_MODE_8 = 8,

1835  AMDSMI_XGMI_FB_SHARING_MODE_UNKNOWN = 0xFFFFFFFF

1836 } amdsmi_xgmi_fb_sharing_mode_t;

1837 

1843 typedef enum {

1844  AMDSMI_PROFILE_CAPABILITY_MEMORY = 0,

1845  AMDSMI_PROFILE_CAPABILITY_ENCODE = 1,

1846  AMDSMI_PROFILE_CAPABILITY_DECODE = 2,

1847  AMDSMI_PROFILE_CAPABILITY_COMPUTE = 3,

1848  AMDSMI_PROFILE_CAPABILITY__MAX,

1849 } amdsmi_profile_capability_type_t;

1850 

1856 typedef enum {

1857  AMDSMI_METRIC_CATEGORY_ACC_COUNTER,

1858  AMDSMI_METRIC_CATEGORY_FREQUENCY,

1859  AMDSMI_METRIC_CATEGORY_ACTIVITY,

1860  AMDSMI_METRIC_CATEGORY_TEMPERATURE,

1861  AMDSMI_METRIC_CATEGORY_POWER,

1862  AMDSMI_METRIC_CATEGORY_ENERGY,

1863  AMDSMI_METRIC_CATEGORY_THROTTLE,

1864  AMDSMI_METRIC_CATEGORY_PCIE,

1865  AMDSMI_METRIC_CATEGORY_STATIC,

1866  AMDSMI_METRIC_CATEGORY_SYS_ACC_COUNTER,

1867  AMDSMI_METRIC_CATEGORY_SYS_BASEBOARD_TEMP,

1868  AMDSMI_METRIC_CATEGORY_SYS_GPUBOARD_TEMP,

1869  AMDSMI_METRIC_CATEGORY_UNKNOWN

1870 } amdsmi_metric_category_t;

1871 

1877 typedef enum {

1878  AMDSMI_METRIC_NAME_METRIC_ACC_COUNTER,

1879  AMDSMI_METRIC_NAME_FW_TIMESTAMP,

1880  AMDSMI_METRIC_NAME_CLK_GFX,

1881  AMDSMI_METRIC_NAME_CLK_SOC,

1882  AMDSMI_METRIC_NAME_CLK_MEM,

1883  AMDSMI_METRIC_NAME_CLK_VCLK,

1884  AMDSMI_METRIC_NAME_CLK_DCLK,

1885 

1886  AMDSMI_METRIC_NAME_USAGE_GFX,

1887  AMDSMI_METRIC_NAME_USAGE_MEM,

1888  AMDSMI_METRIC_NAME_USAGE_MM,

1889  AMDSMI_METRIC_NAME_USAGE_VCN,

1890  AMDSMI_METRIC_NAME_USAGE_JPEG,

1891 

1892  AMDSMI_METRIC_NAME_VOLT_GFX,

1893  AMDSMI_METRIC_NAME_VOLT_SOC,

1894  AMDSMI_METRIC_NAME_VOLT_MEM,

1895 

1896  AMDSMI_METRIC_NAME_TEMP_HOTSPOT_CURR,

1897  AMDSMI_METRIC_NAME_TEMP_HOTSPOT_LIMIT,

1898  AMDSMI_METRIC_NAME_TEMP_MEM_CURR,

1899  AMDSMI_METRIC_NAME_TEMP_MEM_LIMIT,

1900  AMDSMI_METRIC_NAME_TEMP_VR_CURR,

1901  AMDSMI_METRIC_NAME_TEMP_SHUTDOWN,

1902 

1903  AMDSMI_METRIC_NAME_POWER_CURR,

1904  AMDSMI_METRIC_NAME_POWER_LIMIT,

1905 

1906  AMDSMI_METRIC_NAME_ENERGY_SOCKET,

1907  AMDSMI_METRIC_NAME_ENERGY_CCD,

1908  AMDSMI_METRIC_NAME_ENERGY_XCD,

1909  AMDSMI_METRIC_NAME_ENERGY_AID,

1910  AMDSMI_METRIC_NAME_ENERGY_MEM,

1911 

1912  AMDSMI_METRIC_NAME_THROTTLE_SOCKET_ACTIVE,

1913  AMDSMI_METRIC_NAME_THROTTLE_VR_ACTIVE,

1914  AMDSMI_METRIC_NAME_THROTTLE_MEM_ACTIVE,

1915 

1916  AMDSMI_METRIC_NAME_PCIE_BANDWIDTH,

1917  AMDSMI_METRIC_NAME_PCIE_L0_TO_RECOVERY_COUNT,

1918  AMDSMI_METRIC_NAME_PCIE_REPLAY_COUNT,

1919  AMDSMI_METRIC_NAME_PCIE_REPLAY_ROLLOVER_COUNT,

1920  AMDSMI_METRIC_NAME_PCIE_NAK_SENT_COUNT,

1921  AMDSMI_METRIC_NAME_PCIE_NAK_RECEIVED_COUNT,

1922 

1923  AMDSMI_METRIC_NAME_CLK_GFX_MAX_LIMIT,

1924  AMDSMI_METRIC_NAME_CLK_SOC_MAX_LIMIT,

1925  AMDSMI_METRIC_NAME_CLK_MEM_MAX_LIMIT,

1926  AMDSMI_METRIC_NAME_CLK_VCLK_MAX_LIMIT,

1927  AMDSMI_METRIC_NAME_CLK_DCLK_MAX_LIMIT,

1928 

1929  AMDSMI_METRIC_NAME_CLK_GFX_MIN_LIMIT,

1930  AMDSMI_METRIC_NAME_CLK_SOC_MIN_LIMIT,

1931  AMDSMI_METRIC_NAME_CLK_MEM_MIN_LIMIT,

1932  AMDSMI_METRIC_NAME_CLK_VCLK_MIN_LIMIT,

1933  AMDSMI_METRIC_NAME_CLK_DCLK_MIN_LIMIT,

1934 

1935  AMDSMI_METRIC_NAME_CLK_GFX_LOCKED,

1936 

1937  AMDSMI_METRIC_NAME_CLK_GFX_DS_DISABLED,

1938  AMDSMI_METRIC_NAME_CLK_MEM_DS_DISABLED,

1939  AMDSMI_METRIC_NAME_CLK_SOC_DS_DISABLED,

1940  AMDSMI_METRIC_NAME_CLK_VCLK_DS_DISABLED,

1941  AMDSMI_METRIC_NAME_CLK_DCLK_DS_DISABLED,

1942 

1943  AMDSMI_METRIC_NAME_PCIE_LINK_SPEED,

1944  AMDSMI_METRIC_NAME_PCIE_LINK_WIDTH,

1945 

1946  AMDSMI_METRIC_NAME_DRAM_BANDWIDTH,

1947  AMDSMI_METRIC_NAME_MAX_DRAM_BANDWIDTH,

1948 

1949  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_PPT,

1950  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_THM,

1951  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_TOTAL,

1952  AMDSMI_METRIC_NAME_GFX_CLK_LOW_UTILIZATION,

1953  AMDSMI_METRIC_NAME_INPUT_TELEMETRY_VOLTAGE,

1954  AMDSMI_METRIC_NAME_PLDM_VERSION,

1955  AMDSMI_METRIC_NAME_TEMP_XCD,

1956  AMDSMI_METRIC_NAME_TEMP_AID,

1957  AMDSMI_METRIC_NAME_TEMP_HBM,

1958 

1959  AMDSMI_METRIC_NAME_SYS_METRIC_ACC_COUNTER,

1960  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA,

1961  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FRONT,

1962  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_BACK,

1963  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_OAM7,

1964  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_IBC,

1965  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_UFPGA,

1966  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_OAM1,

1967  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_0_1_HSC,

1968  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_2_3_HSC,

1969  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_4_5_HSC,

1970  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_6_7_HSC,

1971  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA_0V72_VR,

1972  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA_3V3_VR,

1973  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR,

1974  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR,

1975  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_0_1_0V9_VR,

1976  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_4_5_0V9_VR,

1977  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_2_3_0V9_VR,

1978  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_6_7_0V9_VR,

1979  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR,

1980  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR,

1981  AMDSMI_METRIC_NAME_SYSTEM_TEMP_IBC_HSC,

1982  AMDSMI_METRIC_NAME_SYSTEM_TEMP_IBC,

1983  AMDSMI_METRIC_NAME_NODE_TEMP_RETIMER,

1984  AMDSMI_METRIC_NAME_NODE_TEMP_IBC_TEMP,

1985  AMDSMI_METRIC_NAME_NODE_TEMP_IBC_2_TEMP,

1986  AMDSMI_METRIC_NAME_NODE_TEMP_VDD18_VR_TEMP,

1987  AMDSMI_METRIC_NAME_NODE_TEMP_04_HBM_B_VR_TEMP,

1988  AMDSMI_METRIC_NAME_NODE_TEMP_04_HBM_D_VR_TEMP,

1989  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD0,

1990  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD1,

1991  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD2,

1992  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD3,

1993  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOC_A,

1994  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOC_C,

1995  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOCIO_A,

1996  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOCIO_C,

1997  AMDSMI_METRIC_NAME_VR_TEMP_VDD_085_HBM,

1998  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_11_HBM_B,

1999  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_11_HBM_D,

2000  AMDSMI_METRIC_NAME_VR_TEMP_VDD_USR,

2001  AMDSMI_METRIC_NAME_VR_TEMP_VDDIO_11_E32,

2002 

2003  AMDSMI_METRIC_NAME_UNKNOWN

2004 } amdsmi_metric_name_t;

2005 

2011 typedef enum {

2012  AMDSMI_METRIC_UNIT_COUNTER,

2013  AMDSMI_METRIC_UNIT_UINT,

2014  AMDSMI_METRIC_UNIT_BOOL,

2015  AMDSMI_METRIC_UNIT_MHZ,

2016  AMDSMI_METRIC_UNIT_PERCENT,

2017  AMDSMI_METRIC_UNIT_MILLIVOLT,

2018  AMDSMI_METRIC_UNIT_CELSIUS,

2019  AMDSMI_METRIC_UNIT_WATT,

2020  AMDSMI_METRIC_UNIT_JOULE,

2021  AMDSMI_METRIC_UNIT_GBPS,

2022  AMDSMI_METRIC_UNIT_MBITPS,

2023  AMDSMI_METRIC_UNIT_PCIE_GEN,

2024  AMDSMI_METRIC_UNIT_PCIE_LANES,

2025  AMDSMI_METRIC_UNIT_15_625_MILLIJOULE,

2026  AMDSMI_METRIC_UNIT_UNKNOWN

2027 } amdsmi_metric_unit_t;

2028 

2034 typedef enum {

2035  AMDSMI_METRIC_TYPE_COUNTER = (1 << 0),

2036  AMDSMI_METRIC_TYPE_CHIPLET = (1 << 1),

2037  AMDSMI_METRIC_TYPE_INST = (1 << 2),

2038  AMDSMI_METRIC_TYPE_ACC = (1 << 3)

2039 } amdsmi_metric_type_t;

2040 

2041 typedef enum {

2042  AMDSMI_METRIC_RES_GROUP_UNKNOWN,

2043  AMDSMI_METRIC_RES_GROUP_NA,

2044  AMDSMI_METRIC_RES_GROUP_GPU,

2045  AMDSMI_METRIC_RES_GROUP_XCP,

2046  AMDSMI_METRIC_RES_GROUP_AID,

2047  AMDSMI_METRIC_RES_GROUP_MID,

2048  AMDSMI_METRIC_RES_GROUP_SYSTEM

2049 } amdsmi_metric_res_group_t;

2050 

2051 typedef enum {

2052  AMDSMI_METRIC_RES_SUBGROUP_UNKNOWN,

2053  AMDSMI_METRIC_RES_SUBGROUP_NA,

2054  AMDSMI_METRIC_RES_SUBGROUP_XCC,

2055  AMDSMI_METRIC_RES_SUBGROUP_ENGINE,

2056  AMDSMI_METRIC_RES_SUBGROUP_HBM,

2057  AMDSMI_METRIC_RES_SUBGROUP_BASEBOARD,

2058  AMDSMI_METRIC_RES_SUBGROUP_GPUBOARD

2059 } amdsmi_metric_res_subgroup_t;

2060 

2061 typedef enum {

2062  AMDSMI_VF_MODE_1 = (1U << 1),

2063  AMDSMI_VF_MODE_2 = (1U << 2),

2064  AMDSMI_VF_MODE_4 = (1U << 4),

2065  AMDSMI_VF_MODE_8 = (1U << 8),

2066  AMDSMI_VF_MODE_ALL = (AMDSMI_VF_MODE_1 | AMDSMI_VF_MODE_2 | AMDSMI_VF_MODE_4 | AMDSMI_VF_MODE_8)

2067 } amdsmi_vf_mode_t;

2068 

2074 typedef enum {

2075  AMDSMI_DRIVER_MODEL_TYPE_WDDM = 0,

2076  AMDSMI_DRIVER_MODEL_TYPE_WDM = 1,

2077  AMDSMI_DRIVER_MODEL_TYPE_MCDM = 2,

2078  AMDSMI_DRIVER_MODEL_TYPE__MAX = 3,

2079 } amdsmi_driver_model_type_t;

2080 

2086 typedef struct {

2087  uint64_t handle;

2088 } amdsmi_vf_handle_t;

2089 

2095 typedef struct {

2096  amdsmi_vf_handle_t fcn_id;

2097  uint64_t dev_id;

2098  uint64_t timestamp;

2099  uint64_t data;

2100  uint32_t category;

2101  uint32_t subcode;

2102  uint32_t level;

2103  char date[AMDSMI_MAX_DATE_STRING_LENGTH];

2104  char message[AMDSMI_MAX_STRING_LENGTH];

2105  amdsmi_processor_handle processor_handle;

2106  uint64_t reserved[37];

2107 } amdsmi_event_entry_t;

2108 

2114 typedef struct {

2115  uint32_t version;

2116 } amdsmi_handshake_t;

2117 

2123 typedef struct {

2124  uint32_t total_fb_size;

2125  uint32_t pf_fb_reserved;

2126  uint32_t pf_fb_offset;

2127  uint32_t fb_alignment;

2128  uint32_t max_vf_fb_usable;

2129  uint32_t min_vf_fb_usable;

2130  uint64_t reserved[5];

2131 } amdsmi_pf_fb_info_t;

2132 

2138 typedef struct {

2139  uint32_t fb_offset;

2140  uint32_t fb_size;

2141  uint64_t reserved[3];

2142 } amdsmi_vf_fb_info_t;

2143 

2149 typedef struct {

2150  amdsmi_vf_handle_t id;

2151  amdsmi_vf_fb_info_t fb;

2152  uint64_t reserved[3];

2153 } amdsmi_partition_info_t;

2154 

2160 typedef struct {

2161  uint8_t enabled;

2162  struct {

2163  amdsmi_guard_state_t state;

2164  /* amount of monitor event after enabled */

2165  uint32_t amount;

2166  /* threshold of events in the interval(seconds) */

2167  uint64_t interval;

2168  uint32_t threshold;

2169  /* current number of events in the interval*/

2170  uint32_t active;

2171  uint32_t reserved[4];

2172  } guard[AMDSMI_GUARD_EVENT__MAX];

2173  uint32_t reserved[6];

2174 } amdsmi_guard_info_t;

2175 

2181 typedef struct {

2182  amdsmi_vf_fb_info_t fb;

2183  uint32_t gfx_timeslice;

2184  uint64_t reserved[27];

2185 } amdsmi_vf_info_t;

2186 

2192 typedef struct {

2193  uint64_t flr_count;

2194  uint64_t boot_up_time;

2195  uint64_t shutdown_time;

2196  uint64_t reset_time;

2197  amdsmi_vf_sched_state_t state;

2198  char last_boot_start[AMDSMI_MAX_STRING_LENGTH];

2199  char last_boot_end[AMDSMI_MAX_STRING_LENGTH];

2200  char last_shutdown_start[AMDSMI_MAX_STRING_LENGTH];

2201  char last_shutdown_end[AMDSMI_MAX_STRING_LENGTH];

2202  char last_reset_start[AMDSMI_MAX_STRING_LENGTH];

2203  char last_reset_end[AMDSMI_MAX_STRING_LENGTH];

2204  char current_active_time[AMDSMI_MAX_STRING_LENGTH];

2205  char current_running_time[AMDSMI_MAX_STRING_LENGTH];

2206  char total_active_time[AMDSMI_MAX_STRING_LENGTH];

2207  char total_running_time[AMDSMI_MAX_STRING_LENGTH];

2208  uint64_t reserved[11];

2209 } amdsmi_sched_info_t;

2210 

2216 typedef struct {

2217  amdsmi_sched_info_t sched;

2218  amdsmi_guard_info_t guard;

2219  uint64_t reserved[8];

2220 } amdsmi_vf_data_t;

2221 

2227 typedef struct {

2228  uint64_t total;

2229  uint64_t available;

2230  uint64_t optimal;

2231  uint64_t min_value;

2232  uint64_t max_value;

2233  uint64_t reserved[2];

2234 } amdsmi_profile_caps_info_t;

2235 

2241 typedef struct {

2242  uint8_t profile_count;

2243  uint8_t current_profile_index;

2244  struct {

2245  uint32_t vf_count;

2246  amdsmi_profile_caps_info_t profile_caps[AMDSMI_PROFILE_CAPABILITY__MAX];

2247  } profiles[AMDSMI_MAX_PROFILE_COUNT];

2248  uint32_t reserved[6];

2249 } amdsmi_profile_info_t;

2250 

2256 typedef struct {

2257  char driver_version[AMDSMI_MAX_STRING_LENGTH];

2258  uint32_t fb_usage;

2259  uint64_t reserved[23];

2260 } amdsmi_guest_data_t;

2261 

2267 typedef struct {

2268  uint32_t dfc_fw_version;

2269  uint32_t dfc_fw_total_entries;

2270  uint32_t dfc_gart_wr_guest_min;

2271  uint32_t dfc_gart_wr_guest_max;

2272  uint32_t reserved[12];

2273 } amdsmi_dfc_fw_header_t;

2274 

2280 typedef struct {

2281  uint32_t oldest;

2282  uint32_t latest;

2283 } amdsmi_dfc_fw_white_list_t;

2284 

2290 typedef struct {

2291  uint8_t ta_uuid[AMDSMI_MAX_UUID_ELEMENTS];

2292 } amdsmi_dfc_fw_ta_uuid_t;

2293 

2299 typedef struct {

2300  uint32_t dfc_fw_type;

2301  uint32_t verification_enabled;

2302  uint32_t customer_ordinal;

2303  uint32_t reserved[13];

2304  union {

2305  amdsmi_dfc_fw_white_list_t white_list[AMDSMI_MAX_WHITE_LIST_ELEMENTS];

2306  amdsmi_dfc_fw_ta_uuid_t ta_white_list[AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS];

2307  };

2308  uint32_t black_list[AMDSMI_MAX_BLACK_LIST_ELEMENTS];

2309 } amdsmi_dfc_fw_data_t;

2310 

2316 typedef struct {

2317  amdsmi_dfc_fw_header_t header;

2318  amdsmi_dfc_fw_data_t data[AMDSMI_DFC_FW_NUMBER_OF_ENTRIES];

2319 } amdsmi_dfc_fw_t;

2320 

2330 typedef struct {

2331  uint64_t retired_page;

2332  uint64_t ts;

2333  unsigned char err_type;

2334  union {

2335  unsigned char bank;

2336  unsigned char cu;

2337  };

2338  unsigned char mem_channel;

2339  unsigned char mcumc_id;

2340  uint32_t reserved[3];

2341 } amdsmi_eeprom_table_record_t;

2342 

2348 typedef struct {

2349  uint64_t timestamp;

2350  uint32_t vf_idx;

2351  uint32_t fw_id;

2352  uint16_t status;

2353  uint32_t reserved[3];

2354 } amdsmi_fw_load_error_record_t;

2355 

2361 typedef struct {

2362  uint8_t num_err_records;

2363  amdsmi_fw_load_error_record_t err_records[AMDSMI_MAX_ERR_RECORDS];

2364  uint64_t reserved[7];

2365 } amdsmi_fw_error_record_t;

2366 

2372 typedef struct {

2373  uint64_t weight;

2374  amdsmi_link_status_t link_status;

2375  amdsmi_link_type_t link_type;

2376  uint8_t num_hops;

2377  uint8_t fb_sharing;

2378  uint32_t reserved[10];

2379 } amdsmi_link_topology_t;

2380 

2386 typedef struct {

2387  uint32_t count;

2388  amdsmi_processor_handle processor_list[AMDSMI_MAX_DEVICES];

2389  uint64_t reserved[15];

2390 } amdsmi_topology_nearest_t;

2391 

2397 typedef union {

2398  struct cap_ {

2399  uint32_t mode_custom_cap :1;

2400  uint32_t mode_1_cap :1;

2401  uint32_t mode_2_cap :1;

2402  uint32_t mode_4_cap :1;

2403  uint32_t mode_8_cap :1;

2404  uint32_t reserved :27;

2405  } cap;

2406  uint32_t xgmi_fb_sharing_cap_mask;

2407 } amdsmi_xgmi_fb_sharing_caps_t;

2408 

2414 typedef struct {

2415  amdsmi_metric_unit_t unit;

2416  amdsmi_metric_name_t name;

2417  amdsmi_metric_category_t category;

2418  uint32_t flags;

2419  uint32_t vf_mask;

2420  uint64_t val;

2421  amdsmi_metric_res_group_t res_group;

2422  amdsmi_metric_res_subgroup_t res_subgroup;

2423  uint32_t res_instance;

2424  uint32_t reserved[5];

2425 } amdsmi_metric_t;

2426 

2432 typedef struct {

2433  uint32_t major;

2434  uint32_t minor;

2435  uint32_t release;

2436 } amdsmi_version_t;

2437 

2438 typedef struct {

2439  amdsmi_accelerator_partition_profile_t profile;

2440  uint32_t vf_mode;

2441  uint64_t reserved[6];

2442 } amdsmi_accelerator_partition_profile_global_t;

2443 

2444 typedef struct {

2445  uint32_t num_profiles;

2446  uint32_t num_resource_profiles;

2447  amdsmi_accelerator_partition_resource_profile_t resource_profiles[AMDSMI_MAX_CP_PROFILE_RESOURCES];

2448  uint32_t default_profile_index;

2449  amdsmi_accelerator_partition_profile_global_t profiles[AMDSMI_MAX_ACCELERATOR_PROFILE];

2450  uint64_t reserved[30];

2451 } amdsmi_accelerator_partition_profile_config_global_t;

2452 

2458 #define AMDSMI_MAX_NIC_PORTS 32

2459 #define AMDSMI_MAX_NIC_RDMA_DEV 32

2460 #define AMDSMI_MAX_NIC_FW 16

2461 

2469 typedef struct {

2470  char name[AMDSMI_MAX_STRING_LENGTH];

2471  uint64_t value;

2472 } amdsmi_nic_stat_t;

2473 

2479 typedef struct {

2480  uint16_t vendor_id;

2481  uint16_t subvendor_id;

2482  uint16_t device_id;

2483  uint16_t subsystem_id;

2484  uint8_t revision;

2485  char permanent_address[AMDSMI_MAX_STRING_LENGTH];

2486  char product_name[AMDSMI_MAX_STRING_LENGTH];

2487  char part_number[AMDSMI_MAX_STRING_LENGTH];

2488  char serial_number[AMDSMI_MAX_STRING_LENGTH];

2489  char vendor_name[AMDSMI_MAX_STRING_LENGTH];

2490 } amdsmi_nic_asic_info_t;

2491 

2497 typedef struct {

2498  amdsmi_bdf_t bdf;

2499  uint8_t max_pcie_width;

2500  uint32_t max_pcie_speed;

2501  char pcie_interface_version[AMDSMI_MAX_STRING_LENGTH];

2502  char slot_type[AMDSMI_MAX_STRING_LENGTH];

2503 } amdsmi_nic_bus_info_t;

2504 

2510 typedef struct {

2511  uint8_t node;

2512  char affinity[AMDSMI_MAX_STRING_LENGTH];

2513 } amdsmi_nic_numa_info_t;

2514 

2520 typedef struct {

2521  char name[AMDSMI_MAX_STRING_LENGTH];

2522  char version[AMDSMI_MAX_STRING_LENGTH];

2523 } amdsmi_nic_fw_t;

2524 

2530 typedef struct {

2531  uint32_t num_fw;

2532  amdsmi_nic_fw_t fw[AMDSMI_MAX_NIC_FW];

2533 } amdsmi_nic_fw_info_t;

2534 

2557 typedef struct {

2558  amdsmi_bdf_t bdf;

2559  uint32_t port_num;

2560  char type[AMDSMI_MAX_STRING_LENGTH];

2561  char flavour[AMDSMI_MAX_STRING_LENGTH];

2562  char netdev[AMDSMI_MAX_STRING_LENGTH];

2563  uint8_t ifindex;

2564  char mac_address[AMDSMI_MAX_STRING_LENGTH];

2565  uint8_t carrier;

2566  uint16_t mtu;

2567  char link_state[AMDSMI_MAX_STRING_LENGTH];

2568  uint32_t link_speed;

2569  uint32_t active_fec;

2570  char autoneg[AMDSMI_MAX_STRING_LENGTH];

2571  char pause_autoneg[AMDSMI_MAX_STRING_LENGTH];

2572  char pause_rx[AMDSMI_MAX_STRING_LENGTH];

2573  char pause_tx[AMDSMI_MAX_STRING_LENGTH];

2574 } amdsmi_nic_port_t;

2575 

2581 typedef struct {

2582  uint32_t num_ports;

2583  amdsmi_nic_port_t ports[AMDSMI_MAX_NIC_PORTS];

2584 } amdsmi_nic_port_info_t;

2585 

2591 typedef struct {

2592  char name[AMDSMI_MAX_STRING_LENGTH];

2593  char version[AMDSMI_MAX_STRING_LENGTH];

2594 } amdsmi_nic_driver_info_t;

2595 

2601 typedef struct {

2602  char netdev[AMDSMI_MAX_STRING_LENGTH];

2603  char state[AMDSMI_MAX_STRING_LENGTH];

2604  uint8_t rdma_port;

2605  uint16_t max_mtu;

2606  uint16_t active_mtu;

2607 } amdsmi_nic_rdma_port_info_t;

2608 

2614 typedef struct {

2615  char rdma_dev[AMDSMI_MAX_STRING_LENGTH];

2616  char node_guid[AMDSMI_MAX_STRING_LENGTH];

2617  char node_type[AMDSMI_MAX_STRING_LENGTH];

2618  char sys_image_guid[AMDSMI_MAX_STRING_LENGTH];

2619  char fw_ver[AMDSMI_MAX_STRING_LENGTH];

2620  uint8_t num_rdma_ports;

2621  amdsmi_nic_rdma_port_info_t rdma_port_info[AMDSMI_MAX_NIC_PORTS];

2622 } amdsmi_nic_rdma_dev_info_t;

2623 

2629 typedef struct {

2630  uint8_t num_rdma_dev;

2631  amdsmi_nic_rdma_dev_info_t rdma_dev_info[AMDSMI_MAX_NIC_RDMA_DEV];

2632 } amdsmi_nic_rdma_devices_info_t;

2633 /*****************************************************************************/

2662 amdsmi_status_t amdsmi_init(uint64_t init_flags);

2663 

2678 amdsmi_status_t amdsmi_shut_down(void);

2679 

2682 /*****************************************************************************/

2706 amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle,

2707  processor_type_t *processor_type);

2708 

2726 amdsmi_status_t amdsmi_get_processor_handle_from_index(uint32_t processor_index, amdsmi_processor_handle *processor_handle);

2727 

2759 amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count, amdsmi_socket_handle *socket_handles);

2760 

2776 amdsmi_status_t amdsmi_get_index_from_processor_handle(amdsmi_processor_handle processor_handle, uint32_t *processor_index);

2777 

2819 amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle,

2820  uint32_t *processor_count,

2821  amdsmi_processor_handle *processor_handles);

2822 

2842 amdsmi_status_t amdsmi_get_socket_info(amdsmi_socket_handle socket_handle, size_t len, char *name);

2843 

2861 amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_processor_handle *processor_handle);

2862 

2877 amdsmi_status_t amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);

2878 

2893 amdsmi_status_t amdsmi_get_processor_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);

2894 

2909 amdsmi_status_t amdsmi_get_processor_handle_from_uuid(const char *uuid, amdsmi_processor_handle *processor_handle);

2910 

2930 amdsmi_status_t amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid);

2931 

2949  amdsmi_status_t amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle, amdsmi_virtualization_mode_t *mode);

2950 

2976 amdsmi_status_t amdsmi_get_cpu_affinity_with_scope(amdsmi_processor_handle processor_handle,

2977  uint32_t cpu_set_size, uint64_t *cpu_set, amdsmi_affinity_scope_t scope);

2978 

2998 amdsmi_status_t amdsmi_get_node_handle(amdsmi_processor_handle processor_handle, amdsmi_node_handle *node_handle);

2999 

3014 amdsmi_status_t amdsmi_get_vf_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_vf_handle_t *vf_handle);

3015 

3030 amdsmi_status_t amdsmi_get_vf_handle_from_uuid(const char *uuid, amdsmi_vf_handle_t *vf_handle);

3031 

3047 amdsmi_status_t amdsmi_get_vf_handle_from_vf_index(amdsmi_processor_handle processor_handle, uint32_t fcn_idx, amdsmi_vf_handle_t *vf_handle);

3048 

3062 amdsmi_status_t amdsmi_get_vf_bdf(amdsmi_vf_handle_t vf_handle, amdsmi_bdf_t *bdf);

3063 

3082 amdsmi_status_t amdsmi_get_vf_uuid(amdsmi_vf_handle_t processor_handle, unsigned int *uuid_length, char *uuid);

3083 

3098 amdsmi_status_t amdsmi_get_nic_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);

3121 amdsmi_status_t amdsmi_get_processor_handles_by_type(amdsmi_socket_handle socket_handle,

3122  processor_type_t processor_type,

3123  amdsmi_processor_handle* processor_handles,

3124  uint32_t* processor_count);

3125 

3128 /*****************************************************************************/

3149 amdsmi_status_t amdsmi_get_lib_version(amdsmi_version_t *version);

3150 

3153 /*****************************************************************************/

3178 amdsmi_status_t amdsmi_status_code_to_string(amdsmi_status_t status, const char **status_string);

3179 

3182 /*****************************************************************************/

3202 amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info);

3203 

3217 amdsmi_status_t amdsmi_get_gpu_driver_model(amdsmi_processor_handle processor_handle, amdsmi_driver_model_type_t *model);

3218 

3221 /*****************************************************************************/

3245 amdsmi_status_t amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info);

3246 

3265 amdsmi_status_t

3266 amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind,

3267  amdsmi_power_cap_info_t *info);

3268 

3283 amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle, amdsmi_pcie_info_t *info);

3284 

3299 amdsmi_status_t amdsmi_get_gpu_vram_info(amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info);

3300 

3315 amdsmi_status_t amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info);

3316 

3331 amdsmi_status_t amdsmi_get_fb_layout(amdsmi_processor_handle processor_handle, amdsmi_pf_fb_info_t *info);

3332 

3335 /*****************************************************************************/

3354 amdsmi_status_t

3355 amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info);

3356 

3372 amdsmi_status_t

3373 amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info);

3374 

3389 amdsmi_status_t amdsmi_get_fw_error_records(amdsmi_processor_handle processor_handle, amdsmi_fw_error_record_t *records);

3390 

3404 amdsmi_status_t amdsmi_get_dfc_fw_table(amdsmi_processor_handle processor_handle, amdsmi_dfc_fw_t *info);

3405 

3408 /*****************************************************************************/

3427 amdsmi_status_t amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info);

3428 

3445 amdsmi_status_t amdsmi_get_power_info(amdsmi_processor_handle processor_handle, amdsmi_power_info_t *info);

3446 

3460 amdsmi_status_t

3461 amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled);

3462 

3482 amdsmi_status_t amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info);

3483 

3513 amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle, amdsmi_temperature_type_t sensor_type,

3514  amdsmi_temperature_metric_t metric, int64_t *temperature);

3515 

3534 amdsmi_status_t amdsmi_get_gpu_metrics(amdsmi_processor_handle processor_handle, uint32_t *metrics_size,

3535  amdsmi_metric_t *metrics);

3536 

3539 /*****************************************************************************/

3558  amdsmi_status_t

3559  amdsmi_get_gpu_memory_partition_config(amdsmi_processor_handle processor_handle,

3560  amdsmi_memory_partition_config_t *config);

3561 

3585 amdsmi_status_t

3586 amdsmi_set_gpu_memory_partition_mode(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_type_t mode);

3587 

3590 /*****************************************************************************/

3612 amdsmi_status_t

3613 amdsmi_get_gpu_accelerator_partition_profile_config(amdsmi_processor_handle processor_handle,

3614  amdsmi_accelerator_partition_profile_config_t *profile_config);

3615 

3636 amdsmi_status_t

3637 amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle,

3638  amdsmi_accelerator_partition_profile_t *profile,

3639  uint32_t *partition_id);

3640 

3658 amdsmi_status_t

3659 amdsmi_set_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle,

3660  uint32_t profile_index);

3661 

3684 amdsmi_status_t

3685 amdsmi_get_gpu_accelerator_partition_profile_config_global(amdsmi_processor_handle processor_handle,

3686  amdsmi_accelerator_partition_profile_config_global_t *config);

3687 

3690 /*****************************************************************************/

3709 amdsmi_status_t amdsmi_get_link_metrics(amdsmi_processor_handle processor_handle, amdsmi_link_metrics_t *link_metrics);

3710 

3735 amdsmi_status_t

3736 amdsmi_get_link_topology_nearest(amdsmi_processor_handle processor_handle,

3737  amdsmi_link_type_t link_type,

3738  amdsmi_topology_nearest_t* topology_nearest_info);

3739 

3766 amdsmi_status_t amdsmi_topo_get_p2p_status(amdsmi_processor_handle processor_handle_src,

3767  amdsmi_processor_handle processor_handle_dst,

3768  amdsmi_link_type_t *type, amdsmi_p2p_capability_t *cap);

3769 

3789 amdsmi_status_t amdsmi_topo_get_numa_node_number(amdsmi_processor_handle processor_handle, uint32_t *numa_node);

3790 

3807 amdsmi_status_t amdsmi_get_link_topology(amdsmi_processor_handle processor_handle_src,

3808  amdsmi_processor_handle processor_handle_dst,

3809  amdsmi_link_topology_t *topology_info);

3810 

3825 amdsmi_status_t amdsmi_get_xgmi_fb_sharing_caps(amdsmi_processor_handle processor_handle,

3826  amdsmi_xgmi_fb_sharing_caps_t *caps);

3827 

3846 amdsmi_status_t amdsmi_get_xgmi_fb_sharing_mode_info(amdsmi_processor_handle processor_handle_src,

3847  amdsmi_processor_handle processor_handle_dst,

3848  amdsmi_xgmi_fb_sharing_mode_t mode,

3849  uint8_t *fb_sharing);

3850 

3864 amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode(amdsmi_processor_handle processor_handle,

3865  amdsmi_xgmi_fb_sharing_mode_t mode);

3866 

3884 amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode_v2(amdsmi_processor_handle *processor_list,

3885  uint32_t num_processors,

3886  amdsmi_xgmi_fb_sharing_mode_t mode);

3887 

3890 /*****************************************************************************/

3916 amdsmi_status_t amdsmi_get_soc_pstate(amdsmi_processor_handle processor_handle,

3917  amdsmi_dpm_policy_t* policy);

3918 

3940 amdsmi_status_t amdsmi_set_soc_pstate(amdsmi_processor_handle processor_handle,

3941  uint32_t policy_id);

3942 

3962 amdsmi_status_t amdsmi_get_xgmi_plpd(amdsmi_processor_handle processor_handle,

3963  amdsmi_dpm_policy_t *xgmi_plpd);

3964 

3986 amdsmi_status_t amdsmi_set_xgmi_plpd(amdsmi_processor_handle processor_handle,

3987  uint32_t policy_id);

3988 

3991 /*****************************************************************************/

4018 amdsmi_status_t amdsmi_set_power_cap(amdsmi_processor_handle processor_handle,

4019  uint32_t sensor_ind, uint64_t cap);

4020 

4023 /*****************************************************************************/

4044 amdsmi_status_t amdsmi_get_gpu_cache_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info);

4045 

4048 /*****************************************************************************/

4078 amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle,

4079  amdsmi_gpu_block_t block, amdsmi_error_count_t *ec);

4080 

4108 amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle,

4109  uint64_t *enabled_blocks);

4110 

4127 amdsmi_status_t

4128 amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec);

4129 

4132 /*****************************************************************************/

4162 amdsmi_status_t amdsmi_get_bad_page_threshold(amdsmi_processor_handle processor_handle, uint32_t *threshold);

4163 

4200 amdsmi_status_t

4201 amdsmi_get_gpu_cper_entries(amdsmi_processor_handle processor_handle, uint32_t severity_mask, char *cper_data,

4202  uint64_t *buf_size, amdsmi_cper_hdr_t** cper_hdrs, uint64_t *entry_count, uint64_t *cursor);

4203 

4230 amdsmi_status_t amdsmi_get_afids_from_cper(char *cper_buffer, uint32_t buf_size, uint64_t *afids, uint32_t *num_afids);

4231 

4246 amdsmi_status_t amdsmi_get_gpu_ras_feature_info(amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature);

4247 

4264 amdsmi_status_t amdsmi_get_gpu_ras_policy_info(amdsmi_processor_handle processor_handle,

4265  amdsmi_gpu_ras_policy_info_t *info);

4266 

4286 amdsmi_status_t amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *bad_page_size,

4287  amdsmi_eeprom_table_record_t *bad_pages);

4288 

4291 /*****************************************************************************/

4315 amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle);

4316 

4340 amdsmi_status_t amdsmi_get_npm_info(amdsmi_node_handle node_handle, amdsmi_npm_info_t *info);

4341 

4344 /*****************************************************************************/

4369 amdsmi_status_t

4370 amdsmi_get_gpu_ptl_state(amdsmi_processor_handle processor_handle, bool *enabled);

4371 

4390 amdsmi_status_t amdsmi_set_gpu_ptl_state(amdsmi_processor_handle processor_handle, bool enable);

4391 

4414 amdsmi_status_t

4415 amdsmi_get_gpu_ptl_formats(amdsmi_processor_handle processor_handle,

4416  amdsmi_ptl_data_format_t *data_format1,

4417  amdsmi_ptl_data_format_t *data_format2);

4418 

4443 amdsmi_status_t

4444 amdsmi_set_gpu_ptl_formats(amdsmi_processor_handle processor_handle,

4445  amdsmi_ptl_data_format_t data_format1,

4446  amdsmi_ptl_data_format_t data_format2);

4447 

4450 /*****************************************************************************/

4472 amdsmi_status_t

4473 amdsmi_get_num_vf(amdsmi_processor_handle processor_handle, uint32_t *num_vf_enabled,

4474  uint32_t *num_vf_supported);

4475 

4494 amdsmi_status_t

4495 amdsmi_get_vf_partition_info(amdsmi_processor_handle processor_handle, unsigned int vf_buffer_num,

4496  amdsmi_partition_info_t *info);

4497 

4512 amdsmi_status_t

4513 amdsmi_get_partition_profile_info(amdsmi_processor_handle processor_handle,

4514  amdsmi_profile_info_t *profile_info);

4515 

4518 /*****************************************************************************/

4537 amdsmi_status_t

4538 amdsmi_get_vf_info(amdsmi_vf_handle_t vf_handle, amdsmi_vf_info_t *config);

4539 

4554 amdsmi_status_t

4555 amdsmi_get_vf_data(amdsmi_vf_handle_t vf_handle, amdsmi_vf_data_t *info);

4556 

4559 /*****************************************************************************/

4599 amdsmi_status_t

4600 amdsmi_event_create(amdsmi_processor_handle *processor_list, uint32_t num_devices,

4601  uint64_t event_types, amdsmi_event_set *set);

4602 

4634 amdsmi_status_t

4635 amdsmi_event_read(amdsmi_event_set set, int64_t timeout_usec, amdsmi_event_entry_t *event);

4636 

4648 amdsmi_status_t

4649 amdsmi_event_destroy(amdsmi_event_set set);

4650 

4653 /*****************************************************************************/

4675 amdsmi_status_t

4676 amdsmi_get_guest_data(amdsmi_vf_handle_t vf_handle, amdsmi_guest_data_t *info);

4677 

4693 amdsmi_status_t

4694 amdsmi_get_vf_fw_info(amdsmi_vf_handle_t vf_handle, amdsmi_fw_info_t *info);

4695 

4698 /*****************************************************************************/

4715 amdsmi_status_t amdsmi_clear_vf_fb(amdsmi_vf_handle_t vf_handle);

4716 

4730 amdsmi_status_t amdsmi_set_num_vf(amdsmi_processor_handle processor_handle, uint32_t num_vf);

4731 

4734 /*****************************************************************************/

4753 amdsmi_status_t amdsmi_get_nic_driver_info(amdsmi_processor_handle processor_handle, amdsmi_nic_driver_info_t *info);

4754 

4769 amdsmi_status_t amdsmi_get_nic_asic_info(amdsmi_processor_handle processor_handle, amdsmi_nic_asic_info_t *info);

4770 

4785 amdsmi_status_t amdsmi_get_nic_bus_info(amdsmi_processor_handle processor_handle, amdsmi_nic_bus_info_t *info);

4786 

4801 amdsmi_status_t amdsmi_get_nic_numa_info(amdsmi_processor_handle processor_handle, amdsmi_nic_numa_info_t *info);

4802 

4817 amdsmi_status_t amdsmi_get_nic_port_info(amdsmi_processor_handle processor_handle, amdsmi_nic_port_info_t *info);

4818 

4833 amdsmi_status_t amdsmi_get_nic_rdma_dev_info(amdsmi_processor_handle processor_handle, amdsmi_nic_rdma_devices_info_t *info);

4834 

4857 amdsmi_status_t amdsmi_get_nic_port_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index,

4858  uint32_t *num_stats, amdsmi_nic_stat_t *stats);

4859 

4886 amdsmi_status_t amdsmi_get_nic_vendor_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index,

4887  uint32_t *num_stats, amdsmi_nic_stat_t *stats);

4888 

4911 amdsmi_status_t amdsmi_get_nic_rdma_port_statistics(amdsmi_processor_handle processor_handle, uint32_t rdma_port_index,

4912  uint32_t *num_stats, amdsmi_nic_stat_t *stats);

4913 

4916 #endif // __AMDSMI_H__

4917 

amdsmi_event_reset_t

amdsmi_event_reset_t

Event Reset.

Definition: amdsmi.h:1407

amdsmi_vf_mode_t

amdsmi_vf_mode_t

Definition: amdsmi.h:2061

AMDSMI_VF_MODE_ALL

@ AMDSMI_VF_MODE_ALL

All VF counts supported.

Definition: amdsmi.h:2066

AMDSMI_MAX_ACCELERATOR_PROFILE

#define AMDSMI_MAX_ACCELERATOR_PROFILE

Maximum number of accelerator profiles.

Definition: amdsmi.h:164

AMDSMI_MAX_WHITE_LIST_ELEMENTS

#define AMDSMI_MAX_WHITE_LIST_ELEMENTS

Maximum number of white list elements for device access control.

Definition: amdsmi.h:183

amdsmi_event_fw_t

amdsmi_event_fw_t

Event Firmware.

Definition: amdsmi.h:1353

amdsmi_metric_category_t

amdsmi_metric_category_t

Metric Category.

Definition: amdsmi.h:1856

amdsmi_npm_status_t

amdsmi_npm_status_t

NPM status.

Definition: amdsmi.h:620

amdsmi_link_type_t

amdsmi_link_type_t

Link type.

Definition: amdsmi.h:442

AMDSMI_LINK_TYPE_NOT_APPLICABLE

@ AMDSMI_LINK_TYPE_NOT_APPLICABLE

Not Applicable Link Type.

Definition: amdsmi.h:446

AMDSMI_LINK_TYPE_INTERNAL

@ AMDSMI_LINK_TYPE_INTERNAL

Internal Link Type, within chip.

Definition: amdsmi.h:443

AMDSMI_LINK_TYPE_UNKNOWN

@ AMDSMI_LINK_TYPE_UNKNOWN

Unknown Link Type.

Definition: amdsmi.h:447

AMDSMI_LINK_TYPE_PCIE

@ AMDSMI_LINK_TYPE_PCIE

Peripheral Component Interconnect Express Link Type.

Definition: amdsmi.h:444

AMDSMI_LINK_TYPE_XGMI

@ AMDSMI_LINK_TYPE_XGMI

GPU Memory Interconnect (multi GPU communication)

Definition: amdsmi.h:445

amdsmi_event_xgmi_t

amdsmi_event_xgmi_t

Event XGMI.

Definition: amdsmi.h:1657

AMDSMI_MAX_PROFILE_COUNT

#define AMDSMI_MAX_PROFILE_COUNT

Maximum number of profiles supported.

Definition: amdsmi.h:188

amdsmi_event_ecc_t

amdsmi_event_ecc_t

Event ECC.

Definition: amdsmi.h:1445

amdsmi_event_gpumon_t

amdsmi_event_gpumon_t

Event GPU Monitor.

Definition: amdsmi.h:1622

amdsmi_accelerator_partition_type_t

amdsmi_accelerator_partition_type_t

Accelerator Partition.

Definition: amdsmi.h:232

AMDSMI_ACCELERATOR_PARTITION_DPX

@ AMDSMI_ACCELERATOR_PARTITION_DPX

Definition: amdsmi.h:236

AMDSMI_ACCELERATOR_PARTITION_QPX

@ AMDSMI_ACCELERATOR_PARTITION_QPX

Definition: amdsmi.h:240

AMDSMI_ACCELERATOR_PARTITION_INVALID

@ AMDSMI_ACCELERATOR_PARTITION_INVALID

Invalid accelerator partition type.

Definition: amdsmi.h:233

AMDSMI_ACCELERATOR_PARTITION_SPX

@ AMDSMI_ACCELERATOR_PARTITION_SPX

Definition: amdsmi.h:234

AMDSMI_ACCELERATOR_PARTITION_TPX

@ AMDSMI_ACCELERATOR_PARTITION_TPX

Definition: amdsmi.h:238

AMDSMI_ACCELERATOR_PARTITION_CPX

@ AMDSMI_ACCELERATOR_PARTITION_CPX

Definition: amdsmi.h:242

amdsmi_event_guard_t

amdsmi_event_guard_t

Event Guard.

Definition: amdsmi.h:1611

amdsmi_vf_config_flags_t

amdsmi_vf_config_flags_t

VF Config Flags.

Definition: amdsmi.h:1725

amdsmi_clk_type_t

amdsmi_clk_type_t

Clock types.

Definition: amdsmi.h:294

AMDSMI_CLK_TYPE_DCLK1

@ AMDSMI_CLK_TYPE_DCLK1

Display 2 clock, timing signals for display output.

Definition: amdsmi.h:308

AMDSMI_CLK_TYPE_MEM

@ AMDSMI_CLK_TYPE_MEM

Memory clock speed, system operating frequency.

Definition: amdsmi.h:303

AMDSMI_CLK_TYPE_SYS

@ AMDSMI_CLK_TYPE_SYS

System clock.

Definition: amdsmi.h:295

AMDSMI_CLK_TYPE_SOC

@ AMDSMI_CLK_TYPE_SOC

System On Chip clock, integrated circuit frequency.

Definition: amdsmi.h:302

AMDSMI_CLK_TYPE_GFX

@ AMDSMI_CLK_TYPE_GFX

Graphics clock.

Definition: amdsmi.h:297

AMDSMI_CLK_TYPE_DCLK0

@ AMDSMI_CLK_TYPE_DCLK0

Display 1 clock, timing signals for display output.

Definition: amdsmi.h:307

AMDSMI_CLK_TYPE_DCEF

@ AMDSMI_CLK_TYPE_DCEF

Definition: amdsmi.h:300

AMDSMI_CLK_TYPE_VCLK1

@ AMDSMI_CLK_TYPE_VCLK1

Video 1 clock, video processing units.

Definition: amdsmi.h:306

AMDSMI_CLK_TYPE_DF

@ AMDSMI_CLK_TYPE_DF

Definition: amdsmi.h:298

AMDSMI_CLK_TYPE_VCLK0

@ AMDSMI_CLK_TYPE_VCLK0

Video 0 clock, video processing units.

Definition: amdsmi.h:305

AMDSMI_CLK_TYPE_PCIE

@ AMDSMI_CLK_TYPE_PCIE

PCI Express clock, high bandwidth peripherals.

Definition: amdsmi.h:304

amdsmi_accelerator_partition_resource_type_t

amdsmi_accelerator_partition_resource_type_t

Accelerator Partition Resource Types.

Definition: amdsmi.h:280

AMDSMI_ACCELERATOR_DMA

@ AMDSMI_ACCELERATOR_DMA

Direct Memory Access, high speed data transfers.

Definition: amdsmi.h:284

AMDSMI_ACCELERATOR_XCC

@ AMDSMI_ACCELERATOR_XCC

Compute complex or stream processors.

Definition: amdsmi.h:281

AMDSMI_ACCELERATOR_DECODER

@ AMDSMI_ACCELERATOR_DECODER

Video decoding.

Definition: amdsmi.h:283

AMDSMI_ACCELERATOR_JPEG

@ AMDSMI_ACCELERATOR_JPEG

Encoding and Decoding jpeg engines.

Definition: amdsmi.h:285

AMDSMI_ACCELERATOR_ENCODER

@ AMDSMI_ACCELERATOR_ENCODER

Video encoding.

Definition: amdsmi.h:282

AMDSMI_MAX_ERR_RECORDS

#define AMDSMI_MAX_ERR_RECORDS

Maximum number of error records that can be stored.

Definition: amdsmi.h:187

amdsmi_card_form_factor_t

amdsmi_card_form_factor_t

Card Form Factor.

Definition: amdsmi.h:430

AMDSMI_CARD_FORM_FACTOR_OAM

@ AMDSMI_CARD_FORM_FACTOR_OAM

OAM form factor.

Definition: amdsmi.h:432

AMDSMI_CARD_FORM_FACTOR_UNKNOWN

@ AMDSMI_CARD_FORM_FACTOR_UNKNOWN

Unknown Form factor.

Definition: amdsmi.h:434

AMDSMI_CARD_FORM_FACTOR_PCIE

@ AMDSMI_CARD_FORM_FACTOR_PCIE

PCIE card form factor.

Definition: amdsmi.h:431

AMDSMI_CARD_FORM_FACTOR_CEM

@ AMDSMI_CARD_FORM_FACTOR_CEM

CEM form factor.

Definition: amdsmi.h:433

amdsmi_node_handle

void * amdsmi_node_handle

opaque handler point to underlying implementation

Definition: amdsmi.h:203

AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK

#define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK

Common defines.

Definition: amdsmi.h:149

amdsmi_guard_type_t

amdsmi_guard_type_t

Guard Event.

Definition: amdsmi.h:1761

amdsmi_pp_throttler_type_t

amdsmi_pp_throttler_type_t

This enum determines which type of PP throttler event occurred.

Definition: amdsmi.h:1671

amdsmi_profile_capability_type_t

amdsmi_profile_capability_type_t

Profile Capability.

Definition: amdsmi.h:1843

AMDSMI_PROFILE_CAPABILITY_DECODE

@ AMDSMI_PROFILE_CAPABILITY_DECODE

decode engine

Definition: amdsmi.h:1846

AMDSMI_PROFILE_CAPABILITY_MEMORY

@ AMDSMI_PROFILE_CAPABILITY_MEMORY

memory

Definition: amdsmi.h:1844

AMDSMI_PROFILE_CAPABILITY_ENCODE

@ AMDSMI_PROFILE_CAPABILITY_ENCODE

encode engine

Definition: amdsmi.h:1845

AMDSMI_PROFILE_CAPABILITY_COMPUTE

@ AMDSMI_PROFILE_CAPABILITY_COMPUTE

compute engine

Definition: amdsmi.h:1847

amdsmi_init_flags_t

amdsmi_init_flags_t

Initialization flags.

Definition: amdsmi.h:44

AMDSMI_INIT_AMD_GPUS

@ AMDSMI_INIT_AMD_GPUS

Initialize AMD GPUS.

Definition: amdsmi.h:47

AMDSMI_INIT_ALL_PROCESSORS

@ AMDSMI_INIT_ALL_PROCESSORS

Initialize all processors.

Definition: amdsmi.h:45

AMDSMI_INIT_AMD_CPUS

@ AMDSMI_INIT_AMD_CPUS

Initialize AMD CPUS.

Definition: amdsmi.h:46

AMDSMI_INIT_NON_AMD_GPUS

@ AMDSMI_INIT_NON_AMD_GPUS

Initialize Non-AMD GPUS.

Definition: amdsmi.h:49

AMDSMI_INIT_NON_AMD_CPUS

@ AMDSMI_INIT_NON_AMD_CPUS

Initialize Non-AMD CPUS.

Definition: amdsmi.h:48

AMDSMI_INIT_AMD_APUS

@ AMDSMI_INIT_AMD_APUS

Definition: amdsmi.h:50

amdsmi_event_pp_t

amdsmi_event_pp_t

Event PP.

Definition: amdsmi.h:1514

amdsmi_event_vbios_t

amdsmi_event_vbios_t

Event VBios.

Definition: amdsmi.h:1584

amdsmi_event_set

void * amdsmi_event_set

Opague Handler point to underlying implementation.

Definition: amdsmi.h:1235

AMDSMI_MAX_NIC_FW

#define AMDSMI_MAX_NIC_FW

Maximum number of NIC firmwares.

Definition: amdsmi.h:2460

amdsmi_vram_type_t

amdsmi_vram_type_t

vRam Types. This enum is used to identify various VRam types.

Definition: amdsmi.h:252

AMDSMI_VRAM_TYPE_GDDR2

@ AMDSMI_VRAM_TYPE_GDDR2

Graphics Double Data Rate, Generation 2.

Definition: amdsmi.h:266

AMDSMI_VRAM_TYPE_HBM2E

@ AMDSMI_VRAM_TYPE_HBM2E

High Bandwidth Memory, Generation 2 Enhanced.

Definition: amdsmi.h:257

AMDSMI_VRAM_TYPE_GDDR6

@ AMDSMI_VRAM_TYPE_GDDR6

Graphics Double Data Rate, Generation 6.

Definition: amdsmi.h:270

AMDSMI_VRAM_TYPE_HBM

@ AMDSMI_VRAM_TYPE_HBM

High Bandwidth Memory.

Definition: amdsmi.h:255

AMDSMI_VRAM_TYPE_GDDR3

@ AMDSMI_VRAM_TYPE_GDDR3

Graphics Double Data Rate, Generation 3.

Definition: amdsmi.h:267

AMDSMI_VRAM_TYPE_GDDR1

@ AMDSMI_VRAM_TYPE_GDDR1

Graphics Double Data Rate, Generation 1.

Definition: amdsmi.h:265

AMDSMI_VRAM_TYPE_HBM3

@ AMDSMI_VRAM_TYPE_HBM3

High Bandwidth Memory, Generation 3.

Definition: amdsmi.h:258

AMDSMI_VRAM_TYPE_HBM3E

@ AMDSMI_VRAM_TYPE_HBM3E

High Bandwidth Memory, Generation 3 Enhanced.

Definition: amdsmi.h:259

AMDSMI_VRAM_TYPE_GDDR5

@ AMDSMI_VRAM_TYPE_GDDR5

Graphics Double Data Rate, Generation 5.

Definition: amdsmi.h:269

AMDSMI_VRAM_TYPE_DDR3

@ AMDSMI_VRAM_TYPE_DDR3

Double Data Rate, Generation 3.

Definition: amdsmi.h:262

AMDSMI_VRAM_TYPE_GDDR4

@ AMDSMI_VRAM_TYPE_GDDR4

Graphics Double Data Rate, Generation 4.

Definition: amdsmi.h:268

AMDSMI_VRAM_TYPE_DDR2

@ AMDSMI_VRAM_TYPE_DDR2

Double Data Rate, Generation 2.

Definition: amdsmi.h:261

AMDSMI_VRAM_TYPE_GDDR7

@ AMDSMI_VRAM_TYPE_GDDR7

Graphics Double Data Rate, Generation 7.

Definition: amdsmi.h:271

AMDSMI_VRAM_TYPE_HBM2

@ AMDSMI_VRAM_TYPE_HBM2

High Bandwidth Memory, Generation 2.

Definition: amdsmi.h:256

AMDSMI_VRAM_TYPE_DDR4

@ AMDSMI_VRAM_TYPE_DDR4

Double Data Rate, Generation 4.

Definition: amdsmi.h:263

AMDSMI_VRAM_TYPE_UNKNOWN

@ AMDSMI_VRAM_TYPE_UNKNOWN

Unknown memory type.

Definition: amdsmi.h:253

amdsmi_event_vf_max_t

amdsmi_event_vf_max_t

Event VF.

Definition: amdsmi.h:1565

amdsmi_metric_type_t

amdsmi_metric_type_t

Metric Type.

Definition: amdsmi.h:2034

AMDSMI_METRIC_TYPE_COUNTER

@ AMDSMI_METRIC_TYPE_COUNTER

counter metric

Definition: amdsmi.h:2035

AMDSMI_METRIC_TYPE_CHIPLET

@ AMDSMI_METRIC_TYPE_CHIPLET

chiplet metric

Definition: amdsmi.h:2036

AMDSMI_METRIC_TYPE_ACC

@ AMDSMI_METRIC_TYPE_ACC

accumulated metric

Definition: amdsmi.h:2038

AMDSMI_METRIC_TYPE_INST

@ AMDSMI_METRIC_TYPE_INST

instantaneous metric

Definition: amdsmi.h:2037

AMDSMI_MAX_ACCELERATOR_PARTITIONS

#define AMDSMI_MAX_ACCELERATOR_PARTITIONS

Maximum number of accelerator partitions.

Definition: amdsmi.h:163

amdsmi_cper_notify_type_t

amdsmi_cper_notify_type_t

Cper notify.

Definition: amdsmi.h:1066

AMDSMI_CPER_NOTIFY_TYPE_DMAR

@ AMDSMI_CPER_NOTIFY_TYPE_DMAR

Direct Memory Access Remapping Error.

Definition: amdsmi.h:1074

AMDSMI_CPER_NOTIFY_TYPE_NMI

@ AMDSMI_CPER_NOTIFY_TYPE_NMI

Non_Maskable Interrupt.

Definition: amdsmi.h:1072

AMDSMI_CPER_NOTIFY_TYPE_SEI

@ AMDSMI_CPER_NOTIFY_TYPE_SEI

System Error Interface.

Definition: amdsmi.h:1076

AMDSMI_CPER_NOTIFY_TYPE_CMC

@ AMDSMI_CPER_NOTIFY_TYPE_CMC

Corrected Memory Check.

Definition: amdsmi.h:1067

AMDSMI_CPER_NOTIFY_TYPE_CPE

@ AMDSMI_CPER_NOTIFY_TYPE_CPE

Corrected Platform Error.

Definition: amdsmi.h:1068

AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT

@ AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT

Compute Express Link Component Error.

Definition: amdsmi.h:1078

AMDSMI_CPER_NOTIFY_TYPE_SEA

@ AMDSMI_CPER_NOTIFY_TYPE_SEA

System Error Architecture.

Definition: amdsmi.h:1075

AMDSMI_CPER_NOTIFY_TYPE_PEI

@ AMDSMI_CPER_NOTIFY_TYPE_PEI

Platform Error Interface.

Definition: amdsmi.h:1077

AMDSMI_CPER_NOTIFY_TYPE_MCE

@ AMDSMI_CPER_NOTIFY_TYPE_MCE

Machine Check Exception.

Definition: amdsmi.h:1069

AMDSMI_CPER_NOTIFY_TYPE_BOOT

@ AMDSMI_CPER_NOTIFY_TYPE_BOOT

Boot Error.

Definition: amdsmi.h:1073

AMDSMI_CPER_NOTIFY_TYPE_PCIE

@ AMDSMI_CPER_NOTIFY_TYPE_PCIE

PCI Express Error.

Definition: amdsmi.h:1070

AMDSMI_CPER_NOTIFY_TYPE_INIT

@ AMDSMI_CPER_NOTIFY_TYPE_INIT

Initialization Error.

Definition: amdsmi.h:1071

AMDSMI_MAX_CP_PROFILE_RESOURCES

#define AMDSMI_MAX_CP_PROFILE_RESOURCES

Maximum number of compute profile resources.

Definition: amdsmi.h:162

processor_type_t

processor_type_t

Processor types detectable by AMD SMI.

Definition: amdsmi.h:133

AMDSMI_PROCESSOR_TYPE_AMD_APU

@ AMDSMI_PROCESSOR_TYPE_AMD_APU

AMD Accelerated processor type (GPU and CPU)

Definition: amdsmi.h:140

AMDSMI_PROCESSOR_TYPE_UNKNOWN

@ AMDSMI_PROCESSOR_TYPE_UNKNOWN

Unknown processor type.

Definition: amdsmi.h:134

AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU

@ AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU

Non-AMD CPU processor type.

Definition: amdsmi.h:138

AMDSMI_PROCESSOR_TYPE_AMD_CPU

@ AMDSMI_PROCESSOR_TYPE_AMD_CPU

AMD CPU processor type.

Definition: amdsmi.h:136

AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE

@ AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE

AMD CPU-Core processor type.

Definition: amdsmi.h:139

AMDSMI_PROCESSOR_TYPE_AMD_GPU

@ AMDSMI_PROCESSOR_TYPE_AMD_GPU

AMD Graphics processor type.

Definition: amdsmi.h:135

AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU

@ AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU

Non-AMD Graphics processor type.

Definition: amdsmi.h:137

AMDSMI_PROCESSOR_TYPE_AMD_NIC

@ AMDSMI_PROCESSOR_TYPE_AMD_NIC

AMD Network Interface Card processor type.

Definition: amdsmi.h:141

amdsmi_fw_block_t

amdsmi_fw_block_t

The values of this enum are used to identify the various firmware blocks.

Definition: amdsmi.h:500

AMDSMI_FW_ID_ASD

@ AMDSMI_FW_ID_ASD

Asynchronous Shader Dispatcher.

Definition: amdsmi.h:574

AMDSMI_FW_ID_RS64_ME_P0_DATA

@ AMDSMI_FW_ID_RS64_ME_P0_DATA

Hardware Block RS64 - Micro Engine Partition 0 Data.

Definition: amdsmi.h:556

AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM

@ AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM

Rasterizier and L2 Cache Restore List System RAM Memory.

Definition: amdsmi.h:527

AMDSMI_FW_ID_SDMA7

@ AMDSMI_FW_ID_SDMA7

System Direct Memory Access 7 (high speed data transfers)

Definition: amdsmi.h:519

AMDSMI_FW_ID_PSP_BL

@ AMDSMI_FW_ID_PSP_BL

Platform Security Processor Bootloader (initial firmware)

Definition: amdsmi.h:539

AMDSMI_FW_ID_RLC

@ AMDSMI_FW_ID_RLC

Rasterizer and L2 Cache (rasterization processs)

Definition: amdsmi.h:511

AMDSMI_FW_ID_RS64_PFP

@ AMDSMI_FW_ID_RS64_PFP

Hardware Block RS64 - Pixel Front End Processor.

Definition: amdsmi.h:558

AMDSMI_FW_ID_SDMA_TH1

@ AMDSMI_FW_ID_SDMA_TH1

System Direct Memory Access - Thread Handler 1.

Definition: amdsmi.h:547

AMDSMI_FW_ID_MMSCH

@ AMDSMI_FW_ID_MMSCH

Multi-Media Shader Hardware Scheduler.

Definition: amdsmi.h:530

AMDSMI_FW_ID_RLX6

@ AMDSMI_FW_ID_RLX6

Hardware Block RLX6.

Definition: amdsmi.h:553

AMDSMI_FW_ID_PSP_SOSDRV

@ AMDSMI_FW_ID_PSP_SOSDRV

Platform Security Processor Secure Operating System Driver.

Definition: amdsmi.h:532

AMDSMI_FW_ID_TA_RAS

@ AMDSMI_FW_ID_TA_RAS

Trusted Applications - Reliablity Availability and Serviceability.

Definition: amdsmi.h:575

AMDSMI_FW_ID_PSP_KEYDB

@ AMDSMI_FW_ID_PSP_KEYDB

Platform Security Processor Table of Contents.

Definition: amdsmi.h:534

AMDSMI_FW_ID_RLC_SRLS

@ AMDSMI_FW_ID_RLC_SRLS

Rasterizier and L2 Cache - Shared Resource Local Segment.

Definition: amdsmi.h:579

AMDSMI_FW_ID_VCE

@ AMDSMI_FW_ID_VCE

Video Coding Engine (Encoding video)

Definition: amdsmi.h:522

AMDSMI_FW_ID_DMCU_ISR

@ AMDSMI_FW_ID_DMCU_ISR

Digital Micro Controller Unit - Interrupt Service Routine (interrupt handlers)

Definition: amdsmi.h:525

AMDSMI_FW_ID_SDMA6

@ AMDSMI_FW_ID_SDMA6

System Direct Memory Access 6 (high speed data transfers)

Definition: amdsmi.h:518

AMDSMI_FW_ID_PSP_DBG

@ AMDSMI_FW_ID_PSP_DBG

Platform Security Processor - Debug.

Definition: amdsmi.h:568

AMDSMI_FW_ID_CP_CE

@ AMDSMI_FW_ID_CP_CE

Compute Processor - Command_Engine (fetch, decode, dispatch)

Definition: amdsmi.h:504

AMDSMI_FW_ID_P2S_TABLE

@ AMDSMI_FW_ID_P2S_TABLE

Processor-to-System Table Firmware.

Definition: amdsmi.h:584

AMDSMI_FW_ID_DRV_CAP

@ AMDSMI_FW_ID_DRV_CAP

Driver Capabilities (capabilities, features)

Definition: amdsmi.h:537

AMDSMI_FW_ID_RS64_ME_P1_DATA

@ AMDSMI_FW_ID_RS64_ME_P1_DATA

Hardware Block RS64 - Micro Engine Partition 1 Data.

Definition: amdsmi.h:557

AMDSMI_FW_ID_MES_THREAD1

@ AMDSMI_FW_ID_MES_THREAD1

Micro Engine Scheduler - Thread 1.

Definition: amdsmi.h:551

AMDSMI_FW_ID_PM

@ AMDSMI_FW_ID_PM

Power Management Firmware.

Definition: amdsmi.h:580

AMDSMI_FW_ID_SDMA0

@ AMDSMI_FW_ID_SDMA0

System Direct Memory Access 0 (high speed data transfers)

Definition: amdsmi.h:512

AMDSMI_FW_ID_ISP

@ AMDSMI_FW_ID_ISP

Image Signal Processor (processing raw image data from sensors)

Definition: amdsmi.h:523

AMDSMI_FW_ID_PSP_SOC

@ AMDSMI_FW_ID_PSP_SOC

Platform Security Processor - System On a Chip.

Definition: amdsmi.h:567

AMDSMI_FW_ID_CP_PM4

@ AMDSMI_FW_ID_CP_PM4

Compute Processor Packet Processor 4 (processing command packets)

Definition: amdsmi.h:540

AMDSMI_FW_ID_RLC_P

@ AMDSMI_FW_ID_RLC_P

Rasterizier and L2 Cache Partition.

Definition: amdsmi.h:541

AMDSMI_FW_ID_SDMA_TH0

@ AMDSMI_FW_ID_SDMA_TH0

System Direct Memory Access - Thread Handler 0.

Definition: amdsmi.h:546

AMDSMI_FW_ID_MC

@ AMDSMI_FW_ID_MC

Memory Contoller (RAM and VRAM)

Definition: amdsmi.h:538

AMDSMI_FW_ID_VCN

@ AMDSMI_FW_ID_VCN

Video Core Next (encoding and decoding)

Definition: amdsmi.h:520

AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1

@ AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1

Hardware Block RLX6 Core 1 - Dynamic RAM Boot.

Definition: amdsmi.h:571

AMDSMI_FW_ID_MES_STACK

@ AMDSMI_FW_ID_MES_STACK

Micro Engine Scheduler - Stack.

Definition: amdsmi.h:550

AMDSMI_FW_ID_XGMI

@ AMDSMI_FW_ID_XGMI

XGMI (Interconnect) Firmware.

Definition: amdsmi.h:577

AMDSMI_FW_ID_PSP_TOC

@ AMDSMI_FW_ID_PSP_TOC

Platform Security Processor Table of Contents.

Definition: amdsmi.h:533

AMDSMI_FW_ID_IMU_IRAM

@ AMDSMI_FW_ID_IMU_IRAM

Input/Output Memory Management Unit - Instruction RAM.

Definition: amdsmi.h:545

AMDSMI_FW_ID_SEC_POLICY_STAGE2

@ AMDSMI_FW_ID_SEC_POLICY_STAGE2

Security Policy Stage 2 (security features)

Definition: amdsmi.h:542

AMDSMI_FW_ID_RS64_MEC_P2_DATA

@ AMDSMI_FW_ID_RS64_MEC_P2_DATA

Hardware Block RS64 - Micro Engine Controller Partition 2 Data.

Definition: amdsmi.h:564

AMDSMI_FW_ID_PLDM_BUNDLE

@ AMDSMI_FW_ID_PLDM_BUNDLE

Platform Level Data Model Firmware Bundle.

Definition: amdsmi.h:585

AMDSMI_FW_ID_TA_XGMI

@ AMDSMI_FW_ID_TA_XGMI

Trusted Applications - Reliablity XGMI.

Definition: amdsmi.h:576

AMDSMI_FW_ID_RS64_ME

@ AMDSMI_FW_ID_RS64_ME

Hardware Block RS64 - Micro Engine.

Definition: amdsmi.h:555

AMDSMI_FW_ID_SDMA3

@ AMDSMI_FW_ID_SDMA3

System Direct Memory Access 3 (high speed data transfers)

Definition: amdsmi.h:515

AMDSMI_FW_ID_SDMA1

@ AMDSMI_FW_ID_SDMA1

System Direct Memory Access 1 (high speed data transfers)

Definition: amdsmi.h:513

AMDSMI_FW_ID_CP_ME

@ AMDSMI_FW_ID_CP_ME

Compute Processor - Micro Engine (specialize processing)

Definition: amdsmi.h:506

AMDSMI_FW_ID_RS64_MEC_P3_DATA

@ AMDSMI_FW_ID_RS64_MEC_P3_DATA

Hardware Block RS64 - Micro Engine Controller Partition 3 Data.

Definition: amdsmi.h:565

AMDSMI_FW_ID_CP_MEC_JT1

@ AMDSMI_FW_ID_CP_MEC_JT1

Compute Processor - Micro Engine Controler Job Table 1 (queues, scheduling)

Definition: amdsmi.h:507

AMDSMI_FW_ID_UVD

@ AMDSMI_FW_ID_UVD

Unified Video Decoder (decode specific video formats)

Definition: amdsmi.h:521

AMDSMI_FW_ID_RLC_V

@ AMDSMI_FW_ID_RLC_V

Rasterizier and L2 Cache Virtual memory.

Definition: amdsmi.h:529

AMDSMI_FW_ID_SMC

@ AMDSMI_FW_ID_SMC

System Management Controller Firmware.

Definition: amdsmi.h:581

AMDSMI_FW_ID_SDMA4

@ AMDSMI_FW_ID_SDMA4

System Direct Memory Access 4 (high speed data transfers)

Definition: amdsmi.h:516

AMDSMI_FW_ID_MES_KIQ

@ AMDSMI_FW_ID_MES_KIQ

Micro Engine Scheduler - Kernel Indirect Queue.

Definition: amdsmi.h:549

AMDSMI_FW_ID_DMCU

@ AMDSMI_FW_ID_DMCU

Display Micro-Controller Unit.

Definition: amdsmi.h:582

AMDSMI_FW_ID_RLC_SRLG

@ AMDSMI_FW_ID_RLC_SRLG

Rasterizier and L2 Cache - Shared Resource Local Group.

Definition: amdsmi.h:578

AMDSMI_FW_ID_RS64_PFP_P1_DATA

@ AMDSMI_FW_ID_RS64_PFP_P1_DATA

Hardware Block RS64 - Pixel Front End Processor Partition 1 Data.

Definition: amdsmi.h:560

AMDSMI_FW_ID_RLX6_DRAM_BOOT

@ AMDSMI_FW_ID_RLX6_DRAM_BOOT

Hardware Block RLX6 - Dynamic Ram Boot.

Definition: amdsmi.h:554

AMDSMI_FW_ID_IMU_DRAM

@ AMDSMI_FW_ID_IMU_DRAM

Input/Output Memory Management Unit - Dynamic RAM.

Definition: amdsmi.h:544

AMDSMI_FW_ID_CP_MEC1

@ AMDSMI_FW_ID_CP_MEC1

Compute Processor - Micro Engine Controler 1 (scheduling, managing resources)

Definition: amdsmi.h:509

AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL

@ AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL

Rasterizier and L2 Cache Restore List Control.

Definition: amdsmi.h:528

AMDSMI_FW_ID_RS64_MEC_P0_DATA

@ AMDSMI_FW_ID_RS64_MEC_P0_DATA

Hardware Block RS64 - Micro Engine Controller Partition 0 Data.

Definition: amdsmi.h:562

AMDSMI_FW_ID_RLX6_CORE1

@ AMDSMI_FW_ID_RLX6_CORE1

Hardware Block RLX6 - Core 1.

Definition: amdsmi.h:570

AMDSMI_FW_ID_RS64_MEC_P1_DATA

@ AMDSMI_FW_ID_RS64_MEC_P1_DATA

Hardware Block RS64 - Micro Engine Controller Partition 1 Data.

Definition: amdsmi.h:563

AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM

@ AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM

Rasterizier and L2 Cache Restore List Graphics Processor Memory.

Definition: amdsmi.h:526

AMDSMI_FW_ID_PSP_INTF

@ AMDSMI_FW_ID_PSP_INTF

Platform Security Processor - Interface.

Definition: amdsmi.h:569

AMDSMI_FW_ID_CP_MEC_JT2

@ AMDSMI_FW_ID_CP_MEC_JT2

Compute Processor - Micro Engine Controler Job Table 2 (queues, scheduling)

Definition: amdsmi.h:508

AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST

@ AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST

Rasterizier and L2 Cache - Save Restore List.

Definition: amdsmi.h:573

AMDSMI_FW_ID_CP_PFP

@ AMDSMI_FW_ID_CP_PFP

Compute Processor - Pixel Front End Processor (pixelating process)

Definition: amdsmi.h:505

AMDSMI_FW_ID_PSP_RAS

@ AMDSMI_FW_ID_PSP_RAS

Platform Security Processor - Reliability, Availability, and Serviceability Firmware.

Definition: amdsmi.h:583

AMDSMI_FW_ID_MES_THREAD1_STACK

@ AMDSMI_FW_ID_MES_THREAD1_STACK

Micro Engine Scheduler - Thread 1 Stack.

Definition: amdsmi.h:552

AMDSMI_FW_ID_SMU

@ AMDSMI_FW_ID_SMU

Definition: amdsmi.h:501

AMDSMI_FW_ID_PPTABLE

@ AMDSMI_FW_ID_PPTABLE

Power Policy Table (power management policies)

Definition: amdsmi.h:566

AMDSMI_FW_ID_PSP_SPL

@ AMDSMI_FW_ID_PSP_SPL

Platform Security Processor Secure Program Loader.

Definition: amdsmi.h:536

AMDSMI_FW_ID_REG_ACCESS_WHITELIST

@ AMDSMI_FW_ID_REG_ACCESS_WHITELIST

Register Access Whitelist (Prevent unathorizied access)

Definition: amdsmi.h:543

AMDSMI_FW_ID_PSP_SYSDRV

@ AMDSMI_FW_ID_PSP_SYSDRV

Platform Security Processor System Driver.

Definition: amdsmi.h:531

AMDSMI_FW_ID_RS64_PFP_P0_DATA

@ AMDSMI_FW_ID_RS64_PFP_P0_DATA

Hardware Block RS64 - Pixel Front End Processor Partition 0 Data.

Definition: amdsmi.h:559

AMDSMI_FW_ID_SDMA5

@ AMDSMI_FW_ID_SDMA5

System Direct Memory Access 5 (high speed data transfers)

Definition: amdsmi.h:517

AMDSMI_FW_ID_SDMA2

@ AMDSMI_FW_ID_SDMA2

System Direct Memory Access 2 (high speed data transfers)

Definition: amdsmi.h:514

AMDSMI_FW_ID_CP_MES

@ AMDSMI_FW_ID_CP_MES

Compute Processor - Micro Engine Scheduler.

Definition: amdsmi.h:548

AMDSMI_FW_ID_DMCU_ERAM

@ AMDSMI_FW_ID_DMCU_ERAM

Digital Micro Controller Unit - Embedded RAM (memory used by DMU)

Definition: amdsmi.h:524

AMDSMI_FW_ID_RLCV_LX7

@ AMDSMI_FW_ID_RLCV_LX7

Hardware Block RLCV - Subsystem LX7.

Definition: amdsmi.h:572

AMDSMI_FW_ID_RS64_MEC

@ AMDSMI_FW_ID_RS64_MEC

Hardware Block RS64 - Micro Engine Controller.

Definition: amdsmi.h:561

AMDSMI_FW_ID_DFC

@ AMDSMI_FW_ID_DFC

Data Fabric Controler (bandwidth and coherency)

Definition: amdsmi.h:535

AMDSMI_FW_ID_CP_MEC2

@ AMDSMI_FW_ID_CP_MEC2

Compute Processor - Micro Engine Controler 2 (scheduling, managing resources)

Definition: amdsmi.h:510

amdsmi_driver_t

amdsmi_driver_t

Driver.

Definition: amdsmi.h:1777

AMDSMI_MAX_NIC_PORTS

#define AMDSMI_MAX_NIC_PORTS

Maximum size definitions AMDSMI NIC.

Definition: amdsmi.h:2458

AMDSMI_MAX_DATE_STRING_LENGTH

#define AMDSMI_MAX_DATE_STRING_LENGTH

Maximum size definitions for date strings.

Definition: amdsmi.h:1228

AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS

#define AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS

Maximum number of TA (Trusted Application) white list elements.

Definition: amdsmi.h:186

amdsmi_virtualization_mode_t

amdsmi_virtualization_mode_t

Variant placeholder.

Definition: amdsmi.h:597

AMDSMI_VIRTUALIZATION_MODE_BAREMETAL

@ AMDSMI_VIRTUALIZATION_MODE_BAREMETAL

Baremetal Virtualization Mode.

Definition: amdsmi.h:599

AMDSMI_VIRTUALIZATION_MODE_UNKNOWN

@ AMDSMI_VIRTUALIZATION_MODE_UNKNOWN

Unknown Virtualization Mode.

Definition: amdsmi.h:598

AMDSMI_VIRTUALIZATION_MODE_HOST

@ AMDSMI_VIRTUALIZATION_MODE_HOST

Host Virtualization Mode.

Definition: amdsmi.h:600

AMDSMI_VIRTUALIZATION_MODE_GUEST

@ AMDSMI_VIRTUALIZATION_MODE_GUEST

Guest Virtualization Mode.

Definition: amdsmi.h:601

AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH

@ AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH

Passthrough Virtualization Mode.

Definition: amdsmi.h:602

AMDSMI_MAX_STRING_LENGTH

#define AMDSMI_MAX_STRING_LENGTH

Maximum length for string buffers.

Definition: amdsmi.h:160

amdsmi_guest_fw_engine_id_t

amdsmi_guest_fw_engine_id_t

The values of this enum are used to identify the various firmware blocks.

Definition: amdsmi.h:1695

amdsmi_metric_unit_t

amdsmi_metric_unit_t

Metric Unit.

Definition: amdsmi.h:2011

amdsmi_link_status_t

amdsmi_link_status_t

Link Status.

Definition: amdsmi.h:630

amdsmi_ecc_correction_schema_support_t

amdsmi_ecc_correction_schema_support_t

The values of this enum are used to identify supported ecc correction schema.

Definition: amdsmi.h:1683

amdsmi_event_driver_t

amdsmi_event_driver_t

Event Driver.

Definition: amdsmi.h:1284

AMDSMI_MAX_BLACK_LIST_ELEMENTS

#define AMDSMI_MAX_BLACK_LIST_ELEMENTS

Maximum number of black list elements for device access control.

Definition: amdsmi.h:184

amdsmi_memory_partition_type_t

amdsmi_memory_partition_type_t

Memory Partitions.

Definition: amdsmi.h:210

AMDSMI_MEMORY_PARTITION_NPS8

@ AMDSMI_MEMORY_PARTITION_NPS8

Definition: amdsmi.h:220

AMDSMI_MEMORY_PARTITION_NPS1

@ AMDSMI_MEMORY_PARTITION_NPS1

Definition: amdsmi.h:212

AMDSMI_MEMORY_PARTITION_NPS2

@ AMDSMI_MEMORY_PARTITION_NPS2

Definition: amdsmi.h:214

AMDSMI_MEMORY_PARTITION_NPS4

@ AMDSMI_MEMORY_PARTITION_NPS4

Definition: amdsmi.h:217

AMDSMI_MAX_NIC_RDMA_DEV

#define AMDSMI_MAX_NIC_RDMA_DEV

Maximum number of NIC RDMA devices.

Definition: amdsmi.h:2459

amdsmi_event_iov_t

amdsmi_event_iov_t

Event IOV.

Definition: amdsmi.h:1420

amdsmi_guard_state_t

amdsmi_guard_state_t

Guard State.

Definition: amdsmi.h:1791

amdsmi_sched_block_t

amdsmi_sched_block_t

Schedule Block.

Definition: amdsmi.h:1802

amdsmi_processor_handle

void * amdsmi_processor_handle

opaque handler point to underlying implementation

Definition: amdsmi.h:59

amdsmi_event_gpu_t

amdsmi_event_gpu_t

Below are the error subcodes of each category.

Definition: amdsmi.h:1266

amdsmi_cache_property_type_t

amdsmi_cache_property_type_t

cache properties

Definition: amdsmi.h:455

AMDSMI_CACHE_PROPERTY_ENABLED

@ AMDSMI_CACHE_PROPERTY_ENABLED

Cache enabled.

Definition: amdsmi.h:456

AMDSMI_CACHE_PROPERTY_INST_CACHE

@ AMDSMI_CACHE_PROPERTY_INST_CACHE

Instruction cache.

Definition: amdsmi.h:458

AMDSMI_CACHE_PROPERTY_DATA_CACHE

@ AMDSMI_CACHE_PROPERTY_DATA_CACHE

Data cache.

Definition: amdsmi.h:457

AMDSMI_CACHE_PROPERTY_SIMD_CACHE

@ AMDSMI_CACHE_PROPERTY_SIMD_CACHE

Single Instruction, Multiple Data Cache.

Definition: amdsmi.h:460

AMDSMI_CACHE_PROPERTY_CPU_CACHE

@ AMDSMI_CACHE_PROPERTY_CPU_CACHE

CPU cache.

Definition: amdsmi.h:459

amdsmi_event_mmsch_t

amdsmi_event_mmsch_t

Event MM Schedule.

Definition: amdsmi.h:1646

AMDSMI_MAX_DEVICES

#define AMDSMI_MAX_DEVICES

Maximum number of devices supported.

Definition: amdsmi.h:159

amdsmi_status_t

amdsmi_status_t

Error codes returned by amdsmi functions.

Definition: amdsmi.h:70

AMDSMI_STATUS_NOT_INIT

@ AMDSMI_STATUS_NOT_INIT

Processor not initialized.

Definition: amdsmi.h:96

AMDSMI_STATUS_NON_AMD_CPU

@ AMDSMI_STATUS_NON_AMD_CPU

System has different cpu than AMD.

Definition: amdsmi.h:106

AMDSMI_STATUS_DIRECTORY_NOT_FOUND

@ AMDSMI_STATUS_DIRECTORY_NOT_FOUND

Error when a directory is not found, maps to ENOTDIR.

Definition: amdsmi.h:92

AMDSMI_STATUS_INVAL

@ AMDSMI_STATUS_INVAL

Invalid parameters.

Definition: amdsmi.h:73

AMDSMI_STATUS_BUSY

@ AMDSMI_STATUS_BUSY

Processor busy.

Definition: amdsmi.h:94

AMDSMI_STATUS_UNKNOWN_ERROR

@ AMDSMI_STATUS_UNKNOWN_ERROR

An unknown error occurred.

Definition: amdsmi.h:121

AMDSMI_STATUS_DRIVER_NOT_LOADED

@ AMDSMI_STATUS_DRIVER_NOT_LOADED

Processor driver not loaded.

Definition: amdsmi.h:98

AMDSMI_STATUS_FILE_ERROR

@ AMDSMI_STATUS_FILE_ERROR

Problem accessing a file.

Definition: amdsmi.h:86

AMDSMI_STATUS_DRM_ERROR

@ AMDSMI_STATUS_DRM_ERROR

Error when call libdrm.

Definition: amdsmi.h:78

AMDSMI_STATUS_CORRUPTED_EEPROM

@ AMDSMI_STATUS_CORRUPTED_EEPROM

EEPROM is corrupted.

Definition: amdsmi.h:118

AMDSMI_STATUS_ARG_PTR_NULL

@ AMDSMI_STATUS_ARG_PTR_NULL

Parsed argument is invalid.

Definition: amdsmi.h:115

AMDSMI_STATUS_IO

@ AMDSMI_STATUS_IO

I/O Error.

Definition: amdsmi.h:84

AMDSMI_STATUS_NO_HSMP_DRV

@ AMDSMI_STATUS_NO_HSMP_DRV

HSMP driver not found.

Definition: amdsmi.h:109

AMDSMI_STATUS_HSMP_TIMEOUT

@ AMDSMI_STATUS_HSMP_TIMEOUT

HSMP message timed out.

Definition: amdsmi.h:112

AMDSMI_STATUS_NO_DATA

@ AMDSMI_STATUS_NO_DATA

No data was found for a given input.

Definition: amdsmi.h:101

AMDSMI_STATUS_RETRY

@ AMDSMI_STATUS_RETRY

Retry operation.

Definition: amdsmi.h:81

AMDSMI_STATUS_UNEXPECTED_SIZE

@ AMDSMI_STATUS_UNEXPECTED_SIZE

An unexpected amount of data was read.

Definition: amdsmi.h:103

AMDSMI_STATUS_SETTING_UNAVAILABLE

@ AMDSMI_STATUS_SETTING_UNAVAILABLE

Setting is not available.

Definition: amdsmi.h:117

AMDSMI_STATUS_FILE_NOT_FOUND

@ AMDSMI_STATUS_FILE_NOT_FOUND

file or directory not found

Definition: amdsmi.h:114

AMDSMI_STATUS_INTERNAL_EXCEPTION

@ AMDSMI_STATUS_INTERNAL_EXCEPTION

An internal exception was caught.

Definition: amdsmi.h:88

AMDSMI_STATUS_NO_HSMP_SUP

@ AMDSMI_STATUS_NO_HSMP_SUP

HSMP not supported.

Definition: amdsmi.h:110

AMDSMI_STATUS_MAP_ERROR

@ AMDSMI_STATUS_MAP_ERROR

The internal library error did not map to a status code.

Definition: amdsmi.h:120

AMDSMI_STATUS_FAIL_LOAD_SYMBOL

@ AMDSMI_STATUS_FAIL_LOAD_SYMBOL

Fail to load symbol.

Definition: amdsmi.h:77

AMDSMI_STATUS_INSUFFICIENT_SIZE

@ AMDSMI_STATUS_INSUFFICIENT_SIZE

Not enough resources were available for the operation.

Definition: amdsmi.h:102

AMDSMI_STATUS_INIT_ERROR

@ AMDSMI_STATUS_INIT_ERROR

An error occurred when initializing internal data structures.

Definition: amdsmi.h:90

AMDSMI_STATUS_OUT_OF_RESOURCES

@ AMDSMI_STATUS_OUT_OF_RESOURCES

Not enough memory.

Definition: amdsmi.h:87

AMDSMI_STATUS_NO_SLOT

@ AMDSMI_STATUS_NO_SLOT

No more free slot.

Definition: amdsmi.h:97

AMDSMI_STATUS_NO_MSR_DRV

@ AMDSMI_STATUS_NO_MSR_DRV

MSR driver not found.

Definition: amdsmi.h:108

AMDSMI_STATUS_INTERRUPT

@ AMDSMI_STATUS_INTERRUPT

An interrupt occurred during execution of function.

Definition: amdsmi.h:83

AMDSMI_STATUS_SUCCESS

@ AMDSMI_STATUS_SUCCESS

Call succeeded.

Definition: amdsmi.h:71

AMDSMI_STATUS_NO_ENERGY_DRV

@ AMDSMI_STATUS_NO_ENERGY_DRV

Energy driver not found.

Definition: amdsmi.h:107

AMDSMI_STATUS_ADDRESS_FAULT

@ AMDSMI_STATUS_ADDRESS_FAULT

Bad address.

Definition: amdsmi.h:85

AMDSMI_STATUS_MORE_DATA

@ AMDSMI_STATUS_MORE_DATA

There is more data than the buffer size the user passed.

Definition: amdsmi.h:100

AMDSMI_STATUS_NOT_YET_IMPLEMENTED

@ AMDSMI_STATUS_NOT_YET_IMPLEMENTED

Not implemented yet.

Definition: amdsmi.h:75

AMDSMI_STATUS_NO_DRV

@ AMDSMI_STATUS_NO_DRV

No Energy and HSMP driver present.

Definition: amdsmi.h:113

AMDSMI_STATUS_NO_PERM

@ AMDSMI_STATUS_NO_PERM

Permission Denied.

Definition: amdsmi.h:82

AMDSMI_STATUS_NOT_FOUND

@ AMDSMI_STATUS_NOT_FOUND

Processor Not found.

Definition: amdsmi.h:95

AMDSMI_STATUS_FAIL_LOAD_MODULE

@ AMDSMI_STATUS_FAIL_LOAD_MODULE

Fail to load lib.

Definition: amdsmi.h:76

AMDSMI_STATUS_AMDGPU_RESTART_ERR

@ AMDSMI_STATUS_AMDGPU_RESTART_ERR

AMDGPU restart failed.

Definition: amdsmi.h:116

AMDSMI_STATUS_NOT_SUPPORTED

@ AMDSMI_STATUS_NOT_SUPPORTED

Command not supported.

Definition: amdsmi.h:74

AMDSMI_STATUS_UNEXPECTED_DATA

@ AMDSMI_STATUS_UNEXPECTED_DATA

The data read or provided to function is not what was expected.

Definition: amdsmi.h:104

AMDSMI_STATUS_API_FAILED

@ AMDSMI_STATUS_API_FAILED

API call failed.

Definition: amdsmi.h:79

AMDSMI_STATUS_TIMEOUT

@ AMDSMI_STATUS_TIMEOUT

Timeout in API call.

Definition: amdsmi.h:80

AMDSMI_STATUS_NO_HSMP_MSG_SUP

@ AMDSMI_STATUS_NO_HSMP_MSG_SUP

HSMP message/feature not supported.

Definition: amdsmi.h:111

AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS

@ AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS

The provided input is out of allowable or safe range.

Definition: amdsmi.h:89

AMDSMI_STATUS_REFCOUNT_OVERFLOW

@ AMDSMI_STATUS_REFCOUNT_OVERFLOW

An internal reference counter exceeded INT32_MAX.

Definition: amdsmi.h:91

AMDSMI_MAX_NUM_PM_POLICIES

#define AMDSMI_MAX_NUM_PM_POLICIES

Maximum number of power management policies.

Definition: amdsmi.h:150

amdsmi_guest_fw_load_status_t

amdsmi_guest_fw_load_status_t

Guest firmware load status.

Definition: amdsmi.h:1816

amdsmi_xgmi_fb_sharing_mode_t

amdsmi_xgmi_fb_sharing_mode_t

XGMI FB Sharing Mode.

Definition: amdsmi.h:1829

amdsmi_ptl_data_format_t

amdsmi_ptl_data_format_t

PTL (Peak Tops Limiter) data format types These correspond to the hardware data types used in matrix ...

Definition: amdsmi.h:645

AMDSMI_PTL_DATA_FORMAT_INVALID

@ AMDSMI_PTL_DATA_FORMAT_INVALID

Invalid format.

Definition: amdsmi.h:651

AMDSMI_PTL_DATA_FORMAT_I8

@ AMDSMI_PTL_DATA_FORMAT_I8

Integer 8-bit format.

Definition: amdsmi.h:646

AMDSMI_PTL_DATA_FORMAT_F64

@ AMDSMI_PTL_DATA_FORMAT_F64

Float 64-bit format.

Definition: amdsmi.h:650

AMDSMI_PTL_DATA_FORMAT_BF16

@ AMDSMI_PTL_DATA_FORMAT_BF16

Brain Float 16-bit format.

Definition: amdsmi.h:648

AMDSMI_PTL_DATA_FORMAT_F32

@ AMDSMI_PTL_DATA_FORMAT_F32

Float 32-bit format.

Definition: amdsmi.h:649

AMDSMI_PTL_DATA_FORMAT_F16

@ AMDSMI_PTL_DATA_FORMAT_F16

Float 16-bit format.

Definition: amdsmi.h:647

amdsmi_affinity_scope_t

amdsmi_affinity_scope_t

Scope for Numa affinity or Socket affinity.

Definition: amdsmi.h:610

AMDSMI_AFFINITY_SCOPE_NODE

@ AMDSMI_AFFINITY_SCOPE_NODE

Memory affinity as numa node.

Definition: amdsmi.h:611

AMDSMI_AFFINITY_SCOPE_SOCKET

@ AMDSMI_AFFINITY_SCOPE_SOCKET

socket affinity

Definition: amdsmi.h:612

amdsmi_temperature_metric_t

amdsmi_temperature_metric_t

Temperature Metrics. This enum is used to identify various temperature metrics. Corresponding values ...

Definition: amdsmi.h:394

AMDSMI_TEMP_CRITICAL_HYST

@ AMDSMI_TEMP_CRITICAL_HYST

Definition: amdsmi.h:405

AMDSMI_TEMP_CRITICAL

@ AMDSMI_TEMP_CRITICAL

Definition: amdsmi.h:403

AMDSMI_TEMP_OFFSET

@ AMDSMI_TEMP_OFFSET

Definition: amdsmi.h:417

AMDSMI_TEMP_EMERGENCY

@ AMDSMI_TEMP_EMERGENCY

Definition: amdsmi.h:407

AMDSMI_TEMP_LOWEST

@ AMDSMI_TEMP_LOWEST

Historical min temperature.

Definition: amdsmi.h:419

AMDSMI_TEMP_CRIT_MIN

@ AMDSMI_TEMP_CRIT_MIN

Definition: amdsmi.h:413

AMDSMI_TEMP_SHUTDOWN

@ AMDSMI_TEMP_SHUTDOWN

Shutdown temperature.

Definition: amdsmi.h:421

AMDSMI_TEMP_EMERGENCY_HYST

@ AMDSMI_TEMP_EMERGENCY_HYST

Definition: amdsmi.h:411

AMDSMI_TEMP_CURRENT

@ AMDSMI_TEMP_CURRENT

Current temperature.

Definition: amdsmi.h:395

AMDSMI_TEMP_MIN

@ AMDSMI_TEMP_MIN

Min temperature.

Definition: amdsmi.h:398

AMDSMI_TEMP_HIGHEST

@ AMDSMI_TEMP_HIGHEST

Historical max temperature.

Definition: amdsmi.h:420

AMDSMI_TEMP_CRIT_MIN_HYST

@ AMDSMI_TEMP_CRIT_MIN_HYST

Definition: amdsmi.h:415

AMDSMI_TEMP_MIN_HYST

@ AMDSMI_TEMP_MIN_HYST

Definition: amdsmi.h:401

AMDSMI_TEMP_MAX_HYST

@ AMDSMI_TEMP_MAX_HYST

Definition: amdsmi.h:399

AMDSMI_TEMP_MAX

@ AMDSMI_TEMP_MAX

Max temperature.

Definition: amdsmi.h:397

amdsmi_event_category_t

amdsmi_event_category_t

Event Category.

Definition: amdsmi.h:1242

amdsmi_cper_sev_t

amdsmi_cper_sev_t

Cper sev.

Definition: amdsmi.h:1053

AMDSMI_CPER_SEV_NUM

@ AMDSMI_CPER_SEV_NUM

CPER severity Number.

Definition: amdsmi.h:1057

AMDSMI_CPER_SEV_NON_FATAL_CORRECTED

@ AMDSMI_CPER_SEV_NON_FATAL_CORRECTED

CPER Non-Fatal Corrected severity.

Definition: amdsmi.h:1056

AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED

@ AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED

CPER Non-Fatal Uncorrected severity.

Definition: amdsmi.h:1054

AMDSMI_CPER_SEV_FATAL

@ AMDSMI_CPER_SEV_FATAL

CPER Fatal severity.

Definition: amdsmi.h:1055

AMDSMI_CPER_SEV_UNUSED

@ AMDSMI_CPER_SEV_UNUSED

CPER Unused severity.

Definition: amdsmi.h:1058

amdsmi_gpu_block_t

amdsmi_gpu_block_t

This enum is used to identify different GPU blocks.

Definition: amdsmi.h:468

AMDSMI_GPU_BLOCK_XGMI_WAFL

@ AMDSMI_GPU_BLOCK_XGMI_WAFL

XGMI block.

Definition: amdsmi.h:478

AMDSMI_GPU_BLOCK_GFX

@ AMDSMI_GPU_BLOCK_GFX

GFX block.

Definition: amdsmi.h:473

AMDSMI_GPU_BLOCK_IH

@ AMDSMI_GPU_BLOCK_IH

IH block.

Definition: amdsmi.h:488

AMDSMI_GPU_BLOCK_VCN

@ AMDSMI_GPU_BLOCK_VCN

VCN block.

Definition: amdsmi.h:486

AMDSMI_GPU_BLOCK_INVALID

@ AMDSMI_GPU_BLOCK_INVALID

Invalid block.

Definition: amdsmi.h:469

AMDSMI_GPU_BLOCK_MP0

@ AMDSMI_GPU_BLOCK_MP0

MP0 block.

Definition: amdsmi.h:482

AMDSMI_GPU_BLOCK_HDP

@ AMDSMI_GPU_BLOCK_HDP

HDP block.

Definition: amdsmi.h:477

AMDSMI_GPU_BLOCK_MPIO

@ AMDSMI_GPU_BLOCK_MPIO

MPIO block.

Definition: amdsmi.h:489

AMDSMI_GPU_BLOCK_ATHUB

@ AMDSMI_GPU_BLOCK_ATHUB

ATHUB block.

Definition: amdsmi.h:475

AMDSMI_GPU_BLOCK_MP1

@ AMDSMI_GPU_BLOCK_MP1

MP1 block.

Definition: amdsmi.h:483

AMDSMI_GPU_BLOCK_PCIE_BIF

@ AMDSMI_GPU_BLOCK_PCIE_BIF

PCIE_BIF block.

Definition: amdsmi.h:476

AMDSMI_GPU_BLOCK_SDMA

@ AMDSMI_GPU_BLOCK_SDMA

SDMA block.

Definition: amdsmi.h:472

AMDSMI_GPU_BLOCK_JPEG

@ AMDSMI_GPU_BLOCK_JPEG

JPEG block.

Definition: amdsmi.h:487

AMDSMI_GPU_BLOCK_UMC

@ AMDSMI_GPU_BLOCK_UMC

UMC block.

Definition: amdsmi.h:471

AMDSMI_GPU_BLOCK_FUSE

@ AMDSMI_GPU_BLOCK_FUSE

Fuse block.

Definition: amdsmi.h:484

AMDSMI_GPU_BLOCK_DF

@ AMDSMI_GPU_BLOCK_DF

DF block.

Definition: amdsmi.h:479

AMDSMI_GPU_BLOCK_MMHUB

@ AMDSMI_GPU_BLOCK_MMHUB

MMHUB block.

Definition: amdsmi.h:474

AMDSMI_GPU_BLOCK_SMN

@ AMDSMI_GPU_BLOCK_SMN

SMN block.

Definition: amdsmi.h:480

AMDSMI_GPU_BLOCK_SEM

@ AMDSMI_GPU_BLOCK_SEM

SEM block.

Definition: amdsmi.h:481

AMDSMI_GPU_BLOCK_MCA

@ AMDSMI_GPU_BLOCK_MCA

MCA block.

Definition: amdsmi.h:485

amdsmi_metric_name_t

amdsmi_metric_name_t

Metric Name.

Definition: amdsmi.h:1877

amdsmi_vf_sched_state_t

amdsmi_vf_sched_state_t

VF Schedule State.

Definition: amdsmi.h:1747

amdsmi_event_sched_t

amdsmi_event_sched_t

Event Schedule.

Definition: amdsmi.h:1527

amdsmi_driver_model_type_t

amdsmi_driver_model_type_t

The values of this enum are used to identify driver model type.

Definition: amdsmi.h:2074

amdsmi_temperature_type_t

amdsmi_temperature_type_t

This enumeration is used to indicate from which part of the processor a temperature reading should be...

Definition: amdsmi.h:318

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR

OAM X 0.4V HBM D voltage regulator temperature.

Definition: amdsmi.h:338

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3

VDDCR VDD3 voltage regulator temperature.

Definition: amdsmi.h:347

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC

OAM 0-1 HSC temperature.

Definition: amdsmi.h:368

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A

VDDCR SOC A voltage regulator temperature.

Definition: amdsmi.h:348

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC

OAM 6-7 HSC temperature.

Definition: amdsmi.h:371

AMDSMI_TEMPERATURE_TYPE_HBM_2

@ AMDSMI_TEMPERATURE_TYPE_HBM_2

High Bandwidth 2 temperature per stack.

Definition: amdsmi.h:326

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2

OAM X IBC 2 temperature.

Definition: amdsmi.h:335

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR

Retimer 4-5 0.9V voltage regulator temperature.

Definition: amdsmi.h:377

AMDSMI_TEMPERATURE_TYPE_HOTSPOT

@ AMDSMI_TEMPERATURE_TYPE_HOTSPOT

Hottest temperature reported for entire die.

Definition: amdsmi.h:321

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM

VDD 0.85V HBM voltage regulator temperature.

Definition: amdsmi.h:352

AMDSMI_TEMPERATURE_TYPE_HBM_0

@ AMDSMI_TEMPERATURE_TYPE_HBM_0

High Bandwidth 0 temperature per stack.

Definition: amdsmi.h:324

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2

VDDCR VDD2 voltage regulator temperature.

Definition: amdsmi.h:346

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC

UBB IBC temperature.

Definition: amdsmi.h:365

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D

VDDCR 1.1V HBM D voltage regulator temperature.

Definition: amdsmi.h:354

AMDSMI_TEMPERATURE_TYPE_JUNCTION

@ AMDSMI_TEMPERATURE_TYPE_JUNCTION

Synonymous with HOTSPOT.

Definition: amdsmi.h:322

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR

Retimer 4-5-6-7 1.2V voltage regulator temperature.

Definition: amdsmi.h:375

AMDSMI_TEMPERATURE_TYPE_HBM_3

@ AMDSMI_TEMPERATURE_TYPE_HBM_3

High Bandwidth 3 temperature per stack.

Definition: amdsmi.h:327

AMDSMI_TEMPERATURE_TYPE_VRAM

@ AMDSMI_TEMPERATURE_TYPE_VRAM

VRAM temperature on graphics card.

Definition: amdsmi.h:323

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC

OAM 2-3 HSC temperature.

Definition: amdsmi.h:369

AMDSMI_TEMPERATURE_TYPE_EDGE

@ AMDSMI_TEMPERATURE_TYPE_EDGE

Edge temperature.

Definition: amdsmi.h:319

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA

UBB UFPGA temperature.

Definition: amdsmi.h:366

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR

VDD USR voltage regulator temperature.

Definition: amdsmi.h:355

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR

OAM X 0.4V HBM B voltage regulator temperature.

Definition: amdsmi.h:337

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C

VDDCR SOC C voltage regulator temperature.

Definition: amdsmi.h:349

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A

VDDCR SOCIO A voltage regulator temperature.

Definition: amdsmi.h:350

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC

IBC HSC temperature.

Definition: amdsmi.h:382

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC

OAM 4-5 HSC temperature.

Definition: amdsmi.h:370

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR

Retimer 2-3 0.9V voltage regulator temperature.

Definition: amdsmi.h:378

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1

VDDCR VDD1 voltage regulator temperature.

Definition: amdsmi.h:345

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C

VDDCR SOCIO C voltage regulator temperature.

Definition: amdsmi.h:351

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR

Retimer 0-1 0.9V voltage regulator temperature.

Definition: amdsmi.h:376

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0

VDDCR VDD0 voltage regulator temperature.

Definition: amdsmi.h:343

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR

UBB FPGA 0.72V voltage regulator temperature.

Definition: amdsmi.h:372

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR

UBB FPGA 3.3V voltage regulator temperature.

Definition: amdsmi.h:373

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32

VDDIO 1.1V E32 voltage regulator temperature.

Definition: amdsmi.h:356

AMDSMI_TEMPERATURE_TYPE_PLX

@ AMDSMI_TEMPERATURE_TYPE_PLX

PCIe switch temperature.

Definition: amdsmi.h:328

AMDSMI_TEMPERATURE_TYPE_HBM_1

@ AMDSMI_TEMPERATURE_TYPE_HBM_1

High Bandwidth 1 temperature per stack.

Definition: amdsmi.h:325

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7

UBB OAM7 temperature.

Definition: amdsmi.h:364

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR

OAM 0-1-2-3 3.3V voltage regulator temperature.

Definition: amdsmi.h:380

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B

VDDCR 1.1V HBM B voltage regulator temperature.

Definition: amdsmi.h:353

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK

UBB back temperature.

Definition: amdsmi.h:363

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA

UBB FPGA temperature.

Definition: amdsmi.h:361

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X

Retimer X temperature.

Definition: amdsmi.h:332

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC

IBC temperature.

Definition: amdsmi.h:383

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR

OAM X VDD 1.8V voltage regulator temperature.

Definition: amdsmi.h:336

AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC

@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC

OAM X IBC temperature.

Definition: amdsmi.h:334

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR

Retimer 0-1-2-3 1.2V voltage regulator temperature.

Definition: amdsmi.h:374

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT

UBB front temperature.

Definition: amdsmi.h:362

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR

Retimer 6-7 0.9V voltage regulator temperature.

Definition: amdsmi.h:379

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR

OAM 4-5-6-7 3.3V voltage regulator temperature.

Definition: amdsmi.h:381

AMDSMI_TEMPERATURE_TYPE__MAX

@ AMDSMI_TEMPERATURE_TYPE__MAX

Maximum per GPU temperature type.

Definition: amdsmi.h:385

AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1

@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1

UBB OAM1 temperature.

Definition: amdsmi.h:367

AMDSMI_MAX_UUID_ELEMENTS

#define AMDSMI_MAX_UUID_ELEMENTS

Maximum number of UUID elements supported.

Definition: amdsmi.h:185

AMDSMI_MAX_CACHE_TYPES

#define AMDSMI_MAX_CACHE_TYPES

Maximum number of cache types.

Definition: amdsmi.h:161

AMDSMI_DFC_FW_NUMBER_OF_ENTRIES

#define AMDSMI_DFC_FW_NUMBER_OF_ENTRIES

Number of DFC firmware entries supported.

Definition: amdsmi.h:182

AMDSMI_MAX_NUM_NUMA_NODES

#define AMDSMI_MAX_NUM_NUMA_NODES

Maximum number of NUMA nodes.

Definition: amdsmi.h:165

amdsmi_set_gpu_accelerator_partition_profile

amdsmi_status_t amdsmi_set_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, uint32_t profile_index)

Set accelerator partition setting based on profile_index from amdsmi_get_gpu_accelerator_partition_pr...

amdsmi_get_gpu_accelerator_partition_profile_config

amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile_config(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_config_t *profile_config)

Returns gpu accelerator partition caps as currently configured in the system.

amdsmi_get_gpu_accelerator_partition_profile_config_global

amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile_config_global(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_config_global_t *config)

Returns all GPU accelerator partition capabilities which can be configured on the system.

amdsmi_get_gpu_accelerator_partition_profile

amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_t *profile, uint32_t *partition_id)

Returns current gpu accelerator partition cap.

amdsmi_get_fb_layout

amdsmi_status_t amdsmi_get_fb_layout(amdsmi_processor_handle processor_handle, amdsmi_pf_fb_info_t *info)

Returns the framebuffer info for the ASIC.

amdsmi_get_power_cap_info

amdsmi_status_t amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, amdsmi_power_cap_info_t *info)

Returns the power caps as currently configured in the system.

amdsmi_get_pcie_info

amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle, amdsmi_pcie_info_t *info)

Returns the PCIe info for the GPU.

amdsmi_get_gpu_vram_info

amdsmi_status_t amdsmi_get_gpu_vram_info(amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info)

Returns vram info.

amdsmi_get_gpu_board_info

amdsmi_status_t amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info)

Returns the board part number and board information for the requested device.

amdsmi_get_gpu_asic_info

amdsmi_status_t amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info)

Returns the ASIC information for the device.

amdsmi_get_xgmi_plpd

amdsmi_status_t amdsmi_get_xgmi_plpd(amdsmi_processor_handle processor_handle, amdsmi_dpm_policy_t *xgmi_plpd)

Get the xgmi per-link power down policy parameter for the processor.

amdsmi_set_xgmi_plpd

amdsmi_status_t amdsmi_set_xgmi_plpd(amdsmi_processor_handle processor_handle, uint32_t policy_id)

Set the xgmi per-link power down policy parameter for the processor.

amdsmi_get_soc_pstate

amdsmi_status_t amdsmi_get_soc_pstate(amdsmi_processor_handle processor_handle, amdsmi_dpm_policy_t *policy)

Get the soc pstate policy for the processor.

amdsmi_set_soc_pstate

amdsmi_status_t amdsmi_set_soc_pstate(amdsmi_processor_handle processor_handle, uint32_t policy_id)

Set the soc pstate policy for the processor.

amdsmi_reset_gpu

amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle)

Triggers a chain that resets all GPUs. It is not supported on virtual machine guest.

amdsmi_get_gpu_total_ecc_count

amdsmi_status_t amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec)

Returns the total number of ECC errors (correctable, uncorrectable and deferred) in the given GPU....

amdsmi_get_gpu_ecc_count

amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_gpu_block_t block, amdsmi_error_count_t *ec)

Retrieve the error counts for a GPU block. It is not supported on virtual machine guest.

amdsmi_get_gpu_ecc_enabled

amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle, uint64_t *enabled_blocks)

Retrieve the enabled ECC bit-mask. It is not supported on virtual machine guest.

amdsmi_status_code_to_string

amdsmi_status_t amdsmi_status_code_to_string(amdsmi_status_t status, const char **status_string)

Get a description of a provided AMDSMI error status.

amdsmi_event_destroy

amdsmi_status_t amdsmi_event_destroy(amdsmi_event_set set)

Destroys and frees an event set.

amdsmi_event_read

amdsmi_status_t amdsmi_event_read(amdsmi_event_set set, int64_t timeout_usec, amdsmi_event_entry_t *event)

The call blocks till timeout is expired to copy one event specified by the event set into the user pr...

amdsmi_event_create

amdsmi_status_t amdsmi_event_create(amdsmi_processor_handle *processor_list, uint32_t num_devices, uint64_t event_types, amdsmi_event_set *set)

Allocate a new event set notifier to monitor different types of issues with the GPU running virtualiz...

amdsmi_get_gpu_vbios_info

amdsmi_status_t amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info)

Returns the static information for the vBIOS on the device.

amdsmi_get_fw_info

amdsmi_status_t amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info)

Returns the firmware versions running on the device.

amdsmi_get_dfc_fw_table

amdsmi_status_t amdsmi_get_dfc_fw_table(amdsmi_processor_handle processor_handle, amdsmi_dfc_fw_t *info)

Returns the DFC fw table.

amdsmi_get_fw_error_records

amdsmi_status_t amdsmi_get_fw_error_records(amdsmi_processor_handle processor_handle, amdsmi_fw_error_record_t *records)

Gets firmware error records.

amdsmi_get_power_info

amdsmi_status_t amdsmi_get_power_info(amdsmi_processor_handle processor_handle, amdsmi_power_info_t *info)

Returns the current power and voltage of the GPU.

amdsmi_get_gpu_metrics

amdsmi_status_t amdsmi_get_gpu_metrics(amdsmi_processor_handle processor_handle, uint32_t *metrics_size, amdsmi_metric_t *metrics)

Return metrics information.

amdsmi_get_temp_metric

amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle, amdsmi_temperature_type_t sensor_type, amdsmi_temperature_metric_t metric, int64_t *temperature)

Get the temperature metric value for the specified metric, from the specified temperature sensor on t...

amdsmi_get_gpu_activity

amdsmi_status_t amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info)

Returns the current usage of the GPU engines (GFX, MM and MEM). Each usage is reported as a percentag...

amdsmi_get_clock_info

amdsmi_status_t amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info)

Returns the measurements of the clocks in the GPU for the GFX and multimedia engines and Memory....

amdsmi_is_gpu_power_management_enabled

amdsmi_status_t amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled)

Returns is power management enabled.

amdsmi_get_xgmi_fb_sharing_caps

amdsmi_status_t amdsmi_get_xgmi_fb_sharing_caps(amdsmi_processor_handle processor_handle, amdsmi_xgmi_fb_sharing_caps_t *caps)

Return XGMI capabilities.

amdsmi_set_xgmi_fb_sharing_mode_v2

amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode_v2(amdsmi_processor_handle *processor_list, uint32_t num_processors, amdsmi_xgmi_fb_sharing_mode_t mode)

Set XGMI framebuffer custom sharing mode.

amdsmi_get_xgmi_fb_sharing_mode_info

amdsmi_status_t amdsmi_get_xgmi_fb_sharing_mode_info(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_xgmi_fb_sharing_mode_t mode, uint8_t *fb_sharing)

Return XGMI framebuffer sharing information between two GPUs.

amdsmi_topo_get_numa_node_number

amdsmi_status_t amdsmi_topo_get_numa_node_number(amdsmi_processor_handle processor_handle, uint32_t *numa_node)

Retrieve the NUMA CPU node number for a device.

amdsmi_get_link_topology

amdsmi_status_t amdsmi_get_link_topology(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_link_topology_t *topology_info)

Return link topology information between two connected processors.

amdsmi_get_link_metrics

amdsmi_status_t amdsmi_get_link_metrics(amdsmi_processor_handle processor_handle, amdsmi_link_metrics_t *link_metrics)

Return link metric information.

amdsmi_topo_get_p2p_status

amdsmi_status_t amdsmi_topo_get_p2p_status(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_link_type_t *type, amdsmi_p2p_capability_t *cap)

Retrieve connection type and P2P capabilities between 2 GPUs.

amdsmi_set_xgmi_fb_sharing_mode

amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode(amdsmi_processor_handle processor_handle, amdsmi_xgmi_fb_sharing_mode_t mode)

Set XGMI framebuffer sharing mode.

amdsmi_get_link_topology_nearest

amdsmi_status_t amdsmi_get_link_topology_nearest(amdsmi_processor_handle processor_handle, amdsmi_link_type_t link_type, amdsmi_topology_nearest_t *topology_nearest_info)

Retrieve the set of GPUs that are nearest to a given device at a specific interconnectivity level.

amdsmi_get_guest_data

amdsmi_status_t amdsmi_get_guest_data(amdsmi_vf_handle_t vf_handle, amdsmi_guest_data_t *info)

Returns guest OS information of the queried VF. The fw_info field from the amdsmi_guest_data structur...

amdsmi_get_vf_fw_info

amdsmi_status_t amdsmi_get_vf_fw_info(amdsmi_vf_handle_t vf_handle, amdsmi_fw_info_t *info)

Returns the firmware versions running on a VF. In case the VM is not started on the VF,...

amdsmi_shut_down

amdsmi_status_t amdsmi_shut_down(void)

Shutdown the AMD SMI library.

amdsmi_init

amdsmi_status_t amdsmi_init(uint64_t init_flags)

Initialize the AMD SMI library.

amdsmi_get_gpu_memory_partition_config

amdsmi_status_t amdsmi_get_gpu_memory_partition_config(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_config_t *config)

Returns current gpu memory partition capabilities.

amdsmi_set_gpu_memory_partition_mode

amdsmi_status_t amdsmi_set_gpu_memory_partition_mode(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_type_t mode)

Sets memory partition mode Set memory partition setting based on memory_partition mode from amdsmi_ge...

amdsmi_get_nic_rdma_dev_info

amdsmi_status_t amdsmi_get_nic_rdma_dev_info(amdsmi_processor_handle processor_handle, amdsmi_nic_rdma_devices_info_t *info)

Retrieves RDMA devices information for the NIC.

amdsmi_get_nic_rdma_port_statistics

amdsmi_status_t amdsmi_get_nic_rdma_port_statistics(amdsmi_processor_handle processor_handle, uint32_t rdma_port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)

Retrieve RDMA port statistics for the NIC.

amdsmi_get_nic_port_info

amdsmi_status_t amdsmi_get_nic_port_info(amdsmi_processor_handle processor_handle, amdsmi_nic_port_info_t *info)

Retrieves PORT information for the NIC.

amdsmi_get_nic_vendor_statistics

amdsmi_status_t amdsmi_get_nic_vendor_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)

Retrieve vendor specific statistics for the NIC port.

amdsmi_get_nic_port_statistics

amdsmi_status_t amdsmi_get_nic_port_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)

Retrieve PORT statistics for the specified NIC port.

amdsmi_get_nic_driver_info

amdsmi_status_t amdsmi_get_nic_driver_info(amdsmi_processor_handle processor_handle, amdsmi_nic_driver_info_t *info)

Retrieves information about the NIC driver.

amdsmi_get_nic_bus_info

amdsmi_status_t amdsmi_get_nic_bus_info(amdsmi_processor_handle processor_handle, amdsmi_nic_bus_info_t *info)

Retrieves BUS information for the NIC.

amdsmi_get_nic_asic_info

amdsmi_status_t amdsmi_get_nic_asic_info(amdsmi_processor_handle processor_handle, amdsmi_nic_asic_info_t *info)

Retrieves ASIC information for the NIC.

amdsmi_get_nic_numa_info

amdsmi_status_t amdsmi_get_nic_numa_info(amdsmi_processor_handle processor_handle, amdsmi_nic_numa_info_t *info)

Retrieves NUMA information for the NIC.

amdsmi_get_npm_info

amdsmi_status_t amdsmi_get_npm_info(amdsmi_node_handle node_handle, amdsmi_npm_info_t *info)

Retrieves node power management (NPM) status and power limit for the specified node.

amdsmi_get_gpu_ptl_state

amdsmi_status_t amdsmi_get_gpu_ptl_state(amdsmi_processor_handle processor_handle, bool *enabled)

Get PTL enable/disable state.

amdsmi_set_gpu_ptl_state

amdsmi_status_t amdsmi_set_gpu_ptl_state(amdsmi_processor_handle processor_handle, bool enable)

Set PTL enable/disable state.

amdsmi_set_gpu_ptl_formats

amdsmi_status_t amdsmi_set_gpu_ptl_formats(amdsmi_processor_handle processor_handle, amdsmi_ptl_data_format_t data_format1, amdsmi_ptl_data_format_t data_format2)

Set PTL with specified preferred data formats.

amdsmi_get_gpu_ptl_formats

amdsmi_status_t amdsmi_get_gpu_ptl_formats(amdsmi_processor_handle processor_handle, amdsmi_ptl_data_format_t *data_format1, amdsmi_ptl_data_format_t *data_format2)

Get PTL (Peak Tops Limiter) formats for the processor.

amdsmi_get_gpu_cache_info

amdsmi_status_t amdsmi_get_gpu_cache_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info)

Returns gpu cache info.

amdsmi_set_power_cap

amdsmi_status_t amdsmi_set_power_cap(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, uint64_t cap)

Set the maximum gpu power cap value. It is not supported on virtual machine guest.

amdsmi_get_processor_handles

amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle, uint32_t *processor_count, amdsmi_processor_handle *processor_handles)

Get the list of the processor handles associated to a socket.

amdsmi_get_index_from_processor_handle

amdsmi_status_t amdsmi_get_index_from_processor_handle(amdsmi_processor_handle processor_handle, uint32_t *processor_index)

Returns the index of the given processor handle.

amdsmi_get_gpu_device_uuid

amdsmi_status_t amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid)

Returns the UUID of the device.

amdsmi_get_processor_type

amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle, processor_type_t *processor_type)

Get the processor type of the processor_handle.

amdsmi_get_socket_info

amdsmi_status_t amdsmi_get_socket_info(amdsmi_socket_handle socket_handle, size_t len, char *name)

Get information about the given socket.

amdsmi_get_node_handle

amdsmi_status_t amdsmi_get_node_handle(amdsmi_processor_handle processor_handle, amdsmi_node_handle *node_handle)

Get the node handle associated with processor handle.

amdsmi_get_gpu_virtualization_mode

amdsmi_status_t amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle, amdsmi_virtualization_mode_t *mode)

Returns the virtualization mode for the target device.

amdsmi_get_nic_device_bdf

amdsmi_status_t amdsmi_get_nic_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)

Returns BDF of the given NIC device.

amdsmi_get_processor_handle_from_uuid

amdsmi_status_t amdsmi_get_processor_handle_from_uuid(const char *uuid, amdsmi_processor_handle *processor_handle)

Returns the processor handle from the given UUID.

amdsmi_get_socket_handles

amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count, amdsmi_socket_handle *socket_handles)

Get the list of socket handles in the system.

amdsmi_get_vf_bdf

amdsmi_status_t amdsmi_get_vf_bdf(amdsmi_vf_handle_t vf_handle, amdsmi_bdf_t *bdf)

Returns BDF of the given device (VF).

amdsmi_get_vf_handle_from_bdf

amdsmi_status_t amdsmi_get_vf_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_vf_handle_t *vf_handle)

Returns VF handle from the given BDF.

amdsmi_get_processor_handle_from_bdf

amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_processor_handle *processor_handle)

Get processor handle with the matching bdf.

amdsmi_get_vf_handle_from_vf_index

amdsmi_status_t amdsmi_get_vf_handle_from_vf_index(amdsmi_processor_handle processor_handle, uint32_t fcn_idx, amdsmi_vf_handle_t *vf_handle)

Returns the handle of a virtual function given its index.

amdsmi_get_processor_handles_by_type

amdsmi_status_t amdsmi_get_processor_handles_by_type(amdsmi_socket_handle socket_handle, processor_type_t processor_type, amdsmi_processor_handle *processor_handles, uint32_t *processor_count)

Returns a list of processor handles of the specified type in the system.

amdsmi_get_vf_uuid

amdsmi_status_t amdsmi_get_vf_uuid(amdsmi_vf_handle_t processor_handle, unsigned int *uuid_length, char *uuid)

Returns the UUID of the VF.

amdsmi_get_gpu_device_bdf

amdsmi_status_t amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)

Returns BDF of the given GPU device.

amdsmi_get_processor_bdf

amdsmi_status_t amdsmi_get_processor_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)

Returns BDF of the given device.

amdsmi_get_vf_handle_from_uuid

amdsmi_status_t amdsmi_get_vf_handle_from_uuid(const char *uuid, amdsmi_vf_handle_t *vf_handle)

Returns the handle of a virtual function from the given UUID.

amdsmi_get_cpu_affinity_with_scope

amdsmi_status_t amdsmi_get_cpu_affinity_with_scope(amdsmi_processor_handle processor_handle, uint32_t cpu_set_size, uint64_t *cpu_set, amdsmi_affinity_scope_t scope)

Retrieves an array of uint64_t (sized to cpu_set_size) of bitmasks with the affinity within numa node...

amdsmi_get_processor_handle_from_index

amdsmi_status_t amdsmi_get_processor_handle_from_index(uint32_t processor_index, amdsmi_processor_handle *processor_handle)

Returns the processor handle from the given processor index.

amdsmi_get_gpu_ras_policy_info

amdsmi_status_t amdsmi_get_gpu_ras_policy_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_ras_policy_info_t *info)

Get the RAS policy info for a device.

amdsmi_get_afids_from_cper

amdsmi_status_t amdsmi_get_afids_from_cper(char *cper_buffer, uint32_t buf_size, uint64_t *afids, uint32_t *num_afids)

Get the AFIDs from CPER buffer.

amdsmi_get_bad_page_threshold

amdsmi_status_t amdsmi_get_bad_page_threshold(amdsmi_processor_handle processor_handle, uint32_t *threshold)

Get the bad page threshold for a device.

amdsmi_get_gpu_cper_entries

amdsmi_status_t amdsmi_get_gpu_cper_entries(amdsmi_processor_handle processor_handle, uint32_t severity_mask, char *cper_data, uint64_t *buf_size, amdsmi_cper_hdr_t **cper_hdrs, uint64_t *entry_count, uint64_t *cursor)

Retrieve CPER entries cached in the driver.

amdsmi_get_gpu_ras_feature_info

amdsmi_status_t amdsmi_get_gpu_ras_feature_info(amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature)

Returns RAS features info.

amdsmi_get_gpu_bad_page_info

amdsmi_status_t amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *bad_page_size, amdsmi_eeprom_table_record_t *bad_pages)

Returns the bad page info.

amdsmi_get_gpu_driver_info

amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info)

Returns the driver version information.

amdsmi_get_gpu_driver_model

amdsmi_status_t amdsmi_get_gpu_driver_model(amdsmi_processor_handle processor_handle, amdsmi_driver_model_type_t *model)

Returns the driver model information.

amdsmi_get_vf_info

amdsmi_status_t amdsmi_get_vf_info(amdsmi_vf_handle_t vf_handle, amdsmi_vf_info_t *config)

Returns the configuration structure for a VF.

amdsmi_get_vf_data

amdsmi_status_t amdsmi_get_vf_data(amdsmi_vf_handle_t vf_handle, amdsmi_vf_data_t *info)

Returns the data structure for a VF.

amdsmi_get_vf_partition_info

amdsmi_status_t amdsmi_get_vf_partition_info(amdsmi_processor_handle processor_handle, unsigned int vf_buffer_num, amdsmi_partition_info_t *info)

Returns the current framebuffer partitioning structure as currently configured by the driver.

amdsmi_get_num_vf

amdsmi_status_t amdsmi_get_num_vf(amdsmi_processor_handle processor_handle, uint32_t *num_vf_enabled, uint32_t *num_vf_supported)

Returns the number of VFs enabled by gpuv in the ASIC.

amdsmi_get_partition_profile_info

amdsmi_status_t amdsmi_get_partition_profile_info(amdsmi_processor_handle processor_handle, amdsmi_profile_info_t *profile_info)

Return the list of supported profiles on the given GPU device.

amdsmi_clear_vf_fb

amdsmi_status_t amdsmi_clear_vf_fb(amdsmi_vf_handle_t vf_handle)

Clear the framebuffer of a VF. If trying to clear the framebuffer of an active function,...

amdsmi_set_num_vf

amdsmi_status_t amdsmi_set_num_vf(amdsmi_processor_handle processor_handle, uint32_t num_vf)

Enable a given number of VF.

amdsmi_get_lib_version

amdsmi_status_t amdsmi_get_lib_version(amdsmi_version_t *version)

Get the build version information for the currently running build of AMDSMI.

amdsmi_accelerator_partition_profile_config_global_t

Definition: amdsmi.h:2444

amdsmi_accelerator_partition_profile_config_global_t::num_profiles

uint32_t num_profiles

The length of profiles array.

Definition: amdsmi.h:2445

amdsmi_accelerator_partition_profile_config_global_t::default_profile_index

uint32_t default_profile_index

The index of the default profile in the profiles array.

Definition: amdsmi.h:2448

amdsmi_accelerator_partition_profile_config_t

Accelerator Partition Profile Configurations.

Definition: amdsmi.h:924

amdsmi_accelerator_partition_profile_config_t::default_profile_index

uint32_t default_profile_index

The index of the default profile in the profiles array.

Definition: amdsmi.h:928

amdsmi_accelerator_partition_profile_config_t::num_profiles

uint32_t num_profiles

The length of profiles array.

Definition: amdsmi.h:925

amdsmi_accelerator_partition_profile_global_t

Definition: amdsmi.h:2438

amdsmi_accelerator_partition_profile_global_t::vf_mode

uint32_t vf_mode

Bitmask of VF modes (see amdsmi_vf_mode_t)

Definition: amdsmi.h:2440

amdsmi_accelerator_partition_profile_t

Accelerator Partition Resource Profile.

Definition: amdsmi.h:895

amdsmi_accelerator_partition_profile_t::profile_index

uint32_t profile_index

Index in the profiles array in amdsmi_accelerator_partition_profile_t.

Definition: amdsmi.h:899

amdsmi_accelerator_partition_profile_t::num_partitions

uint32_t num_partitions

On MI300X: SPX=>1, DPX=>2, QPX=>4, CPX=>8; length of resources.

Definition: amdsmi.h:897

amdsmi_accelerator_partition_profile_t::memory_caps

amdsmi_nps_caps_t memory_caps

Possible memory partition capabilities.

Definition: amdsmi.h:898

amdsmi_accelerator_partition_profile_t::profile_type

amdsmi_accelerator_partition_type_t profile_type

SPX, DPX, QPX, CPX and so on.

Definition: amdsmi.h:896

amdsmi_accelerator_partition_profile_t::num_resources

uint32_t num_resources

length of index_of_resources_profile

Definition: amdsmi.h:900

amdsmi_accelerator_partition_resource_profile_t

Accelerator Partition Resources. This struct is used to identify various partition resource profiles.

Definition: amdsmi.h:911

amdsmi_accelerator_partition_resource_profile_t::partition_resource

uint32_t partition_resource

Resources a partition can use, which may be shared.

Definition: amdsmi.h:914

amdsmi_accelerator_partition_resource_profile_t::num_partitions_share_resource

uint32_t num_partitions_share_resource

If it is greater than 1, then resource is shared.

Definition: amdsmi.h:915

amdsmi_asic_info_t

ASIC Information.

Definition: amdsmi.h:757

amdsmi_asic_info_t::target_graphics_version

uint64_t target_graphics_version

0xFFFFFFFFFFFFFFFF if not supported

Definition: amdsmi.h:767

amdsmi_asic_info_t::vendor_id

uint32_t vendor_id

Use 32 bit to be compatible with other platform.

Definition: amdsmi.h:759

amdsmi_asic_info_t::device_id

uint64_t device_id

The device ID of a GPU.

Definition: amdsmi.h:762

amdsmi_asic_info_t::oam_id

uint32_t oam_id

0xFFFFFFFF if not supported

Definition: amdsmi.h:765

amdsmi_asic_info_t::num_of_compute_units

uint32_t num_of_compute_units

0xFFFFFFFF if not supported

Definition: amdsmi.h:766

amdsmi_asic_info_t::subvendor_id

uint32_t subvendor_id

The subsystem vendor ID.

Definition: amdsmi.h:761

amdsmi_asic_info_t::rev_id

uint32_t rev_id

The revision ID of a GPU.

Definition: amdsmi.h:763

amdsmi_bdf_t::bdf_

Definition: amdsmi.h:660

amdsmi_board_info_t

Board Information.

Definition: amdsmi.h:938

amdsmi_clk_info_t

Clock Information.

Definition: amdsmi.h:835

amdsmi_clk_info_t::clk

uint32_t clk

In MHz.

Definition: amdsmi.h:836

amdsmi_clk_info_t::clk_locked

uint8_t clk_locked

True/False.

Definition: amdsmi.h:839

amdsmi_clk_info_t::clk_deep_sleep

uint8_t clk_deep_sleep

True/False.

Definition: amdsmi.h:840

amdsmi_clk_info_t::min_clk

uint32_t min_clk

In MHz.

Definition: amdsmi.h:837

amdsmi_clk_info_t::max_clk

uint32_t max_clk

In MHz.

Definition: amdsmi.h:838

amdsmi_cper_guid_t

Cper.

Definition: amdsmi.h:1113

amdsmi_cper_hdr_t

Definition: amdsmi.h:1138

amdsmi_cper_hdr_t::notify_type

amdsmi_cper_guid_t notify_type

CMC, MCE, can use amdsmi_cper_notifiy_type_t to decode.

Definition: amdsmi.h:1150

amdsmi_cper_hdr_t::persistence_info

uint64_t persistence_info

Reserved.

Definition: amdsmi.h:1153

amdsmi_cper_hdr_t::signature_end

uint32_t signature_end

0xFFFFFFFF

Definition: amdsmi.h:1141

amdsmi_cper_hdr_t::flags

uint32_t flags

Reserved.

Definition: amdsmi.h:1152

amdsmi_cper_hdr_t::partition_id

amdsmi_cper_guid_t partition_id

Reserved.

Definition: amdsmi.h:1148

amdsmi_cper_hdr_t::record_length

uint32_t record_length

Total size of CPER Entry.

Definition: amdsmi.h:1145

amdsmi_cper_timestamp_t

Definition: amdsmi.h:1117

amdsmi_cper_valid_bits_t::valid_bits_

Definition: amdsmi.h:1129

amdsmi_dfc_fw_data_t

DFC Firmware Data.

Definition: amdsmi.h:2299

amdsmi_dfc_fw_data_t::customer_ordinal

uint32_t customer_ordinal

only used in driver version on NV32+

Definition: amdsmi.h:2302

amdsmi_dfc_fw_header_t

DFC Firmware Header.

Definition: amdsmi.h:2267

amdsmi_dfc_fw_t

DFC Firmware.

Definition: amdsmi.h:2316

amdsmi_dfc_fw_ta_uuid_t

DFC Firmware TA UUID.

Definition: amdsmi.h:2290

amdsmi_dfc_fw_white_list_t

DFC Firmware White List.

Definition: amdsmi.h:2280

amdsmi_dpm_policy_entry_t

The dpm policy.

Definition: amdsmi.h:1009

amdsmi_dpm_policy_t

DPM Policy.

Definition: amdsmi.h:1021

amdsmi_dpm_policy_t::num_supported

uint32_t num_supported

The number of supported policies.

Definition: amdsmi.h:1022

amdsmi_dpm_policy_t::current

uint32_t current

The current policy index.

Definition: amdsmi.h:1023

amdsmi_driver_info_t

Driver Information.

Definition: amdsmi.h:793

amdsmi_eeprom_table_record_t

Structure representing an EEPROM table record for tracking memory errors.

Definition: amdsmi.h:2330

amdsmi_eeprom_table_record_t::retired_page

uint64_t retired_page

Bad page frame address.

Definition: amdsmi.h:2331

amdsmi_engine_usage_t

Engine Usage amdsmi_engine_usage_t: This structure holds common GPU activity values seen in both BM o...

Definition: amdsmi.h:823

amdsmi_engine_usage_t::gfx_activity

uint32_t gfx_activity

In %.

Definition: amdsmi.h:824

amdsmi_engine_usage_t::umc_activity

uint32_t umc_activity

In %.

Definition: amdsmi.h:825

amdsmi_engine_usage_t::mm_activity

uint32_t mm_activity

In %.

Definition: amdsmi.h:826

amdsmi_error_count_t

This structure holds error counts.

Definition: amdsmi.h:849

amdsmi_error_count_t::uncorrectable_count

uint64_t uncorrectable_count

Accumulated uncorrectable errors.

Definition: amdsmi.h:851

amdsmi_error_count_t::correctable_count

uint64_t correctable_count

Accumulated correctable errors.

Definition: amdsmi.h:850

amdsmi_error_count_t::deferred_count

uint64_t deferred_count

Accumulated deferred errors.

Definition: amdsmi.h:852

amdsmi_event_entry_t

Event Entry.

Definition: amdsmi.h:2095

amdsmi_event_entry_t::timestamp

uint64_t timestamp

UTC microseconds.

Definition: amdsmi.h:2098

amdsmi_fw_error_record_t

Firmware Error Record.

Definition: amdsmi.h:2361

amdsmi_fw_info_t

Firmware Information.

Definition: amdsmi.h:994

amdsmi_fw_load_error_record_t

Firmware Load Error Record.

Definition: amdsmi.h:2348

amdsmi_fw_load_error_record_t::timestamp

uint64_t timestamp

UTC microseconds.

Definition: amdsmi.h:2349

amdsmi_fw_load_error_record_t::status

uint16_t status

amdsmi_guest_fw_load_status

Definition: amdsmi.h:2352

amdsmi_gpu_cache_info_t::cache_

Definition: amdsmi.h:978

amdsmi_gpu_cache_info_t::cache_::num_cache_instance

uint32_t num_cache_instance

total number of instance of this cache type

Definition: amdsmi.h:983

amdsmi_gpu_cache_info_t::cache_::cache_size

uint32_t cache_size

In KB.

Definition: amdsmi.h:980

amdsmi_gpu_cache_info_t::cache_::max_num_cu_shared

uint32_t max_num_cu_shared

Indicates how many Compute Units share this cache instance.

Definition: amdsmi.h:982

amdsmi_gpu_cache_info_t::cache_::cache_properties

uint32_t cache_properties

amdsmi_cache_property_type_t which is a bitmask

Definition: amdsmi.h:979

amdsmi_gpu_cache_info_t

GPU Cache Information.

Definition: amdsmi.h:976

amdsmi_gpu_ras_policy_info_t

Ras policy info structure for storing version and different ras policy version structures.

Definition: amdsmi.h:1097

amdsmi_gpu_ras_policy_v4_0_t

Ras policy v4.0.

Definition: amdsmi.h:1086

amdsmi_gpu_ras_policy_v4_0_t::dram_critical_region_threshold

uint16_t dram_critical_region_threshold

Critical region UCE threshold.

Definition: amdsmi.h:1088

amdsmi_gpu_ras_policy_v4_0_t::dram_non_critical_region_threshold

uint16_t dram_non_critical_region_threshold

Non-critical region UCE threshold.

Definition: amdsmi.h:1087

amdsmi_guard_info_t

Guard Information.

Definition: amdsmi.h:2160

amdsmi_guest_data_t

Guest Data.

Definition: amdsmi.h:2256

amdsmi_guest_data_t::fb_usage

uint32_t fb_usage

guest framebuffer usage in MB

Definition: amdsmi.h:2258

amdsmi_handshake_t

Handshake.

Definition: amdsmi.h:2114

amdsmi_link_metrics_t::_links

Definition: amdsmi.h:711

amdsmi_link_metrics_t::_links::write

uint64_t write

total data transfered for each link in KB

Definition: amdsmi.h:717

amdsmi_link_metrics_t::_links::link_status

amdsmi_link_status_t link_status

HW status of the link.

Definition: amdsmi.h:718

amdsmi_link_metrics_t::_links::read

uint64_t read

total data received for each link in KB

Definition: amdsmi.h:716

amdsmi_link_metrics_t::_links::bit_rate

uint32_t bit_rate

current link speed in Gb/s

Definition: amdsmi.h:713

amdsmi_link_metrics_t::_links::link_type

amdsmi_link_type_t link_type

type of the link

Definition: amdsmi.h:715

amdsmi_link_metrics_t::_links::bdf

amdsmi_bdf_t bdf

bdf of the destination gpu

Definition: amdsmi.h:712

amdsmi_link_metrics_t::_links::max_bandwidth

uint32_t max_bandwidth

max bandwidth of the link in Gb/s

Definition: amdsmi.h:714

amdsmi_link_metrics_t

Link Metrics.

Definition: amdsmi.h:709

amdsmi_link_metrics_t::num_links

uint32_t num_links

number of links

Definition: amdsmi.h:710

amdsmi_link_topology_t

Link Topology.

Definition: amdsmi.h:2372

amdsmi_link_topology_t::weight

uint64_t weight

link weight

Definition: amdsmi.h:2373

amdsmi_link_topology_t::link_type

amdsmi_link_type_t link_type

type of the link

Definition: amdsmi.h:2375

amdsmi_link_topology_t::num_hops

uint8_t num_hops

number of hops

Definition: amdsmi.h:2376

amdsmi_link_topology_t::link_status

amdsmi_link_status_t link_status

HW status of the link.

Definition: amdsmi.h:2374

amdsmi_link_topology_t::fb_sharing

uint8_t fb_sharing

framebuffer sharing flag

Definition: amdsmi.h:2377

amdsmi_memory_partition_config_t::numa_range_

Definition: amdsmi.h:882

amdsmi_memory_partition_config_t

Memory Partition Configuration. This structure is used to identify various memory partition configura...

Definition: amdsmi.h:878

amdsmi_metric_t

Metric.

Definition: amdsmi.h:2414

amdsmi_metric_t::res_group

amdsmi_metric_res_group_t res_group

Resource group this metric belongs to.

Definition: amdsmi.h:2421

amdsmi_metric_t::res_subgroup

amdsmi_metric_res_subgroup_t res_subgroup

Resource subgroup this metric belongs to.

Definition: amdsmi.h:2422

amdsmi_metric_t::flags

uint32_t flags

used to determine type of the metric (amdsmi_metric_type_t)

Definition: amdsmi.h:2418

amdsmi_metric_t::res_instance

uint32_t res_instance

Resource instance this metric belongs to.

Definition: amdsmi.h:2423

amdsmi_metric_t::vf_mask

uint32_t vf_mask

Mask of all active VFs + PF that this metric applies to.

Definition: amdsmi.h:2419

amdsmi_nic_asic_info_t

NIC asic information.

Definition: amdsmi.h:2479

amdsmi_nic_bus_info_t

NIC bus information.

Definition: amdsmi.h:2497

amdsmi_nic_bus_info_t::max_pcie_speed

uint32_t max_pcie_speed

maximum PCIe speed in GT/s

Definition: amdsmi.h:2500

amdsmi_nic_driver_info_t

NIC driver information.

Definition: amdsmi.h:2591

amdsmi_nic_fw_info_t

NIC firmware information collection.

Definition: amdsmi.h:2530

amdsmi_nic_fw_t

NIC firmware information.

Definition: amdsmi.h:2520

amdsmi_nic_numa_info_t

NIC NUMA information.

Definition: amdsmi.h:2510

amdsmi_nic_port_info_t

NIC port information collection.

Definition: amdsmi.h:2581

amdsmi_nic_port_t

NIC port information.

Definition: amdsmi.h:2557

amdsmi_nic_port_t::active_fec

uint32_t active_fec

Active FEC modes bitmask (see about FEC modes in the description)

Definition: amdsmi.h:2569

amdsmi_nic_rdma_dev_info_t

NIC RDMA device information.

Definition: amdsmi.h:2614

amdsmi_nic_rdma_devices_info_t

NIC RDMA devices information collection.

Definition: amdsmi.h:2629

amdsmi_nic_rdma_port_info_t

NIC RDMA port information.

Definition: amdsmi.h:2601

amdsmi_nic_stat_t

Structure for NIC statistic name-value pairs.

Definition: amdsmi.h:2469

amdsmi_npm_info_t

NPM info.

Definition: amdsmi.h:965

amdsmi_npm_info_t::status

amdsmi_npm_status_t status

NPM status (enabled/disabled).

Definition: amdsmi.h:966

amdsmi_npm_info_t::limit

uint64_t limit

Node-level power limit in Watts.

Definition: amdsmi.h:967

amdsmi_nps_caps_t::nps_flags_

Definition: amdsmi.h:862

amdsmi_nps_caps_t::nps_flags_::nps8_cap

uint32_t nps8_cap

bool 1 = true; 0 = false

Definition: amdsmi.h:866

amdsmi_nps_caps_t::nps_flags_::nps4_cap

uint32_t nps4_cap

bool 1 = true; 0 = false

Definition: amdsmi.h:865

amdsmi_nps_caps_t::nps_flags_::nps2_cap

uint32_t nps2_cap

bool 1 = true; 0 = false

Definition: amdsmi.h:864

amdsmi_nps_caps_t::nps_flags_::nps1_cap

uint32_t nps1_cap

bool 1 = true; 0 = false

Definition: amdsmi.h:863

amdsmi_p2p_capability_t

IO Link P2P Capability.

Definition: amdsmi.h:952

amdsmi_p2p_capability_t::is_iolink_atomics_64bit

uint8_t is_iolink_atomics_64bit

1 = true, 0 = false, UINT8_MAX = Not defined

Definition: amdsmi.h:955

amdsmi_p2p_capability_t::is_iolink_atomics_32bit

uint8_t is_iolink_atomics_32bit

1 = true, 0 = false, UINT8_MAX = Not defined

Definition: amdsmi.h:954

amdsmi_p2p_capability_t::is_iolink_bi_directional

uint8_t is_iolink_bi_directional

1 = true, 0 = false, UINT8_MAX = Not defined

Definition: amdsmi.h:957

amdsmi_p2p_capability_t::is_iolink_coherent

uint8_t is_iolink_coherent

1 = true, 0 = false, UINT8_MAX = Not defined

Definition: amdsmi.h:953

amdsmi_p2p_capability_t::is_iolink_dma

uint8_t is_iolink_dma

1 = true, 0 = false, UINT8_MAX = Not defined

Definition: amdsmi.h:956

amdsmi_partition_info_t

Partition Information.

Definition: amdsmi.h:2149

amdsmi_pcie_info_t::pcie_metric_

Definition: amdsmi.h:689

amdsmi_pcie_info_t::pcie_metric_::pcie_nak_received_count

uint64_t pcie_nak_received_count

total number of NAKs issued on the PCIe link by the receiver

Definition: amdsmi.h:697

amdsmi_pcie_info_t::pcie_metric_::pcie_replay_count

uint64_t pcie_replay_count

total number of the replays issued on the PCIe link

Definition: amdsmi.h:693

amdsmi_pcie_info_t::pcie_metric_::pcie_width

uint16_t pcie_width

current PCIe width

Definition: amdsmi.h:690

amdsmi_pcie_info_t::pcie_metric_::pcie_speed

uint32_t pcie_speed

current PCIe speed in MT/s

Definition: amdsmi.h:691

amdsmi_pcie_info_t::pcie_metric_::pcie_bandwidth

uint32_t pcie_bandwidth

current PCIe bandwidth in Mb/s

Definition: amdsmi.h:692

amdsmi_pcie_info_t::pcie_metric_::pcie_l0_to_recovery_count

uint64_t pcie_l0_to_recovery_count

total number of times the PCIe link transitioned from L0 to the recovery state

Definition: amdsmi.h:694

amdsmi_pcie_info_t::pcie_metric_::pcie_nak_sent_count

uint64_t pcie_nak_sent_count

total number of NAKs issued on the PCIe link by the device

Definition: amdsmi.h:696

amdsmi_pcie_info_t::pcie_metric_::pcie_replay_roll_over_count

uint64_t pcie_replay_roll_over_count

total number of replay rollovers issued on the PCIe link

Definition: amdsmi.h:695

amdsmi_pcie_info_t::pcie_metric_::pcie_lc_perf_other_end_recovery_count

uint32_t pcie_lc_perf_other_end_recovery_count

PCIe other end recovery counter.

Definition: amdsmi.h:698

amdsmi_pcie_info_t::pcie_static_

Definition: amdsmi.h:681

amdsmi_pcie_info_t::pcie_static_::max_pcie_width

uint16_t max_pcie_width

maximum number of PCIe lanes

Definition: amdsmi.h:682

amdsmi_pcie_info_t::pcie_static_::max_pcie_interface_version

uint32_t max_pcie_interface_version

maximum PCIe link generation

Definition: amdsmi.h:686

amdsmi_pcie_info_t::pcie_static_::slot_type

amdsmi_card_form_factor_t slot_type

card form factor

Definition: amdsmi.h:685

amdsmi_pcie_info_t::pcie_static_::max_pcie_speed

uint32_t max_pcie_speed

maximum PCIe speed in GT/s

Definition: amdsmi.h:683

amdsmi_pcie_info_t::pcie_static_::pcie_interface_version

uint32_t pcie_interface_version

PCIe interface version.

Definition: amdsmi.h:684

amdsmi_pcie_info_t

pcie information

Definition: amdsmi.h:680

amdsmi_pf_fb_info_t

PF FB Information.

Definition: amdsmi.h:2123

amdsmi_pf_fb_info_t::pf_fb_reserved

uint32_t pf_fb_reserved

Total fb consumed by PF.

Definition: amdsmi.h:2125

amdsmi_pf_fb_info_t::min_vf_fb_usable

uint32_t min_vf_fb_usable

Minimum usable fb size in MB.

Definition: amdsmi.h:2129

amdsmi_pf_fb_info_t::fb_alignment

uint32_t fb_alignment

FB alignment.

Definition: amdsmi.h:2127

amdsmi_pf_fb_info_t::total_fb_size

uint32_t total_fb_size

Total GPU fb size in MB.

Definition: amdsmi.h:2124

amdsmi_pf_fb_info_t::max_vf_fb_usable

uint32_t max_vf_fb_usable

Maximum usable fb size in MB.

Definition: amdsmi.h:2128

amdsmi_pf_fb_info_t::pf_fb_offset

uint32_t pf_fb_offset

PF FB offset.

Definition: amdsmi.h:2126

amdsmi_power_cap_info_t

Power Cap Information.

Definition: amdsmi.h:729

amdsmi_power_cap_info_t::power_cap

uint64_t power_cap

current power cap Units uW {@linux_bm} or W {@host}

Definition: amdsmi.h:730

amdsmi_power_cap_info_t::dpm_cap

uint64_t dpm_cap

dpm power cap Units MHz {@linux_bm} or Hz {@host}

Definition: amdsmi.h:732

amdsmi_power_cap_info_t::max_power_cap

uint64_t max_power_cap

maximum power cap Units uW {@linux_bm} or W {@host}

Definition: amdsmi.h:734

amdsmi_power_cap_info_t::default_power_cap

uint64_t default_power_cap

default power cap Units uW {@linux_bm} or W {@host}

Definition: amdsmi.h:731

amdsmi_power_cap_info_t::min_power_cap

uint64_t min_power_cap

minimum power cap Units uW {@linux_bm} or W {@host}

Definition: amdsmi.h:733

amdsmi_power_info_t

Power Information.

Definition: amdsmi.h:777

amdsmi_power_info_t::soc_voltage

uint64_t soc_voltage

SOC voltage measurement in mV {@linux_bm} or V {@host}.

Definition: amdsmi.h:782

amdsmi_power_info_t::socket_power

uint64_t socket_power

Socket power in W {@linux_bm}, uW {@host}.

Definition: amdsmi.h:778

amdsmi_power_info_t::power_limit

uint32_t power_limit

The power limit in W {@linux_bm}, Linux only.

Definition: amdsmi.h:784

amdsmi_power_info_t::mem_voltage

uint64_t mem_voltage

MEM voltage measurement in mV {@linux_bm} or V {@host}.

Definition: amdsmi.h:783

amdsmi_power_info_t::current_socket_power

uint32_t current_socket_power

Current socket power in W {@linux_bm}, Linux only, Mi 300+ Series cards.

Definition: amdsmi.h:779

amdsmi_power_info_t::average_socket_power

uint32_t average_socket_power

Average socket power in W {@linux_bm}, Linux only, Navi + Mi 200 and earlier Series cards.

Definition: amdsmi.h:780

amdsmi_power_info_t::gfx_voltage

uint64_t gfx_voltage

GFX voltage measurement in mV {@linux_bm} or V {@host}.

Definition: amdsmi.h:781

amdsmi_profile_caps_info_t

Profile Caps Information.

Definition: amdsmi.h:2227

amdsmi_profile_info_t

Profile Information.

Definition: amdsmi.h:2241

amdsmi_ras_feature_t

This structure holds ras feature information.

Definition: amdsmi.h:1032

amdsmi_ras_feature_t::ras_eeprom_version

uint32_t ras_eeprom_version

Definition: amdsmi.h:1040

amdsmi_ras_feature_t::ecc_correction_schema_flag

uint32_t ecc_correction_schema_flag

Definition: amdsmi.h:1042

amdsmi_sched_info_t

Schedule Information.

Definition: amdsmi.h:2192

amdsmi_sched_info_t::boot_up_time

uint64_t boot_up_time

in microseconds

Definition: amdsmi.h:2194

amdsmi_topology_nearest_t

Topology Nearest.

Definition: amdsmi.h:2386

amdsmi_vbios_info_t

VBios Information.

Definition: amdsmi.h:743

amdsmi_version_t

This structure holds version information.

Definition: amdsmi.h:2432

amdsmi_version_t::minor

uint32_t minor

Minor version.

Definition: amdsmi.h:2434

amdsmi_version_t::major

uint32_t major

Major version.

Definition: amdsmi.h:2433

amdsmi_version_t::release

uint32_t release

Patch, build or stepping version.

Definition: amdsmi.h:2435

amdsmi_vf_data_t

VF Data.

Definition: amdsmi.h:2216

amdsmi_vf_fb_info_t

VF FB Information.

Definition: amdsmi.h:2138

amdsmi_vf_fb_info_t::fb_size

uint32_t fb_size

Size in MB Must be divisible by 16 and not less than 256.

Definition: amdsmi.h:2140

amdsmi_vf_fb_info_t::fb_offset

uint32_t fb_offset

Offset in MB from start of the framebuffer.

Definition: amdsmi.h:2139

amdsmi_vf_handle_t

VF Handle.

Definition: amdsmi.h:2086

amdsmi_vf_info_t

VF Information.

Definition: amdsmi.h:2181

amdsmi_vf_info_t::gfx_timeslice

uint32_t gfx_timeslice

Graphics timeslice in us, maximum value is 1000 ms.

Definition: amdsmi.h:2183

amdsmi_vram_info_t

VRam Information.

Definition: amdsmi.h:805

amdsmi_vram_info_t::vram_bit_width

uint32_t vram_bit_width

In bits.

Definition: amdsmi.h:809

amdsmi_vram_info_t::vram_size

uint64_t vram_size

vram size in MB

Definition: amdsmi.h:808

amdsmi_vram_info_t::vram_max_bandwidth

uint64_t vram_max_bandwidth

The VRAM max bandwidth at current memory clock (GB/s)

Definition: amdsmi.h:810

amdsmi_xgmi_fb_sharing_caps_t::cap_

Definition: amdsmi.h:2398

amdsmi_bdf_t

bdf types

Definition: amdsmi.h:659

amdsmi_cper_valid_bits_t

Definition: amdsmi.h:1128

amdsmi_nps_caps_t

This union holds memory partition bitmask.

Definition: amdsmi.h:861

amdsmi_xgmi_fb_sharing_caps_t

XGMI FB Sharing Caps.

Definition: amdsmi.h:2397