amdsmi.h Source File

amdsmi.h Source File#

AMD SMI: amdsmi.h Source File
amdsmi.h
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1 /*
2  * Copyright (c) Advanced Micro Devices, Inc. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy
5  * of this software and associated documentation files (the "Software"), to deal
6  * in the Software without restriction, including without limitation the rights
7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8  * copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20  * THE SOFTWARE.
21  */
22 
23 #ifndef __AMDSMI_H__
24 #define __AMDSMI_H__
25 
31 #ifdef __cplusplus
32 #include <cstdint>
33 extern "C" {
34 #else
35 #include <stdint.h>
36 #endif
37 
38 #include <stdbool.h>
39 #include <stddef.h>
40 
48 typedef enum {
49  AMDSMI_INIT_ALL_PROCESSORS = 0xFFFFFFFF,
50  AMDSMI_INIT_AMD_CPUS = (1 << 0),
51  AMDSMI_INIT_AMD_GPUS = (1 << 1),
52  AMDSMI_INIT_NON_AMD_CPUS = (1 << 2),
53  AMDSMI_INIT_NON_AMD_GPUS = (1 << 3),
54  AMDSMI_INIT_AMD_APUS = (AMDSMI_INIT_AMD_CPUS | AMDSMI_INIT_AMD_GPUS),
56  AMDSMI_INIT_AMD_NICS = (1 << 4)
57 } amdsmi_init_flags_t;
58 
64 typedef void *amdsmi_processor_handle;
65 typedef void *amdsmi_socket_handle;
66 
72 typedef enum {
73  AMDSMI_PROCESSOR_TYPE_UNKNOWN = 0,
74  AMDSMI_PROCESSOR_TYPE_AMD_GPU,
75  AMDSMI_PROCESSOR_TYPE_AMD_CPU,
76  AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU,
77  AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU,
78  AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE,
79  AMDSMI_PROCESSOR_TYPE_AMD_APU,
80  AMDSMI_PROCESSOR_TYPE_AMD_NIC,
81  AMDSMI_PROCESSOR_TYPE_BRCM_NIC,
82  AMDSMI_PROCESSOR_TYPE_BRCM_SWITCH
83 } processor_type_t;
84 
93 typedef enum {
94  AMDSMI_STATUS_SUCCESS = 0,
95  // Library usage errors
96  AMDSMI_STATUS_INVAL = 1,
97  AMDSMI_STATUS_NOT_SUPPORTED = 2,
98  AMDSMI_STATUS_NOT_YET_IMPLEMENTED = 3,
99  AMDSMI_STATUS_FAIL_LOAD_MODULE = 4,
100  AMDSMI_STATUS_FAIL_LOAD_SYMBOL = 5,
101  AMDSMI_STATUS_DRM_ERROR = 6,
102  AMDSMI_STATUS_API_FAILED = 7,
103  AMDSMI_STATUS_TIMEOUT = 8,
104  AMDSMI_STATUS_RETRY = 9,
105  AMDSMI_STATUS_NO_PERM = 10,
106  AMDSMI_STATUS_INTERRUPT = 11,
107  AMDSMI_STATUS_IO = 12,
108  AMDSMI_STATUS_ADDRESS_FAULT = 13,
109  AMDSMI_STATUS_FILE_ERROR = 14,
110  AMDSMI_STATUS_OUT_OF_RESOURCES = 15,
111  AMDSMI_STATUS_INTERNAL_EXCEPTION = 16,
112  AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS = 17,
113  AMDSMI_STATUS_INIT_ERROR = 18,
114  AMDSMI_STATUS_REFCOUNT_OVERFLOW = 19,
115  AMDSMI_STATUS_DIRECTORY_NOT_FOUND = 20,
116  // Processor related errors
117  AMDSMI_STATUS_BUSY = 30,
118  AMDSMI_STATUS_NOT_FOUND = 31,
119  AMDSMI_STATUS_NOT_INIT = 32,
120  AMDSMI_STATUS_NO_SLOT = 33,
121  AMDSMI_STATUS_DRIVER_NOT_LOADED = 34,
122  // Data and size errors
123  AMDSMI_STATUS_MORE_DATA = 39,
124  AMDSMI_STATUS_NO_DATA = 40,
125  AMDSMI_STATUS_INSUFFICIENT_SIZE = 41,
126  AMDSMI_STATUS_UNEXPECTED_SIZE = 42,
127  AMDSMI_STATUS_UNEXPECTED_DATA = 43,
128  //esmi errors
129  AMDSMI_STATUS_NON_AMD_CPU = 44,
130  AMDSMI_STATUS_NO_ENERGY_DRV = 45,
131  AMDSMI_STATUS_NO_MSR_DRV = 46,
132  AMDSMI_STATUS_NO_HSMP_DRV = 47,
133  AMDSMI_STATUS_NO_HSMP_SUP = 48,
134  AMDSMI_STATUS_NO_HSMP_MSG_SUP = 49,
135  AMDSMI_STATUS_HSMP_TIMEOUT = 50,
136  AMDSMI_STATUS_NO_DRV = 51,
137  AMDSMI_STATUS_FILE_NOT_FOUND = 52,
138  AMDSMI_STATUS_ARG_PTR_NULL = 53,
139  AMDSMI_STATUS_AMDGPU_RESTART_ERR = 54,
140  AMDSMI_STATUS_SETTING_UNAVAILABLE = 55,
141  AMDSMI_STATUS_CORRUPTED_EEPROM = 56,
142  // General errors
143  AMDSMI_STATUS_MAP_ERROR = 0xFFFFFFFE,
144  AMDSMI_STATUS_UNKNOWN_ERROR = 0xFFFFFFFF,
145 } amdsmi_status_t;
146 
152 #define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK 64
153 #define AMDSMI_MAX_NUM_PM_POLICIES 32
154 #define AMDSMI_MAX_CONTAINER_TYPE 2
155 
161 #define AMDSMI_MAX_MM_IP_COUNT 8
162 #define AMDSMI_MAX_DEVICES 32
163 #define AMDSMI_MAX_STRING_LENGTH 256
164 #define AMDSMI_MAX_CACHE_TYPES 10
165 #define AMDSMI_MAX_CP_PROFILE_RESOURCES 32
166 #define AMDSMI_MAX_ACCELERATOR_PARTITIONS 8
167 #define AMDSMI_MAX_ACCELERATOR_PROFILE 32
168 #define AMDSMI_MAX_NUM_NUMA_NODES 32
169 #define AMDSMI_GPU_UUID_SIZE 38
170 
176 #define MAX_NUMBER_OF_AFIDS_PER_RECORD 12
177 
183 #define AMDSMI_MAX_VF_COUNT 32
184 #define AMDSMI_MAX_DRIVER_NUM 2
185 #define AMDSMI_DFC_FW_NUMBER_OF_ENTRIES 9
186 #define AMDSMI_MAX_WHITE_LIST_ELEMENTS 16
187 #define AMDSMI_MAX_BLACK_LIST_ELEMENTS 64
188 #define AMDSMI_MAX_UUID_ELEMENTS 16
189 #define AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS 8
190 #define AMDSMI_MAX_ERR_RECORDS 10
191 #define AMDSMI_MAX_PROFILE_COUNT 16
192 #define AMDSMI_MAX_NUM_FREQUENCIES 33
193 
199 #define AMDSMI_TIME_FORMAT "%02d:%02d:%02d.%03d"
200 #define AMDSMI_DATE_FORMAT "%04d-%02d-%02d:%02d:%02d:%02d.%03d"
201 
207 typedef void *amdsmi_node_handle;
208 
214 typedef enum {
215  AMDSMI_MEMORY_PARTITION_UNKNOWN = 0,
216  AMDSMI_MEMORY_PARTITION_NPS1 = 1,
218  AMDSMI_MEMORY_PARTITION_NPS2 = 2,
221  AMDSMI_MEMORY_PARTITION_NPS4 = 4,
224  AMDSMI_MEMORY_PARTITION_NPS8 = 8,
229 } amdsmi_memory_partition_type_t;
230 
236 typedef enum {
237  AMDSMI_ACCELERATOR_PARTITION_INVALID = 0,
238  AMDSMI_ACCELERATOR_PARTITION_SPX,
240  AMDSMI_ACCELERATOR_PARTITION_DPX,
242  AMDSMI_ACCELERATOR_PARTITION_TPX,
244  AMDSMI_ACCELERATOR_PARTITION_QPX,
246  AMDSMI_ACCELERATOR_PARTITION_CPX,
248  AMDSMI_ACCELERATOR_PARTITION_MAX
249 } amdsmi_accelerator_partition_type_t;
250 
256 typedef enum {
257  AMDSMI_VRAM_TYPE_UNKNOWN = 0,
258  // HBM
259  AMDSMI_VRAM_TYPE_HBM = 1,
260  AMDSMI_VRAM_TYPE_HBM2 = 2,
261  AMDSMI_VRAM_TYPE_HBM2E = 3,
262  AMDSMI_VRAM_TYPE_HBM3 = 4,
263  AMDSMI_VRAM_TYPE_HBM3E = 5,
264  // DDR
265  AMDSMI_VRAM_TYPE_DDR2 = 10,
266  AMDSMI_VRAM_TYPE_DDR3 = 11,
267  AMDSMI_VRAM_TYPE_DDR4 = 12,
268  AMDSMI_VRAM_TYPE_DDR5 = 13,
269  // GDDR
270  AMDSMI_VRAM_TYPE_GDDR1 = 17,
271  AMDSMI_VRAM_TYPE_GDDR2 = 18,
272  AMDSMI_VRAM_TYPE_GDDR3 = 19,
273  AMDSMI_VRAM_TYPE_GDDR4 = 20,
274  AMDSMI_VRAM_TYPE_GDDR5 = 21,
275  AMDSMI_VRAM_TYPE_GDDR6 = 22,
276  AMDSMI_VRAM_TYPE_GDDR7 = 23,
277  // LPDDR
278  AMDSMI_VRAM_TYPE_LPDDR4 = 30,
279  AMDSMI_VRAM_TYPE_LPDDR5 = 31,
280  AMDSMI_VRAM_TYPE__MAX = AMDSMI_VRAM_TYPE_LPDDR5
281 } amdsmi_vram_type_t;
282 
288 typedef enum {
289  AMDSMI_ACCELERATOR_XCC,
290  AMDSMI_ACCELERATOR_ENCODER,
291  AMDSMI_ACCELERATOR_DECODER,
292  AMDSMI_ACCELERATOR_DMA,
293  AMDSMI_ACCELERATOR_JPEG,
294  AMDSMI_ACCELERATOR_MAX
295 } amdsmi_accelerator_partition_resource_type_t;
296 
302 typedef enum {
303  AMDSMI_CLK_TYPE_SYS = 0x0,
304  AMDSMI_CLK_TYPE_FIRST = AMDSMI_CLK_TYPE_SYS,
305  AMDSMI_CLK_TYPE_GFX = AMDSMI_CLK_TYPE_SYS,
306  AMDSMI_CLK_TYPE_DF,
308  AMDSMI_CLK_TYPE_DCEF,
310  AMDSMI_CLK_TYPE_SOC,
311  AMDSMI_CLK_TYPE_MEM,
312  AMDSMI_CLK_TYPE_PCIE,
313  AMDSMI_CLK_TYPE_VCLK0,
314  AMDSMI_CLK_TYPE_VCLK1,
315  AMDSMI_CLK_TYPE_DCLK0,
316  AMDSMI_CLK_TYPE_DCLK1,
317  AMDSMI_CLK_TYPE__MAX = AMDSMI_CLK_TYPE_DCLK1
318 } amdsmi_clk_type_t;
319 
326 typedef enum {
327  AMDSMI_TEMPERATURE_TYPE_EDGE,
328  AMDSMI_TEMPERATURE_TYPE_FIRST = AMDSMI_TEMPERATURE_TYPE_EDGE,
329  AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
330  AMDSMI_TEMPERATURE_TYPE_JUNCTION = AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
331  AMDSMI_TEMPERATURE_TYPE_VRAM,
332  AMDSMI_TEMPERATURE_TYPE_HBM_0,
333  AMDSMI_TEMPERATURE_TYPE_HBM_1,
334  AMDSMI_TEMPERATURE_TYPE_HBM_2,
335  AMDSMI_TEMPERATURE_TYPE_HBM_3,
336  AMDSMI_TEMPERATURE_TYPE_PLX,
337 
338  // GPU Board Node temperature
339  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_FIRST = 100,
340  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X
341  = AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_FIRST,
342  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC,
343  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2,
344  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR,
345  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR,
346  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR,
347  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_LAST = 149,
348 
349  // GPU Board VR (Voltage Regulator) temperature
350  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_FIRST = 150,
351  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0
352  = AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_FIRST,
353  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1,
354  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2,
355  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3,
356  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A,
357  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C,
358  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A,
359  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C,
360  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM,
361  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B,
362  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D,
363  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR,
364  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32,
365  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_LAST = 199,
366 
367  // Baseboard System temperature
368  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_FIRST = 200,
369  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA = AMDSMI_TEMPERATURE_TYPE_BASEBOARD_FIRST,
370  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT,
371  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK,
372  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7,
373  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC,
374  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA,
375  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1,
376  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC,
377  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC,
378  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC,
379  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC,
380  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR,
381  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR,
382  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR,
383  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR,
384  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR,
385  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR,
386  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR,
387  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR,
388  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR,
389  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR,
390  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC,
391  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC,
392  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_LAST = 249,
393  AMDSMI_TEMPERATURE_TYPE__MAX = AMDSMI_TEMPERATURE_TYPE_BASEBOARD_LAST
394 } amdsmi_temperature_type_t;
395 
402 typedef enum {
403  AMDSMI_TEMP_CURRENT = 0x0,
404  AMDSMI_TEMP_FIRST = AMDSMI_TEMP_CURRENT,
405  AMDSMI_TEMP_MAX,
406  AMDSMI_TEMP_MIN,
407  AMDSMI_TEMP_MAX_HYST,
409  AMDSMI_TEMP_MIN_HYST,
411  AMDSMI_TEMP_CRITICAL,
413  AMDSMI_TEMP_CRITICAL_HYST,
415  AMDSMI_TEMP_EMERGENCY,
419  AMDSMI_TEMP_EMERGENCY_HYST,
421  AMDSMI_TEMP_CRIT_MIN,
423  AMDSMI_TEMP_CRIT_MIN_HYST,
425  AMDSMI_TEMP_OFFSET,
427  AMDSMI_TEMP_LOWEST,
428  AMDSMI_TEMP_HIGHEST,
429  AMDSMI_TEMP_SHUTDOWN,
430  AMDSMI_TEMP_LAST = AMDSMI_TEMP_SHUTDOWN
431 } amdsmi_temperature_metric_t;
432 
438 typedef enum {
439  AMDSMI_CARD_FORM_FACTOR_PCIE,
440  AMDSMI_CARD_FORM_FACTOR_OAM,
441  AMDSMI_CARD_FORM_FACTOR_CEM,
442  AMDSMI_CARD_FORM_FACTOR_UNKNOWN
443 } amdsmi_card_form_factor_t;
444 
450 typedef enum {
451  AMDSMI_LINK_TYPE_INTERNAL = 0,
452  AMDSMI_LINK_TYPE_PCIE = 1,
453  AMDSMI_LINK_TYPE_XGMI = 2,
454  AMDSMI_LINK_TYPE_NOT_APPLICABLE = 3,
455  AMDSMI_LINK_TYPE_UNKNOWN = 4
456 } amdsmi_link_type_t;
457 
463 typedef enum {
464  AMDSMI_CACHE_PROPERTY_ENABLED = 0x00000001,
465  AMDSMI_CACHE_PROPERTY_DATA_CACHE = 0x00000002,
466  AMDSMI_CACHE_PROPERTY_INST_CACHE = 0x00000004,
467  AMDSMI_CACHE_PROPERTY_CPU_CACHE = 0x00000008,
468  AMDSMI_CACHE_PROPERTY_SIMD_CACHE = 0x00000010
469 } amdsmi_cache_property_type_t;
470 
476 typedef enum {
477  AMDSMI_GPU_BLOCK_INVALID = 0,
478  AMDSMI_GPU_BLOCK_FIRST = (1ULL << 0),
479  AMDSMI_GPU_BLOCK_UMC = AMDSMI_GPU_BLOCK_FIRST,
480  AMDSMI_GPU_BLOCK_SDMA = (1ULL << 1),
481  AMDSMI_GPU_BLOCK_GFX = (1ULL << 2),
482  AMDSMI_GPU_BLOCK_MMHUB = (1ULL << 3),
483  AMDSMI_GPU_BLOCK_ATHUB = (1ULL << 4),
484  AMDSMI_GPU_BLOCK_PCIE_BIF = (1ULL << 5),
485  AMDSMI_GPU_BLOCK_HDP = (1ULL << 6),
486  AMDSMI_GPU_BLOCK_XGMI_WAFL = (1ULL << 7),
487  AMDSMI_GPU_BLOCK_DF = (1ULL << 8),
488  AMDSMI_GPU_BLOCK_SMN = (1ULL << 9),
489  AMDSMI_GPU_BLOCK_SEM = (1ULL << 10),
490  AMDSMI_GPU_BLOCK_MP0 = (1ULL << 11),
491  AMDSMI_GPU_BLOCK_MP1 = (1ULL << 12),
492  AMDSMI_GPU_BLOCK_FUSE = (1ULL << 13),
493  AMDSMI_GPU_BLOCK_MCA = (1ULL << 14),
494  AMDSMI_GPU_BLOCK_VCN = (1ULL << 15),
495  AMDSMI_GPU_BLOCK_JPEG = (1ULL << 16),
496  AMDSMI_GPU_BLOCK_IH = (1ULL << 17),
497  AMDSMI_GPU_BLOCK_MPIO = (1ULL << 18),
498  AMDSMI_GPU_BLOCK_LAST = AMDSMI_GPU_BLOCK_MPIO,
499  AMDSMI_GPU_BLOCK_RESERVED = (1ULL << 63)
500 } amdsmi_gpu_block_t;
501 
508 typedef enum {
509  AMDSMI_FW_ID_SMU = 1,
511  AMDSMI_FW_ID_FIRST = AMDSMI_FW_ID_SMU,
512  AMDSMI_FW_ID_CP_CE,
513  AMDSMI_FW_ID_CP_PFP,
514  AMDSMI_FW_ID_CP_ME,
515  AMDSMI_FW_ID_CP_MEC_JT1,
516  AMDSMI_FW_ID_CP_MEC_JT2,
517  AMDSMI_FW_ID_CP_MEC1,
518  AMDSMI_FW_ID_CP_MEC2,
519  AMDSMI_FW_ID_RLC,
520  AMDSMI_FW_ID_SDMA0,
521  AMDSMI_FW_ID_SDMA1,
522  AMDSMI_FW_ID_SDMA2,
523  AMDSMI_FW_ID_SDMA3,
524  AMDSMI_FW_ID_SDMA4,
525  AMDSMI_FW_ID_SDMA5,
526  AMDSMI_FW_ID_SDMA6,
527  AMDSMI_FW_ID_SDMA7,
528  AMDSMI_FW_ID_VCN,
529  AMDSMI_FW_ID_UVD,
530  AMDSMI_FW_ID_VCE,
531  AMDSMI_FW_ID_ISP,
532  AMDSMI_FW_ID_DMCU_ERAM,
533  AMDSMI_FW_ID_DMCU_ISR,
534  AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM,
535  AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM,
536  AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL,
537  AMDSMI_FW_ID_RLC_V,
538  AMDSMI_FW_ID_MMSCH,
539  AMDSMI_FW_ID_PSP_SYSDRV,
540  AMDSMI_FW_ID_PSP_SOSDRV,
541  AMDSMI_FW_ID_PSP_TOC,
542  AMDSMI_FW_ID_PSP_KEYDB,
543  AMDSMI_FW_ID_DFC,
544  AMDSMI_FW_ID_PSP_SPL,
545  AMDSMI_FW_ID_DRV_CAP,
546  AMDSMI_FW_ID_MC,
547  AMDSMI_FW_ID_PSP_BL,
548  AMDSMI_FW_ID_CP_PM4,
549  AMDSMI_FW_ID_RLC_P,
550  AMDSMI_FW_ID_SEC_POLICY_STAGE2,
551  AMDSMI_FW_ID_REG_ACCESS_WHITELIST,
552  AMDSMI_FW_ID_IMU_DRAM,
553  AMDSMI_FW_ID_IMU_IRAM,
554  AMDSMI_FW_ID_SDMA_TH0,
555  AMDSMI_FW_ID_SDMA_TH1,
556  AMDSMI_FW_ID_CP_MES,
557  AMDSMI_FW_ID_MES_KIQ,
558  AMDSMI_FW_ID_MES_STACK,
559  AMDSMI_FW_ID_MES_THREAD1,
560  AMDSMI_FW_ID_MES_THREAD1_STACK,
561  AMDSMI_FW_ID_RLX6,
562  AMDSMI_FW_ID_RLX6_DRAM_BOOT,
563  AMDSMI_FW_ID_RS64_ME,
564  AMDSMI_FW_ID_RS64_ME_P0_DATA,
565  AMDSMI_FW_ID_RS64_ME_P1_DATA,
566  AMDSMI_FW_ID_RS64_PFP,
567  AMDSMI_FW_ID_RS64_PFP_P0_DATA,
568  AMDSMI_FW_ID_RS64_PFP_P1_DATA,
569  AMDSMI_FW_ID_RS64_MEC,
570  AMDSMI_FW_ID_RS64_MEC_P0_DATA,
571  AMDSMI_FW_ID_RS64_MEC_P1_DATA,
572  AMDSMI_FW_ID_RS64_MEC_P2_DATA,
573  AMDSMI_FW_ID_RS64_MEC_P3_DATA,
574  AMDSMI_FW_ID_PPTABLE,
575  AMDSMI_FW_ID_PSP_SOC,
576  AMDSMI_FW_ID_PSP_DBG,
577  AMDSMI_FW_ID_PSP_INTF,
578  AMDSMI_FW_ID_RLX6_CORE1,
579  AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1,
580  AMDSMI_FW_ID_RLCV_LX7,
581  AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST,
582  AMDSMI_FW_ID_ASD,
583  AMDSMI_FW_ID_TA_RAS,
584  AMDSMI_FW_ID_TA_XGMI,
585  AMDSMI_FW_ID_XGMI,
586  AMDSMI_FW_ID_RLC_SRLG,
587  AMDSMI_FW_ID_RLC_SRLS,
588  AMDSMI_FW_ID_PM,
589  AMDSMI_FW_ID_SMC,
590  AMDSMI_FW_ID_DMCU,
591  AMDSMI_FW_ID_PSP_RAS,
592  AMDSMI_FW_ID_P2S_TABLE,
593  AMDSMI_FW_ID_PLDM_BUNDLE,
594  AMDSMI_FW_ID__MAX
595 } amdsmi_fw_block_t;
596 
605 typedef enum {
606  AMDSMI_VIRTUALIZATION_MODE_UNKNOWN = 0,
607  AMDSMI_VIRTUALIZATION_MODE_BAREMETAL,
608  AMDSMI_VIRTUALIZATION_MODE_HOST,
609  AMDSMI_VIRTUALIZATION_MODE_GUEST,
610  AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH
611 } amdsmi_virtualization_mode_t;
612 
618 typedef enum {
619  AMDSMI_AFFINITY_SCOPE_NODE,
620  AMDSMI_AFFINITY_SCOPE_SOCKET
621 } amdsmi_affinity_scope_t;
622 
628 typedef enum {
629  AMDSMI_NPM_STATUS_DISABLED,
630  AMDSMI_NPM_STATUS_ENABLED
631 } amdsmi_npm_status_t;
632 
638 typedef enum {
639  AMDSMI_LINK_STATUS_ENABLED = 0,
640  AMDSMI_LINK_STATUS_DISABLED = 1,
641  AMDSMI_LINK_STATUS_INACTIVE = 2,
642  AMDSMI_LINK_STATUS_ERROR = 3
643 } amdsmi_link_status_t;
644 
653 typedef enum {
654  AMDSMI_PTL_DATA_FORMAT_I8 = 0x0,
655  AMDSMI_PTL_DATA_FORMAT_F16 = 0x1,
656  AMDSMI_PTL_DATA_FORMAT_BF16 = 0x2,
657  AMDSMI_PTL_DATA_FORMAT_F32 = 0x3,
658  AMDSMI_PTL_DATA_FORMAT_F64 = 0x4,
659  AMDSMI_PTL_DATA_FORMAT_F8 = 0x5,
660  AMDSMI_PTL_DATA_FORMAT_VECTOR = 0x6,
661  AMDSMI_PTL_DATA_FORMAT_INVALID = 0xFFFFFFFF
662 } amdsmi_ptl_data_format_t;
663 
669 typedef union {
670  struct bdf_ {
671  uint64_t function_number : 3;
672  uint64_t device_number : 5;
673  uint64_t bus_number : 8;
674  uint64_t domain_number : 48;
675  } bdf;
676  struct {
677  uint64_t function_number : 3;
678  uint64_t device_number : 5;
679  uint64_t bus_number : 8;
680  uint64_t domain_number : 48;
681  };
682  uint64_t as_uint;
683 } amdsmi_bdf_t;
684 
690 typedef struct {
691  struct pcie_static_ {
692  uint16_t max_pcie_width;
693  uint32_t max_pcie_speed;
694  uint32_t pcie_interface_version;
695  amdsmi_card_form_factor_t slot_type;
696  uint32_t max_pcie_interface_version;
697  uint64_t reserved[9];
698  } pcie_static;
699  struct pcie_metric_ {
700  uint16_t pcie_width;
701  uint32_t pcie_speed;
702  uint32_t pcie_bandwidth;
703  uint64_t pcie_replay_count;
704  uint64_t pcie_l0_to_recovery_count;
705  uint64_t pcie_replay_roll_over_count;
706  uint64_t pcie_nak_sent_count;
707  uint64_t pcie_nak_received_count;
708  uint32_t pcie_lc_perf_other_end_recovery_count;
709  uint64_t reserved[12];
710  } pcie_metric;
711  uint64_t reserved[32];
712 } amdsmi_pcie_info_t;
713 
719 typedef struct {
720  bool has_deep_sleep;
721  uint32_t num_supported;
722  uint32_t current;
723  uint64_t frequency[AMDSMI_MAX_NUM_FREQUENCIES];
725 } amdsmi_frequencies_t;
726 
736 typedef struct {
737  amdsmi_frequencies_t transfer_rate;
738  uint32_t lanes[AMDSMI_MAX_NUM_FREQUENCIES];
739 } amdsmi_pcie_bandwidth_t;
740 
746 typedef struct {
747  uint32_t num_links;
748  struct _links {
749  amdsmi_bdf_t bdf;
750  uint32_t bit_rate;
751  uint32_t max_bandwidth;
752  amdsmi_link_type_t link_type;
753  uint64_t read;
754  uint64_t write;
755  amdsmi_link_status_t link_status;
756  uint64_t reserved[1];
757  } links[AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK];
758  uint64_t reserved[7];
759 } amdsmi_link_metrics_t;
760 
766 typedef struct {
767  uint64_t power_cap;
768  uint64_t default_power_cap;
769  uint64_t dpm_cap;
770  uint64_t min_power_cap;
771  uint64_t max_power_cap;
772  uint64_t reserved[3];
773 } amdsmi_power_cap_info_t;
774 
780 typedef enum {
781  AMDSMI_POWER_CAP_TYPE_PPT0,
782  AMDSMI_POWER_CAP_TYPE_PPT1,
783 } amdsmi_power_cap_type_t;
784 
790 typedef struct {
791  char name[AMDSMI_MAX_STRING_LENGTH];
792  char build_date[AMDSMI_MAX_STRING_LENGTH];
793  char part_number[AMDSMI_MAX_STRING_LENGTH];
794  char version[AMDSMI_MAX_STRING_LENGTH];
795  char boot_firmware[AMDSMI_MAX_STRING_LENGTH];
796  uint64_t reserved[36];
797 } amdsmi_vbios_info_t;
798 
804 typedef struct {
805  char market_name[AMDSMI_MAX_STRING_LENGTH];
806  uint32_t vendor_id;
807  char vendor_name[AMDSMI_MAX_STRING_LENGTH];
808  uint32_t subvendor_id;
809  uint64_t device_id;
810  uint32_t rev_id;
811  char asic_serial[AMDSMI_MAX_STRING_LENGTH];
812  uint32_t oam_id;
813  uint32_t num_of_compute_units;
814  uint64_t target_graphics_version;
815  uint32_t subsystem_id;
816  uint64_t flags;
817  uint32_t reserved[18];
818 } amdsmi_asic_info_t;
819 
827 typedef struct {
828  uint64_t socket_power;
829  uint32_t current_socket_power;
830  uint32_t average_socket_power;
831  uint64_t gfx_voltage;
832  uint64_t soc_voltage;
833  uint64_t mem_voltage;
834  uint32_t power_limit;
835  uint64_t reserved[18];
836 } amdsmi_power_info_t;
837 
843 typedef struct {
844  char driver_version[AMDSMI_MAX_STRING_LENGTH];
845  char driver_date[AMDSMI_MAX_STRING_LENGTH];
846  char driver_name[AMDSMI_MAX_STRING_LENGTH];
847  uint64_t reserved[64];
848 } amdsmi_driver_info_t;
849 
855 typedef struct {
856  amdsmi_vram_type_t vram_type;
857  char vram_vendor[AMDSMI_MAX_STRING_LENGTH];
858  uint64_t vram_size;
859  uint32_t vram_bit_width;
860  uint64_t vram_max_bandwidth;
861  uint64_t reserved[37];
862 } amdsmi_vram_info_t;
863 
873 typedef struct {
874  uint32_t gfx_activity;
875  uint32_t umc_activity;
876  uint32_t mm_activity;
877  uint32_t reserved[13];
878 } amdsmi_engine_usage_t;
879 
885 typedef struct {
886  uint32_t clk;
887  uint32_t min_clk;
888  uint32_t max_clk;
889  uint8_t clk_locked;
890  uint8_t clk_deep_sleep;
891  uint32_t reserved[4];
892 } amdsmi_clk_info_t;
893 
899 typedef struct {
900  uint64_t correctable_count;
901  uint64_t uncorrectable_count;
902  uint64_t deferred_count;
903  uint64_t reserved[5];
904 } amdsmi_error_count_t;
905 
911 typedef union {
912  struct nps_flags_ {
913  uint32_t nps1_cap :1;
914  uint32_t nps2_cap :1;
915  uint32_t nps4_cap :1;
916  uint32_t nps8_cap :1;
917  uint32_t reserved :28;
918  } nps_flags;
919  uint32_t nps_cap_mask;
920 } amdsmi_nps_caps_t;
921 
928 typedef struct {
929  amdsmi_nps_caps_t partition_caps;
930  amdsmi_memory_partition_type_t mp_mode;
931  uint32_t num_numa_ranges;
932  struct numa_range_ {
933  amdsmi_vram_type_t memory_type;
934  uint64_t start;
935  uint64_t end;
936  } numa_range[AMDSMI_MAX_NUM_NUMA_NODES];
937  uint64_t reserved[11];
938 } amdsmi_memory_partition_config_t;
939 
945 typedef struct {
946  amdsmi_accelerator_partition_type_t profile_type;
947  uint32_t num_partitions;
948  amdsmi_nps_caps_t memory_caps;
949  uint32_t profile_index;
950  uint32_t num_resources;
951  uint32_t resources[AMDSMI_MAX_ACCELERATOR_PARTITIONS][AMDSMI_MAX_CP_PROFILE_RESOURCES];
952  uint64_t reserved[13];
953 } amdsmi_accelerator_partition_profile_t;
954 
961 typedef struct {
962  uint32_t profile_index;
963  amdsmi_accelerator_partition_resource_type_t resource_type;
964  uint32_t partition_resource;
965  uint32_t num_partitions_share_resource;
966  uint64_t reserved[6];
967 } amdsmi_accelerator_partition_resource_profile_t;
968 
974 typedef struct {
975  uint32_t num_profiles;
976  uint32_t num_resource_profiles;
977  amdsmi_accelerator_partition_resource_profile_t resource_profiles[AMDSMI_MAX_CP_PROFILE_RESOURCES];
978  uint32_t default_profile_index;
979  amdsmi_accelerator_partition_profile_t profiles[AMDSMI_MAX_ACCELERATOR_PROFILE];
980  uint64_t reserved[30];
981 } amdsmi_accelerator_partition_profile_config_t;
982 
988 typedef struct {
989  char model_number[AMDSMI_MAX_STRING_LENGTH];
990  char product_serial[AMDSMI_MAX_STRING_LENGTH];
991  char fru_id[AMDSMI_MAX_STRING_LENGTH];
992  char product_name[AMDSMI_MAX_STRING_LENGTH];
993  char manufacturer_name[AMDSMI_MAX_STRING_LENGTH];
994  uint64_t reserved[64];
995 } amdsmi_board_info_t;
996 
1002 typedef struct {
1003  uint8_t is_iolink_coherent;
1004  uint8_t is_iolink_atomics_32bit;
1005  uint8_t is_iolink_atomics_64bit;
1006  uint8_t is_iolink_dma;
1007  uint8_t is_iolink_bi_directional;
1008 } amdsmi_p2p_capability_t;
1009 
1015 typedef struct {
1016  amdsmi_npm_status_t status;
1017  uint64_t limit;
1018  uint64_t reserved[6];
1019 } amdsmi_npm_info_t;
1020 
1026 typedef struct {
1027  uint32_t num_cache_types;
1028  struct cache_ {
1029  uint32_t cache_properties;
1030  uint32_t cache_size;
1031  uint32_t cache_level;
1032  uint32_t max_num_cu_shared;
1033  uint32_t num_cache_instance;
1034  uint32_t reserved[3];
1035  } cache[AMDSMI_MAX_CACHE_TYPES];
1036  uint32_t reserved[15];
1037 } amdsmi_gpu_cache_info_t;
1038 
1044 typedef struct {
1045  uint8_t num_fw_info;
1046  struct fw_info_list_ {
1047  amdsmi_fw_block_t fw_id;
1048  uint64_t fw_version;
1049  uint64_t reserved[2];
1050  } fw_info_list[AMDSMI_FW_ID__MAX];
1051  uint32_t reserved[7];
1052 } amdsmi_fw_info_t;
1053 
1059 typedef struct {
1060  uint32_t policy_id;
1061  char policy_description[AMDSMI_MAX_STRING_LENGTH];
1062 } amdsmi_dpm_policy_entry_t;
1063 
1071 typedef struct {
1072  uint32_t num_supported;
1073  uint32_t current;
1074  amdsmi_dpm_policy_entry_t policies[AMDSMI_MAX_NUM_PM_POLICIES];
1075 } amdsmi_dpm_policy_t;
1076 
1082 typedef struct {
1083  uint32_t ras_eeprom_version;
1085  uint32_t ecc_correction_schema_flag;
1088  struct ras_info_ {
1089  uint32_t dram_ecc : 1;
1090  uint32_t sram_ecc : 1;
1091  uint32_t poisoning : 1;
1092  uint32_t rsvd : 29;
1093  } ras_info;
1094  bool needs_reboot;
1095 } amdsmi_ras_feature_t;
1096 
1102 typedef enum {
1103  AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED = 0,
1104  AMDSMI_CPER_SEV_FATAL = 1,
1105  AMDSMI_CPER_SEV_NON_FATAL_CORRECTED = 2,
1106  AMDSMI_CPER_SEV_NUM = 3,
1107  AMDSMI_CPER_SEV_UNUSED = 10
1108 } amdsmi_cper_sev_t;
1109 
1115 typedef enum {
1116  AMDSMI_CPER_NOTIFY_TYPE_CMC = 0x450eBDD72DCE8BB1,
1117  AMDSMI_CPER_NOTIFY_TYPE_CPE = 0x4a55D8434E292F96,
1118  AMDSMI_CPER_NOTIFY_TYPE_MCE = 0x4cc5919CE8F56FFE,
1119  AMDSMI_CPER_NOTIFY_TYPE_PCIE = 0x4dfc1A16CF93C01F,
1120  AMDSMI_CPER_NOTIFY_TYPE_INIT = 0x454a9308CC5263E8,
1121  AMDSMI_CPER_NOTIFY_TYPE_NMI = 0x42c9B7E65BAD89FF,
1122  AMDSMI_CPER_NOTIFY_TYPE_BOOT = 0x409aAB403D61A466,
1123  AMDSMI_CPER_NOTIFY_TYPE_DMAR = 0x4c27C6B3667DD791,
1124  AMDSMI_CPER_NOTIFY_TYPE_SEA = 0x11E4BBE89A78788A,
1125  AMDSMI_CPER_NOTIFY_TYPE_SEI = 0x4E87B0AE5C284C81,
1126  AMDSMI_CPER_NOTIFY_TYPE_PEI = 0x4214520409A9D5AC,
1127  AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT = 0x49A341DF69293BC9
1128 } amdsmi_cper_notify_type_t;
1129 
1135 typedef struct {
1136  uint16_t dram_non_critical_region_threshold;
1137  uint16_t dram_critical_region_threshold;
1138 } amdsmi_gpu_ras_policy_v4_0_t;
1139 
1146 typedef struct {
1147  uint8_t major_version;
1148  uint8_t minor_version;
1149  union policy_data_ {
1150  amdsmi_gpu_ras_policy_v4_0_t v4_0;
1151  uint64_t info[5];
1152  } policy_data;
1153 } amdsmi_gpu_ras_policy_info_t;
1154 
1155 #pragma pack(push, 1)
1156 
1162 typedef struct {
1163  unsigned char b[16];
1164 } amdsmi_cper_guid_t;
1165 
1166 typedef struct {
1167  uint8_t seconds;
1168  uint8_t minutes;
1169  uint8_t hours;
1170  uint8_t flag;
1171  uint8_t day;
1172  uint8_t month;
1173  uint8_t year;
1174  uint8_t century;
1175 } amdsmi_cper_timestamp_t;
1176 
1177 typedef union {
1178  struct valid_bits_ {
1179  uint32_t platform_id : 1;
1180  uint32_t timestamp : 1;
1181  uint32_t partition_id : 1;
1182  uint32_t reserved : 29;
1183  } valid_bits;
1184  uint32_t valid_mask;
1185 } amdsmi_cper_valid_bits_t;
1186 
1187 typedef struct {
1188  char signature[4];
1189  uint16_t revision;
1190  uint32_t signature_end;
1191  uint16_t sec_cnt;
1192  amdsmi_cper_sev_t error_severity;
1193  amdsmi_cper_valid_bits_t cper_valid_bits;
1194  uint32_t record_length;
1195  amdsmi_cper_timestamp_t timestamp;
1196  char platform_id[16];
1197  amdsmi_cper_guid_t partition_id;
1198  char creator_id[16];
1199  amdsmi_cper_guid_t notify_type;
1200  char record_id[8];
1201  uint32_t flags;
1202  uint64_t persistence_info;
1203  uint8_t reserved[12];
1204 } amdsmi_cper_hdr_t;
1205 
1206 #pragma pack(pop)
1207 
1213 #define SMI_VERSION_ALPHA_0 0x00000002
1214 #define SMI_VERSION_BETA_0 0x00000003
1215 #define SMI_VERSION_BETA_1 0x00000004
1216 #define SMI_VERSION_BETA_2 0x00000005
1217 #define SMI_VERSION_BETA_3 0x00000006
1218 #define SMI_VERSION_BETA_4 0x00000007
1219 
1227 #define AMDSMI_MASK_ALL (~0ULL)
1228 
1230 #define AMDSMI_MASK_DEFAULT ((1ULL << 62) - 1)
1231 
1233 #define AMDSMI_MASK_INIT (0ULL)
1234 
1236 #define AMDSMI_MASK_HIGH_AND_MED_SEVERITY (~((1ULL << 61) - 1))
1237 
1243 #define AMDSMI_MASK_HIGH_ERROR_SEVERITY_ONLY(mask) (mask & ((1ULL << 60) - 1))
1244 #define AMDSMI_MASK_INCLUDE_MED_ERROR_SEVERITY(mask) (mask | (1ULL << 60))
1245 #define AMDSMI_MASK_INCLUDE_LOW_ERROR_SEVERITY(mask) (mask | (1ULL << 61))
1246 #define AMDSMI_MASK_INCLUDE_WARN_SEVERITY(mask) (mask | (1ULL << 62))
1247 #define AMDSMI_MASK_INCLUDE_INFO_SEVERITY(mask) (mask | (1ULL << 63))
1248 
1254 #define AMDSMI_MASK_HIGH_SEVERITY_ONLY(mask) (mask & ((1ULL << 62) - 1))
1255 #define AMDSMI_MASK_INCLUDE_MED_SEVERITY(mask) AMDSMI_MASK_INCLUDE_WARN_SEVERITY(mask)
1256 #define AMDSMI_MASK_INCLUDE_LOW_SEVERITY(mask) AMDSMI_MASK_INCLUDE_INFO_SEVERITY(mask)
1257 
1258 #define AMDSMI_MASK_INCLUDE_CATEGORY(mask, cate) (mask | (1ULL << cate))
1259 #define AMDSMI_MASK_EXCLUDE_CATEGORY(mask, cate) (mask & (~(1ULL << cate)))
1260 
1261 #define AMDSMI_MAX_FB_SHARING_GROUPS 64
1262 #define AMDSMI_MAX_NUM_CONNECTED_NODES 64
1263 
1264 #define AMDSMI_MAX_NUM_METRICS_V1 255
1265 #define AMDSMI_MAX_NUM_METRICS_V2 512
1266 #define AMDSMI_MAX_NUM_METRICS AMDSMI_MAX_NUM_METRICS_V2
1267 
1268 #define AMDSMI_MAX_BAD_PAGE_RECORD_V1 512
1269 #define AMDSMI_MAX_BAD_PAGE_RECORD_V2 16384
1270 #define AMDSMI_MAX_BAD_PAGE_RECORD AMDSMI_MAX_BAD_PAGE_RECORD_V2
1271 
1277 #define AMDSMI_MAX_DATE_STRING_LENGTH 32
1278 
1284 typedef void *amdsmi_event_set;
1285 
1291 typedef enum {
1292  AMDSMI_EVENT_CATEGORY_NON_USED = 0,
1293  AMDSMI_EVENT_CATEGORY_DRIVER = 1,
1294  AMDSMI_EVENT_CATEGORY_RESET = 2,
1295  AMDSMI_EVENT_CATEGORY_SCHED = 3,
1296  AMDSMI_EVENT_CATEGORY_VBIOS = 4,
1297  AMDSMI_EVENT_CATEGORY_ECC = 5,
1298  AMDSMI_EVENT_CATEGORY_PP = 6,
1299  AMDSMI_EVENT_CATEGORY_IOV = 7,
1300  AMDSMI_EVENT_CATEGORY_VF = 8,
1301  AMDSMI_EVENT_CATEGORY_FW = 9,
1302  AMDSMI_EVENT_CATEGORY_GPU = 10,
1303  AMDSMI_EVENT_CATEGORY_GUARD = 11,
1304  AMDSMI_EVENT_CATEGORY_GPUMON = 12,
1305  AMDSMI_EVENT_CATEGORY_MMSCH = 13,
1306  AMDSMI_EVENT_CATEGORY_XGMI = 14,
1307  AMDSMI_EVENT_CATEGORY__MAX
1308 } amdsmi_event_category_t;
1309 
1315 typedef enum {
1316  AMDSMI_EVENT_GPU_DEVICE_LOST = 0,
1317  AMDSMI_EVENT_GPU_NOT_SUPPORTED,
1318  AMDSMI_EVENT_GPU_RMA,
1319  AMDSMI_EVENT_GPU_NOT_INITIALIZED,
1320  AMDSMI_EVENT_GPU_MMSCH_ABNORMAL_STATE,
1321  AMDSMI_EVENT_GPU_RLCV_ABNORMAL_STATE,
1322  AMDSMI_EVENT_GPU_SDMA_ENGINE_BUSY,
1323  AMDSMI_EVENT_GPU_RLC_ENGINE_BUSY,
1324  AMDSMI_EVENT_GPU_GC_ENGINE_BUSY,
1325  AMDSMI_EVENT_GPU__MAX
1326 } amdsmi_event_gpu_t;
1327 
1333 typedef enum {
1334  AMDSMI_EVENT_DRIVER_SPIN_LOCK_BUSY = 0,
1335  AMDSMI_EVENT_DRIVER_ALLOC_SYSTEM_MEM_FAIL,
1336  AMDSMI_EVENT_DRIVER_CREATE_GFX_WORKQUEUE_FAIL,
1337  AMDSMI_EVENT_DRIVER_CREATE_MM_WORKQUEUE_FAIL,
1338  AMDSMI_EVENT_DRIVER_BUFFER_OVERFLOW,
1339 
1340  AMDSMI_EVENT_DRIVER_DEV_INIT_FAIL,
1341  AMDSMI_EVENT_DRIVER_CREATE_THREAD_FAIL,
1342  AMDSMI_EVENT_DRIVER_NO_ACCESS_PCI_REGION,
1343  AMDSMI_EVENT_DRIVER_MMIO_FAIL,
1344  AMDSMI_EVENT_DRIVER_INTERRUPT_INIT_FAIL,
1345 
1346  AMDSMI_EVENT_DRIVER_INVALID_VALUE,
1347  AMDSMI_EVENT_DRIVER_CREATE_MUTEX_FAIL,
1348  AMDSMI_EVENT_DRIVER_CREATE_TIMER_FAIL,
1349  AMDSMI_EVENT_DRIVER_CREATE_EVENT_FAIL,
1350  AMDSMI_EVENT_DRIVER_CREATE_SPIN_LOCK_FAIL,
1351 
1352  AMDSMI_EVENT_DRIVER_ALLOC_FB_MEM_FAIL,
1353  AMDSMI_EVENT_DRIVER_ALLOC_DMA_MEM_FAIL,
1354  AMDSMI_EVENT_DRIVER_NO_FB_MANAGER,
1355  AMDSMI_EVENT_DRIVER_HW_INIT_FAIL,
1356  AMDSMI_EVENT_DRIVER_SW_INIT_FAIL,
1357 
1358  AMDSMI_EVENT_DRIVER_INIT_CONFIG_ERROR,
1359  AMDSMI_EVENT_DRIVER_ERROR_LOGGING_FAILED,
1360  AMDSMI_EVENT_DRIVER_CREATE_RWLOCK_FAIL,
1361  AMDSMI_EVENT_DRIVER_CREATE_RWSEMA_FAIL,
1362  AMDSMI_EVENT_DRIVER_GET_READ_LOCK_FAIL,
1363 
1364  AMDSMI_EVENT_DRIVER_GET_WRITE_LOCK_FAIL,
1365  AMDSMI_EVENT_DRIVER_GET_READ_SEMA_FAIL,
1366  AMDSMI_EVENT_DRIVER_GET_WRITE_SEMA_FAIL,
1367 
1368  AMDSMI_EVENT_DRIVER_DIAG_DATA_INIT_FAIL,
1369  AMDSMI_EVENT_DRIVER_DIAG_DATA_MEM_REQ_FAIL,
1370  AMDSMI_EVENT_DRIVER_DIAG_DATA_VADDR_REQ_FAIL,
1371  AMDSMI_EVENT_DRIVER_DIAG_DATA_BUS_ADDR_REQ_FAIL,
1372 
1373  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_INIT_FAIL,
1374  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_MEM_REQ_FAIL,
1375  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_VADDR_REQ_FAIL,
1376  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_BUS_ADDR_REQ_FAIL,
1377 
1378  AMDSMI_EVENT_DRIVER_HRTIMER_START_FAIL,
1379  AMDSMI_EVENT_DRIVER_CREATE_DRIVER_FILE_FAIL,
1380  AMDSMI_EVENT_DRIVER_CREATE_DEVICE_FILE_FAIL,
1381  AMDSMI_EVENT_DRIVER_CREATE_DEBUGFS_FILE_FAIL,
1382  AMDSMI_EVENT_DRIVER_CREATE_DEBUGFS_DIR_FAIL,
1383 
1384  AMDSMI_EVENT_DRIVER_PCI_ENABLE_DEVICE_FAIL,
1385  AMDSMI_EVENT_DRIVER_FB_MAP_FAIL,
1386  AMDSMI_EVENT_DRIVER_DOORBELL_MAP_FAIL,
1387  AMDSMI_EVENT_DRIVER_PCI_REGISTER_DRIVER_FAIL,
1388 
1389  AMDSMI_EVENT_DRIVER_ALLOC_IOVA_ALIGN_FAIL,
1390 
1391  AMDSMI_EVENT_DRIVER_ROM_MAP_FAIL,
1392  AMDSMI_EVENT_DRIVER_FULL_ACCESS_TIMEOUT,
1393 
1394  AMDSMI_EVENT_DRIVER__MAX
1395 } amdsmi_event_driver_t;
1396 
1402 typedef enum {
1403  AMDSMI_EVENT_FW_CMD_ALLOC_BUF_FAIL = 0,
1404  AMDSMI_EVENT_FW_CMD_BUF_PREP_FAIL,
1405  AMDSMI_EVENT_FW_RING_INIT_FAIL,
1406  AMDSMI_EVENT_FW_FW_APPLY_SECURITY_POLICY_FAIL,
1407  AMDSMI_EVENT_FW_START_RING_FAIL,
1408 
1409  AMDSMI_EVENT_FW_FW_LOAD_FAIL,
1410  AMDSMI_EVENT_FW_EXIT_FAIL,
1411  AMDSMI_EVENT_FW_INIT_FAIL,
1412  AMDSMI_EVENT_FW_CMD_SUBMIT_FAIL,
1413  AMDSMI_EVENT_FW_CMD_FENCE_WAIT_FAIL,
1414 
1415  AMDSMI_EVENT_FW_TMR_LOAD_FAIL,
1416  AMDSMI_EVENT_FW_TOC_LOAD_FAIL,
1417  AMDSMI_EVENT_FW_RAS_LOAD_FAIL,
1418  AMDSMI_EVENT_FW_RAS_UNLOAD_FAIL,
1419  AMDSMI_EVENT_FW_RAS_TA_INVOKE_FAIL,
1420  AMDSMI_EVENT_FW_RAS_TA_ERR_INJECT_FAIL,
1421 
1422  AMDSMI_EVENT_FW_ASD_LOAD_FAIL,
1423  AMDSMI_EVENT_FW_ASD_UNLOAD_FAIL,
1424  AMDSMI_EVENT_FW_AUTOLOAD_FAIL,
1425  AMDSMI_EVENT_FW_VFGATE_FAIL,
1426 
1427  AMDSMI_EVENT_FW_XGMI_LOAD_FAIL,
1428  AMDSMI_EVENT_FW_XGMI_UNLOAD_FAIL,
1429  AMDSMI_EVENT_FW_XGMI_TA_INVOKE_FAIL,
1430 
1431  AMDSMI_EVENT_FW_TMR_INIT_FAIL,
1432  AMDSMI_EVENT_FW_NOT_SUPPORTED_FEATURE,
1433  AMDSMI_EVENT_FW_GET_PSP_TRACELOG_FAIL,
1434 
1435  AMDSMI_EVENT_FW_SET_SNAPSHOT_ADDR_FAIL,
1436  AMDSMI_EVENT_FW_SNAPSHOT_TRIGGER_FAIL,
1437 
1438  AMDSMI_EVENT_FW_MIGRATION_GET_PSP_INFO_FAIL,
1439  AMDSMI_EVENT_FW_MIGRATION_EXPORT_FAIL,
1440  AMDSMI_EVENT_FW_MIGRATION_IMPORT_FAIL,
1441 
1442  AMDSMI_EVENT_FW_BL_FAIL,
1443  AMDSMI_EVENT_FW_RAS_BOOT_FAIL,
1444  AMDSMI_EVENT_FW_MAILBOX_ERROR,
1445 
1446  AMDSMI_EVENT_FW__MAX
1447 } amdsmi_event_fw_t;
1448 
1449 #define AMDSMI_EVENT_FW_FW_INIT_FAIL AMDSMI_EVENT_FW_RING_INIT_FAIL
1450 
1456 typedef enum {
1457  AMDSMI_EVENT_RESET_GPU = 0,
1458  AMDSMI_EVENT_RESET_GPU_FAILED,
1459  AMDSMI_EVENT_RESET_FLR,
1460  AMDSMI_EVENT_RESET_FLR_FAILED,
1461  AMDSMI_EVENT_RESET__MAX
1462 } amdsmi_event_reset_t;
1463 
1469 typedef enum {
1470  AMDSMI_EVENT_IOV_NO_GPU_IOV_CAP = 0,
1471  AMDSMI_EVENT_IOV_ASIC_NO_SRIOV_SUPPORT,
1472  AMDSMI_EVENT_IOV_ENABLE_SRIOV_FAIL,
1473  AMDSMI_EVENT_IOV_CMD_TIMEOUT,
1474  AMDSMI_EVENT_IOV_CMD_ERROR,
1475 
1476  AMDSMI_EVENT_IOV_INIT_IV_RING_FAIL,
1477  AMDSMI_EVENT_IOV_SRIOV_STRIDE_ERROR,
1478  AMDSMI_EVENT_IOV_WS_SAVE_TIMEOUT,
1479  AMDSMI_EVENT_IOV_WS_IDLE_TIMEOUT,
1480  AMDSMI_EVENT_IOV_WS_RUN_TIMEOUT,
1481  AMDSMI_EVENT_IOV_WS_LOAD_TIMEOUT,
1482  AMDSMI_EVENT_IOV_WS_SHUTDOWN_TIMEOUT,
1483  AMDSMI_EVENT_IOV_WS_ALREADY_SHUTDOWN,
1484  AMDSMI_EVENT_IOV_WS_INFINITE_LOOP,
1485  AMDSMI_EVENT_IOV_WS_REENTRANT_ERROR,
1486  AMDSMI_EVENT_IOV__MAX
1487 } amdsmi_event_iov_t;
1488 
1494 typedef enum {
1495  AMDSMI_EVENT_ECC_UCE = 0,
1496  AMDSMI_EVENT_ECC_CE,
1497  AMDSMI_EVENT_ECC_IN_PF_FB,
1498  AMDSMI_EVENT_ECC_IN_CRI_REG,
1499  AMDSMI_EVENT_ECC_IN_VF_CRI,
1500  AMDSMI_EVENT_ECC_REACH_THD,
1501  AMDSMI_EVENT_ECC_VF_CE,
1502  AMDSMI_EVENT_ECC_VF_UE,
1503  AMDSMI_EVENT_ECC_IN_SAME_ROW,
1504  AMDSMI_EVENT_ECC_UMC_UE,
1505  AMDSMI_EVENT_ECC_GFX_CE,
1506  AMDSMI_EVENT_ECC_GFX_UE,
1507  AMDSMI_EVENT_ECC_SDMA_CE,
1508  AMDSMI_EVENT_ECC_SDMA_UE,
1509  AMDSMI_EVENT_ECC_GFX_CE_TOTAL,
1510  AMDSMI_EVENT_ECC_GFX_UE_TOTAL,
1511  AMDSMI_EVENT_ECC_SDMA_CE_TOTAL,
1512  AMDSMI_EVENT_ECC_SDMA_UE_TOTAL,
1513  AMDSMI_EVENT_ECC_UMC_CE_TOTAL,
1514  AMDSMI_EVENT_ECC_UMC_UE_TOTAL,
1515  AMDSMI_EVENT_ECC_MMHUB_CE,
1516  AMDSMI_EVENT_ECC_MMHUB_UE,
1517  AMDSMI_EVENT_ECC_MMHUB_CE_TOTAL,
1518  AMDSMI_EVENT_ECC_MMHUB_UE_TOTAL,
1519  AMDSMI_EVENT_ECC_XGMI_WAFL_CE,
1520  AMDSMI_EVENT_ECC_XGMI_WAFL_UE,
1521  AMDSMI_EVENT_ECC_XGMI_WAFL_CE_TOTAL,
1522  AMDSMI_EVENT_ECC_XGMI_WAFL_UE_TOTAL,
1523  AMDSMI_EVENT_ECC_FATAL_ERROR,
1524  AMDSMI_EVENT_ECC_POISON_CONSUMPTION,
1525  AMDSMI_EVENT_ECC_ACA_DUMP,
1526  AMDSMI_EVENT_ECC_WRONG_SOCKET_ID,
1527  AMDSMI_EVENT_ECC_ACA_UNKNOWN_BLOCK_INSTANCE,
1528  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_CE,
1529  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_UE,
1530  AMDSMI_EVENT_ECC_UMC_CHIPLET_CE,
1531  AMDSMI_EVENT_ECC_UMC_CHIPLET_UE,
1532  AMDSMI_EVENT_ECC_GFX_CHIPLET_CE,
1533  AMDSMI_EVENT_ECC_GFX_CHIPLET_UE,
1534  AMDSMI_EVENT_ECC_SDMA_CHIPLET_CE,
1535  AMDSMI_EVENT_ECC_SDMA_CHIPLET_UE,
1536  AMDSMI_EVENT_ECC_MMHUB_CHIPLET_CE,
1537  AMDSMI_EVENT_ECC_MMHUB_CHIPLET_UE,
1538  AMDSMI_EVENT_ECC_XGMI_WAFL_CHIPLET_CE,
1539  AMDSMI_EVENT_ECC_XGMI_WAFL_CHIPLET_UE,
1540  AMDSMI_EVENT_ECC_EEPROM_ENTRIES_FOUND,
1541  AMDSMI_EVENT_ECC_UMC_DE,
1542  AMDSMI_EVENT_ECC_UMC_DE_TOTAL,
1543  AMDSMI_EVENT_ECC_UNKNOWN,
1544  AMDSMI_EVENT_ECC_EEPROM_REACH_THD,
1545  AMDSMI_EVENT_ECC_UMC_CHIPLET_DE,
1546  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_DE,
1547  AMDSMI_EVENT_ECC_EEPROM_CHK_MISMATCH,
1548  AMDSMI_EVENT_ECC_EEPROM_RESET,
1549  AMDSMI_EVENT_ECC_EEPROM_RESET_FAILED,
1550  AMDSMI_EVENT_ECC_EEPROM_APPEND,
1551  AMDSMI_EVENT_ECC_THD_CHANGED,
1552  AMDSMI_EVENT_ECC_DUP_ENTRIES,
1553  AMDSMI_EVENT_ECC_EEPROM_WRONG_HDR,
1554  AMDSMI_EVENT_ECC_EEPROM_WRONG_VER,
1555  AMDSMI_EVENT_ECC__MAX
1556 } amdsmi_event_ecc_t;
1557 
1563 typedef enum {
1564  AMDSMI_EVENT_PP_SET_DPM_POLICY_FAIL = 0,
1565  AMDSMI_EVENT_PP_ACTIVATE_DPM_POLICY_FAIL,
1566  AMDSMI_EVENT_PP_I2C_SLAVE_NOT_PRESENT,
1567  AMDSMI_EVENT_PP_THROTTLER_EVENT,
1568  AMDSMI_EVENT_PP__MAX
1569 } amdsmi_event_pp_t;
1570 
1576 typedef enum {
1577  AMDSMI_EVENT_SCHED_WORLD_SWITCH_FAIL = 0,
1578  AMDSMI_EVENT_SCHED_DISABLE_AUTO_HW_SWITCH_FAIL,
1579  AMDSMI_EVENT_SCHED_ENABLE_AUTO_HW_SWITCH_FAIL,
1580  AMDSMI_EVENT_SCHED_GFX_SAVE_REG_FAIL,
1581  AMDSMI_EVENT_SCHED_GFX_IDLE_REG_FAIL,
1582 
1583  AMDSMI_EVENT_SCHED_GFX_RUN_REG_FAIL,
1584  AMDSMI_EVENT_SCHED_GFX_LOAD_REG_FAIL,
1585  AMDSMI_EVENT_SCHED_GFX_INIT_REG_FAIL,
1586  AMDSMI_EVENT_SCHED_MM_SAVE_REG_FAIL,
1587  AMDSMI_EVENT_SCHED_MM_IDLE_REG_FAIL,
1588 
1589  AMDSMI_EVENT_SCHED_MM_RUN_REG_FAIL,
1590  AMDSMI_EVENT_SCHED_MM_LOAD_REG_FAIL,
1591  AMDSMI_EVENT_SCHED_MM_INIT_REG_FAIL,
1592  AMDSMI_EVENT_SCHED_INIT_GPU_FAIL,
1593  AMDSMI_EVENT_SCHED_RUN_GPU_FAIL,
1594 
1595  AMDSMI_EVENT_SCHED_SAVE_GPU_STATE_FAIL,
1596  AMDSMI_EVENT_SCHED_LOAD_GPU_STATE_FAIL,
1597  AMDSMI_EVENT_SCHED_IDLE_GPU_FAIL,
1598  AMDSMI_EVENT_SCHED_FINI_GPU_FAIL,
1599  AMDSMI_EVENT_SCHED_DEAD_VF,
1600 
1601  AMDSMI_EVENT_SCHED_EVENT_QUEUE_FULL,
1602  AMDSMI_EVENT_SCHED_SHUTDOWN_VF_FAIL,
1603  AMDSMI_EVENT_SCHED_RESET_VF_NUM_FAIL,
1604  AMDSMI_EVENT_SCHED_IGNORE_EVENT,
1605  AMDSMI_EVENT_SCHED_PF_SWITCH_FAIL,
1606  AMDSMI_EVENT_SCHED__MAX
1607 } amdsmi_event_sched_t;
1608 
1614 typedef enum {
1615  AMDSMI_EVENT_VF_ATOMBIOS_INIT_FAIL = 0,
1616  AMDSMI_EVENT_VF_NO_VBIOS,
1617  AMDSMI_EVENT_VF_GPU_POST_ERROR,
1618  AMDSMI_EVENT_VF_ATOMBIOS_GET_CLOCK_FAIL,
1619  AMDSMI_EVENT_VF_FENCE_INIT_FAIL,
1620  AMDSMI_EVENT_VF_AMDGPU_INIT_FAIL,
1621  AMDSMI_EVENT_VF_IB_INIT_FAIL,
1622  AMDSMI_EVENT_VF_AMDGPU_LATE_INIT_FAIL,
1623  AMDSMI_EVENT_VF_ASIC_RESUME_FAIL,
1624  AMDSMI_EVENT_VF_GPU_RESET_FAIL,
1625  AMDSMI_EVENT_VF__MAX
1626 } amdsmi_event_vf_max_t;
1627 
1633 typedef enum {
1634  AMDSMI_EVENT_VBIOS_INVALID = 0,
1635  AMDSMI_EVENT_VBIOS_IMAGE_MISSING,
1636  AMDSMI_EVENT_VBIOS_CHECKSUM_ERR,
1637  AMDSMI_EVENT_VBIOS_POST_FAIL,
1638  AMDSMI_EVENT_VBIOS_READ_FAIL,
1639 
1640  AMDSMI_EVENT_VBIOS_READ_IMG_HEADER_FAIL,
1641  AMDSMI_EVENT_VBIOS_READ_IMG_SIZE_FAIL,
1642  AMDSMI_EVENT_VBIOS_GET_FW_INFO_FAIL,
1643  AMDSMI_EVENT_VBIOS_GET_TBL_REVISION_FAIL,
1644  AMDSMI_EVENT_VBIOS_PARSER_TBL_FAIL,
1645 
1646  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_FAIL,
1647  AMDSMI_EVENT_VBIOS_TIMEOUT,
1648  AMDSMI_EVENT_VBIOS_HASH_INVALID,
1649  AMDSMI_EVENT_VBIOS_HASH_UPDATED,
1650  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_BINARY_CHECKSUM_FAIL,
1651  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_TABLE_CHECKSUM_FAIL,
1652  AMDSMI_EVENT_VBIOS__MAX
1653 } amdsmi_event_vbios_t;
1654 
1660 typedef enum {
1661  AMDSMI_EVENT_GUARD_RESET_FAIL = 0,
1662  AMDSMI_EVENT_GUARD_EVENT_OVERFLOW,
1663  AMDSMI_EVENT_GUARD__MAX
1664 } amdsmi_event_guard_t;
1665 
1671 typedef enum {
1672  AMDSMI_EVENT_GPUMON_INVALID_OPTION = 0,
1673  AMDSMI_EVENT_GPUMON_INVALID_VF_INDEX,
1674  AMDSMI_EVENT_GPUMON_INVALID_FB_SIZE,
1675  AMDSMI_EVENT_GPUMON_NO_SUITABLE_SPACE,
1676  AMDSMI_EVENT_GPUMON_NO_AVAILABLE_SLOT,
1677 
1678  AMDSMI_EVENT_GPUMON_OVERSIZE_ALLOCATION,
1679  AMDSMI_EVENT_GPUMON_OVERLAPPING_FB,
1680  AMDSMI_EVENT_GPUMON_INVALID_GFX_TIMESLICE,
1681  AMDSMI_EVENT_GPUMON_INVALID_MM_TIMESLICE,
1682  AMDSMI_EVENT_GPUMON_INVALID_GFX_PART,
1683 
1684  AMDSMI_EVENT_GPUMON_VF_BUSY,
1685  AMDSMI_EVENT_GPUMON_INVALID_VF_NUM,
1686  AMDSMI_EVENT_GPUMON_NOT_SUPPORTED,
1687  AMDSMI_EVENT_GPUMON__MAX
1688 } amdsmi_event_gpumon_t;
1689 
1695 typedef enum {
1696  AMDSMI_EVENT_MMSCH_IGNORED_JOB = 0,
1697  AMDSMI_EVENT_MMSCH_UNSUPPORTED_VCN_FW,
1698  AMDSMI_EVENT_MMSCH__MAX
1699 } amdsmi_event_mmsch_t;
1700 
1706 typedef enum {
1707  AMDSMI_EVENT_XGMI_TOPOLOGY_UPDATE_FAILED = 0,
1708  AMDSMI_EVENT_XGMI_TOPOLOGY_HW_INIT_UPDATE,
1709  AMDSMI_EVENT_XGMI_TOPOLOGY_UPDATE_DONE,
1710  AMDSMI_EVENT_XGMI_FB_SHARING_SETTING_ERROR,
1711  AMDSMI_EVENT_XGMI_FB_SHARING_SETTING_RESET,
1712  AMDSMI_EVENT_XGMI__MAX
1713 } amdsmi_event_xgmi_t;
1714 
1720 typedef enum {
1721  AMDSMI_EVENT_THROTTLER_PROCHOT = 0,
1722  AMDSMI_EVENT_THROTTLER_SOCKET,
1723  AMDSMI_EVENT_THROTTLER_VR,
1724  AMDSMI_EVENT_THROTTLER_HBM
1725 } amdsmi_pp_throttler_type_t;
1726 
1732 typedef enum {
1733  AMDSMI_RAS_ECC_SUPPORT_PARITY = (1 << 0),
1734  AMDSMI_RAS_ECC_SUPPORT_CORRECTABLE = (1 << 1),
1735  AMDSMI_RAS_ECC_SUPPORT_UNCORRECTABLE = (1 << 2),
1736  AMDSMI_RAS_ECC_SUPPORT_POISON = (1 << 3)
1737 } amdsmi_ecc_correction_schema_support_t;
1738 
1744 typedef enum {
1745  AMDSMI_GUEST_FW_ID_VCE = 0,
1746  AMDSMI_GUEST_FW_ID_UVD,
1747  AMDSMI_GUEST_FW_ID_MC,
1748  AMDSMI_GUEST_FW_ID_ME,
1749  AMDSMI_GUEST_FW_ID_PFP,
1750  AMDSMI_GUEST_FW_ID_CE,
1751  AMDSMI_GUEST_FW_ID_RLC,
1752  AMDSMI_GUEST_FW_ID_RLC_SRLC,
1753  AMDSMI_GUEST_FW_ID_RLC_SRLG,
1754  AMDSMI_GUEST_FW_ID_RLC_SRLS,
1755  AMDSMI_GUEST_FW_ID_MEC,
1756  AMDSMI_GUEST_FW_ID_MEC2,
1757  AMDSMI_GUEST_FW_ID_SOS,
1758  AMDSMI_GUEST_FW_ID_ASD,
1759  AMDSMI_GUEST_FW_ID_TA_RAS,
1760  AMDSMI_GUEST_FW_ID_TA_XGMI,
1761  AMDSMI_GUEST_FW_ID_SMC,
1762  AMDSMI_GUEST_FW_ID_SDMA,
1763  AMDSMI_GUEST_FW_ID_SDMA2,
1764  AMDSMI_GUEST_FW_ID_VCN,
1765  AMDSMI_GUEST_FW_ID_DMCU,
1766  AMDSMI_GUEST_FW_ID__MAX
1767 } amdsmi_guest_fw_engine_id_t;
1768 
1774 typedef enum {
1775  AMDSMI_VF_CONFIG_FB_SIZE_SET = 0,
1776  AMDSMI_VF_CONFIG_FB_OFFSET_SET,
1777  AMDSMI_VF_CONFIG_GFX_TIMESLICE_US_SET,
1778  AMDSMI_VF_CONFIG_ENG_COMPUTE_BW_SET,
1779  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_FLR_SET,
1780  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_EXCL_MOD_SET,
1781  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_EXCL_TIMEOUT_SET,
1782  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_ALL_INT_SET,
1783  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_UVD_SET,
1784  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCE_SET,
1785  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_UVD1_SET,
1786  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCN_SET,
1787  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCN1_SET,
1788  AMDSMI_VF_CONFIG__MAX
1789 } amdsmi_vf_config_flags_t;
1790 
1796 typedef enum {
1797  AMDSMI_VF_STATE_UNAVAILABLE,
1798  AMDSMI_VF_STATE_AVAILABLE,
1799  AMDSMI_VF_STATE_ACTIVE,
1800  AMDSMI_VF_STATE_SUSPENDED,
1801  AMDSMI_VF_STATE_FULLACCESS,
1802  AMDSMI_VF_STATE_DEFAULT_AVAILABLE,
1803 } amdsmi_vf_sched_state_t;
1804 
1810 typedef enum {
1811  AMDSMI_GUARD_EVENT_FLR,
1812  AMDSMI_GUARD_EVENT_EXCLUSIVE_MOD,
1813  AMDSMI_GUARD_EVENT_EXCLUSIVE_TIMEOUT,
1814  AMDSMI_GUARD_EVENT_ALL_INT,
1815  AMDSMI_GUARD_EVENT_RAS_ERR_COUNT,
1816  AMDSMI_GUARD_EVENT_RAS_CPER_DUMP,
1817  AMDSMI_GUARD_EVENT_RAS_BAD_PAGES,
1818  AMDSMI_GUARD_EVENT__MAX
1819 } amdsmi_guard_type_t;
1820 
1826 typedef enum {
1827  AMDSMI_DRIVER_LIBGV,
1828  AMDSMI_DRIVER_KMD,
1829  AMDSMI_DRIVER_AMDGPUV,
1830  AMDSMI_DRIVER_AMDGPU,
1831  AMDSMI_DRIVER_VMWGPUV,
1832  AMDSMI_DRIVER__MAX,
1833 } amdsmi_driver_t;
1834 
1840 typedef enum {
1841  AMDSMI_GUARD_STATE_NORMAL = 0,
1842  AMDSMI_GUARD_STATE_FULL = 1,
1843  AMDSMI_GUARD_STATE_OVERFLOW = 2,
1844 } amdsmi_guard_state_t;
1845 
1851 typedef enum {
1852  AMDSMI_SCHED_BLOCK_GFX = 0x0,
1853  AMDSMI_SCHED_BLOCK_UVD = 0x1,
1854  AMDSMI_SCHED_BLOCK_VCE = 0x2,
1855  AMDSMI_SCHED_BLOCK_UVD1 = 0x3,
1856  AMDSMI_SCHED_BLOCK_VCN = 0x4,
1857  AMDSMI_SCHED_BLOCK_VCN1 = 0x5,
1858 } amdsmi_sched_block_t;
1859 
1865 typedef enum {
1866  AMDSMI_GUEST_FW_LOAD_STATUS_OK = 0,
1867  AMDSMI_GUEST_FW_LOAD_STATUS_OBSOLETE_FW = 1,
1868  AMDSMI_GUEST_FW_LOAD_STATUS_BAD_SIG = 2,
1869  AMDSMI_GUEST_FW_LOAD_STATUS_FW_LOAD_FAIL = 3,
1870  AMDSMI_GUEST_FW_LOAD_STATUS_ERR_GENERIC = 4
1871 } amdsmi_guest_fw_load_status_t;
1872 
1878 typedef enum {
1879  AMDSMI_XGMI_FB_SHARING_MODE_CUSTOM = 0,
1880  AMDSMI_XGMI_FB_SHARING_MODE_1 = 1,
1881  AMDSMI_XGMI_FB_SHARING_MODE_2 = 2,
1882  AMDSMI_XGMI_FB_SHARING_MODE_4 = 4,
1883  AMDSMI_XGMI_FB_SHARING_MODE_8 = 8,
1884  AMDSMI_XGMI_FB_SHARING_MODE_UNKNOWN = 0xFFFFFFFF
1885 } amdsmi_xgmi_fb_sharing_mode_t;
1886 
1892 typedef enum {
1893  AMDSMI_PROFILE_CAPABILITY_MEMORY = 0,
1894  AMDSMI_PROFILE_CAPABILITY_ENCODE = 1,
1895  AMDSMI_PROFILE_CAPABILITY_DECODE = 2,
1896  AMDSMI_PROFILE_CAPABILITY_COMPUTE = 3,
1897  AMDSMI_PROFILE_CAPABILITY__MAX,
1898 } amdsmi_profile_capability_type_t;
1899 
1905 typedef enum {
1906  AMDSMI_METRIC_CATEGORY_ACC_COUNTER,
1907  AMDSMI_METRIC_CATEGORY_FREQUENCY,
1908  AMDSMI_METRIC_CATEGORY_ACTIVITY,
1909  AMDSMI_METRIC_CATEGORY_TEMPERATURE,
1910  AMDSMI_METRIC_CATEGORY_POWER,
1911  AMDSMI_METRIC_CATEGORY_ENERGY,
1912  AMDSMI_METRIC_CATEGORY_THROTTLE,
1913  AMDSMI_METRIC_CATEGORY_PCIE,
1914  AMDSMI_METRIC_CATEGORY_STATIC,
1915  AMDSMI_METRIC_CATEGORY_SYS_ACC_COUNTER,
1916  AMDSMI_METRIC_CATEGORY_SYS_BASEBOARD_TEMP,
1917  AMDSMI_METRIC_CATEGORY_SYS_GPUBOARD_TEMP,
1918  AMDSMI_METRIC_CATEGORY_SYS_BASEBOARD_POWER,
1919  AMDSMI_METRIC_CATEGORY_UNKNOWN
1920 } amdsmi_metric_category_t;
1921 
1927 typedef enum {
1928  AMDSMI_METRIC_NAME_METRIC_ACC_COUNTER,
1929  AMDSMI_METRIC_NAME_FW_TIMESTAMP,
1930  AMDSMI_METRIC_NAME_CLK_GFX,
1931  AMDSMI_METRIC_NAME_CLK_SOC,
1932  AMDSMI_METRIC_NAME_CLK_MEM,
1933  AMDSMI_METRIC_NAME_CLK_VCLK,
1934  AMDSMI_METRIC_NAME_CLK_DCLK,
1935 
1936  AMDSMI_METRIC_NAME_USAGE_GFX,
1937  AMDSMI_METRIC_NAME_USAGE_MEM,
1938  AMDSMI_METRIC_NAME_USAGE_MM,
1939  AMDSMI_METRIC_NAME_USAGE_VCN,
1940  AMDSMI_METRIC_NAME_USAGE_JPEG,
1941 
1942  AMDSMI_METRIC_NAME_VOLT_GFX,
1943  AMDSMI_METRIC_NAME_VOLT_SOC,
1944  AMDSMI_METRIC_NAME_VOLT_MEM,
1945 
1946  AMDSMI_METRIC_NAME_TEMP_HOTSPOT_CURR,
1947  AMDSMI_METRIC_NAME_TEMP_HOTSPOT_LIMIT,
1948  AMDSMI_METRIC_NAME_TEMP_MEM_CURR,
1949  AMDSMI_METRIC_NAME_TEMP_MEM_LIMIT,
1950  AMDSMI_METRIC_NAME_TEMP_VR_CURR,
1951  AMDSMI_METRIC_NAME_TEMP_SHUTDOWN,
1952 
1953  AMDSMI_METRIC_NAME_POWER_CURR,
1954  AMDSMI_METRIC_NAME_POWER_LIMIT,
1955 
1956  AMDSMI_METRIC_NAME_ENERGY_SOCKET,
1957  AMDSMI_METRIC_NAME_ENERGY_CCD,
1958  AMDSMI_METRIC_NAME_ENERGY_XCD,
1959  AMDSMI_METRIC_NAME_ENERGY_AID,
1960  AMDSMI_METRIC_NAME_ENERGY_MEM,
1961 
1962  AMDSMI_METRIC_NAME_THROTTLE_SOCKET_ACTIVE,
1963  AMDSMI_METRIC_NAME_THROTTLE_VR_ACTIVE,
1964  AMDSMI_METRIC_NAME_THROTTLE_MEM_ACTIVE,
1965  AMDSMI_METRIC_NAME_THROTTLE_PROCHOT_ACTIVE,
1966  AMDSMI_METRIC_NAME_THROTTLE_PPT_ACTIVE,
1967 
1968  AMDSMI_METRIC_NAME_PCIE_BANDWIDTH,
1969  AMDSMI_METRIC_NAME_PCIE_L0_TO_RECOVERY_COUNT,
1970  AMDSMI_METRIC_NAME_PCIE_REPLAY_COUNT,
1971  AMDSMI_METRIC_NAME_PCIE_REPLAY_ROLLOVER_COUNT,
1972  AMDSMI_METRIC_NAME_PCIE_NAK_SENT_COUNT,
1973  AMDSMI_METRIC_NAME_PCIE_NAK_RECEIVED_COUNT,
1974 
1975  AMDSMI_METRIC_NAME_CLK_GFX_MAX_LIMIT,
1976  AMDSMI_METRIC_NAME_CLK_SOC_MAX_LIMIT,
1977  AMDSMI_METRIC_NAME_CLK_MEM_MAX_LIMIT,
1978  AMDSMI_METRIC_NAME_CLK_VCLK_MAX_LIMIT,
1979  AMDSMI_METRIC_NAME_CLK_DCLK_MAX_LIMIT,
1980 
1981  AMDSMI_METRIC_NAME_CLK_GFX_MIN_LIMIT,
1982  AMDSMI_METRIC_NAME_CLK_SOC_MIN_LIMIT,
1983  AMDSMI_METRIC_NAME_CLK_MEM_MIN_LIMIT,
1984  AMDSMI_METRIC_NAME_CLK_VCLK_MIN_LIMIT,
1985  AMDSMI_METRIC_NAME_CLK_DCLK_MIN_LIMIT,
1986 
1987  AMDSMI_METRIC_NAME_CLK_GFX_LOCKED,
1988 
1989  AMDSMI_METRIC_NAME_CLK_GFX_DS_DISABLED,
1990  AMDSMI_METRIC_NAME_CLK_MEM_DS_DISABLED,
1991  AMDSMI_METRIC_NAME_CLK_SOC_DS_DISABLED,
1992  AMDSMI_METRIC_NAME_CLK_VCLK_DS_DISABLED,
1993  AMDSMI_METRIC_NAME_CLK_DCLK_DS_DISABLED,
1994 
1995  AMDSMI_METRIC_NAME_PCIE_LINK_SPEED,
1996  AMDSMI_METRIC_NAME_PCIE_LINK_WIDTH,
1997 
1998  AMDSMI_METRIC_NAME_DRAM_BANDWIDTH,
1999  AMDSMI_METRIC_NAME_MAX_DRAM_BANDWIDTH,
2000 
2001  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_PPT,
2002  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_THM,
2003  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_TOTAL,
2004  AMDSMI_METRIC_NAME_GFX_CLK_LOW_UTILIZATION,
2005  AMDSMI_METRIC_NAME_INPUT_TELEMETRY_VOLTAGE,
2006  AMDSMI_METRIC_NAME_PLDM_VERSION,
2007  AMDSMI_METRIC_NAME_TEMP_XCD,
2008  AMDSMI_METRIC_NAME_TEMP_AID,
2009  AMDSMI_METRIC_NAME_TEMP_HBM,
2010 
2011  AMDSMI_METRIC_NAME_SYS_METRIC_ACC_COUNTER,
2012  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA,
2013  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FRONT,
2014  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_BACK,
2015  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_OAM7,
2016  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_IBC,
2017  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_UFPGA,
2018  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_OAM1,
2019  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_0_1_HSC,
2020  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_2_3_HSC,
2021  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_4_5_HSC,
2022  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_6_7_HSC,
2023  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA_0V72_VR,
2024  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA_3V3_VR,
2025  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR,
2026  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR,
2027  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_0_1_0V9_VR,
2028  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_4_5_0V9_VR,
2029  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_2_3_0V9_VR,
2030  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_6_7_0V9_VR,
2031  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR,
2032  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR,
2033  AMDSMI_METRIC_NAME_SYSTEM_TEMP_IBC_HSC,
2034  AMDSMI_METRIC_NAME_SYSTEM_TEMP_IBC,
2035  AMDSMI_METRIC_NAME_NODE_TEMP_RETIMER,
2036  AMDSMI_METRIC_NAME_NODE_TEMP_IBC_TEMP,
2037  AMDSMI_METRIC_NAME_NODE_TEMP_IBC_2_TEMP,
2038  AMDSMI_METRIC_NAME_NODE_TEMP_VDD18_VR_TEMP,
2039  AMDSMI_METRIC_NAME_NODE_TEMP_04_HBM_B_VR_TEMP,
2040  AMDSMI_METRIC_NAME_NODE_TEMP_04_HBM_D_VR_TEMP,
2041  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD0,
2042  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD1,
2043  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD2,
2044  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD3,
2045  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOC_A,
2046  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOC_C,
2047  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOCIO_A,
2048  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOCIO_C,
2049  AMDSMI_METRIC_NAME_VR_TEMP_VDD_085_HBM,
2050  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_11_HBM_B,
2051  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_11_HBM_D,
2052  AMDSMI_METRIC_NAME_VR_TEMP_VDD_USR,
2053  AMDSMI_METRIC_NAME_VR_TEMP_VDDIO_11_E32,
2054  AMDSMI_METRIC_NAME_SYSTEM_POWER_UBB_POWER,
2055  AMDSMI_METRIC_NAME_SYSTEM_POWER_UBB_POWER_THRESHOLD,
2056 
2057  AMDSMI_METRIC_NAME_UNKNOWN
2058 } amdsmi_metric_name_t;
2059 
2065 typedef enum {
2066  AMDSMI_METRIC_UNIT_COUNTER,
2067  AMDSMI_METRIC_UNIT_UINT,
2068  AMDSMI_METRIC_UNIT_BOOL,
2069  AMDSMI_METRIC_UNIT_MHZ,
2070  AMDSMI_METRIC_UNIT_PERCENT,
2071  AMDSMI_METRIC_UNIT_MILLIVOLT,
2072  AMDSMI_METRIC_UNIT_CELSIUS,
2073  AMDSMI_METRIC_UNIT_WATT,
2074  AMDSMI_METRIC_UNIT_JOULE,
2075  AMDSMI_METRIC_UNIT_GBPS,
2076  AMDSMI_METRIC_UNIT_MBITPS,
2077  AMDSMI_METRIC_UNIT_PCIE_GEN,
2078  AMDSMI_METRIC_UNIT_PCIE_LANES,
2079  AMDSMI_METRIC_UNIT_15_625_MILLIJOULE,
2080  AMDSMI_METRIC_UNIT_UNKNOWN
2081 } amdsmi_metric_unit_t;
2082 
2088 typedef enum {
2089  AMDSMI_METRIC_TYPE_COUNTER = (1 << 0),
2090  AMDSMI_METRIC_TYPE_CHIPLET = (1 << 1),
2091  AMDSMI_METRIC_TYPE_INST = (1 << 2),
2092  AMDSMI_METRIC_TYPE_ACC = (1 << 3)
2093 } amdsmi_metric_type_t;
2094 
2095 typedef enum {
2096  AMDSMI_METRIC_RES_GROUP_UNKNOWN,
2097  AMDSMI_METRIC_RES_GROUP_NA,
2098  AMDSMI_METRIC_RES_GROUP_GPU,
2099  AMDSMI_METRIC_RES_GROUP_XCP,
2100  AMDSMI_METRIC_RES_GROUP_AID,
2101  AMDSMI_METRIC_RES_GROUP_MID,
2102  AMDSMI_METRIC_RES_GROUP_SYSTEM
2103 } amdsmi_metric_res_group_t;
2104 
2105 typedef enum {
2106  AMDSMI_METRIC_RES_SUBGROUP_UNKNOWN,
2107  AMDSMI_METRIC_RES_SUBGROUP_NA,
2108  AMDSMI_METRIC_RES_SUBGROUP_XCC,
2109  AMDSMI_METRIC_RES_SUBGROUP_ENGINE,
2110  AMDSMI_METRIC_RES_SUBGROUP_HBM,
2111  AMDSMI_METRIC_RES_SUBGROUP_BASEBOARD,
2112  AMDSMI_METRIC_RES_SUBGROUP_GPUBOARD
2113 } amdsmi_metric_res_subgroup_t;
2114 
2115 typedef enum {
2116  AMDSMI_VF_MODE_1 = (1U << 1),
2117  AMDSMI_VF_MODE_2 = (1U << 2),
2118  AMDSMI_VF_MODE_4 = (1U << 4),
2119  AMDSMI_VF_MODE_8 = (1U << 8),
2120  AMDSMI_VF_MODE_ALL = (AMDSMI_VF_MODE_1 | AMDSMI_VF_MODE_2 | AMDSMI_VF_MODE_4 | AMDSMI_VF_MODE_8)
2121 } amdsmi_vf_mode_t;
2122 
2128 typedef enum {
2129  AMDSMI_DRIVER_MODEL_TYPE_WDDM = 0,
2130  AMDSMI_DRIVER_MODEL_TYPE_WDM = 1,
2131  AMDSMI_DRIVER_MODEL_TYPE_MCDM = 2,
2132  AMDSMI_DRIVER_MODEL_TYPE__MAX = 3,
2133 } amdsmi_driver_model_type_t;
2134 
2140 typedef struct {
2141  uint64_t handle;
2142 } amdsmi_vf_handle_t;
2143 
2149 typedef struct {
2150  amdsmi_vf_handle_t fcn_id;
2151  uint64_t dev_id;
2152  uint64_t timestamp;
2153  uint64_t data;
2154  uint32_t category;
2155  uint32_t subcode;
2156  uint32_t level;
2157  char date[AMDSMI_MAX_DATE_STRING_LENGTH];
2158  char message[AMDSMI_MAX_STRING_LENGTH];
2159  amdsmi_processor_handle processor_handle;
2160  uint64_t reserved[37];
2161 } amdsmi_event_entry_t;
2162 
2168 typedef struct {
2169  uint32_t version;
2170 } amdsmi_handshake_t;
2171 
2177 typedef struct {
2178  uint32_t total_fb_size;
2179  uint32_t pf_fb_reserved;
2180  uint32_t pf_fb_offset;
2181  uint32_t fb_alignment;
2182  uint32_t max_vf_fb_usable;
2183  uint32_t min_vf_fb_usable;
2184  uint64_t reserved[5];
2185 } amdsmi_pf_fb_info_t;
2186 
2192 typedef struct {
2193  uint32_t fb_offset;
2194  uint32_t fb_size;
2195  uint64_t reserved[3];
2196 } amdsmi_vf_fb_info_t;
2197 
2203 typedef struct {
2204  amdsmi_vf_handle_t id;
2205  amdsmi_vf_fb_info_t fb;
2206  uint64_t reserved[3];
2207 } amdsmi_partition_info_t;
2208 
2214 typedef struct {
2215  uint8_t enabled;
2216  struct {
2217  amdsmi_guard_state_t state;
2218  /* amount of monitor event after enabled */
2219  uint32_t amount;
2220  /* threshold of events in the interval(seconds) */
2221  uint64_t interval;
2222  uint32_t threshold;
2223  /* current number of events in the interval*/
2224  uint32_t active;
2225  uint32_t reserved[4];
2226  } guard[AMDSMI_GUARD_EVENT__MAX];
2227  uint32_t reserved[6];
2228 } amdsmi_guard_info_t;
2229 
2235 typedef struct {
2236  amdsmi_vf_fb_info_t fb;
2237  uint32_t gfx_timeslice;
2238  uint64_t reserved[27];
2239 } amdsmi_vf_info_t;
2240 
2246 typedef struct {
2247  uint64_t flr_count;
2248  uint64_t boot_up_time;
2249  uint64_t shutdown_time;
2250  uint64_t reset_time;
2251  amdsmi_vf_sched_state_t state;
2252  char last_boot_start[AMDSMI_MAX_STRING_LENGTH];
2253  char last_boot_end[AMDSMI_MAX_STRING_LENGTH];
2254  char last_shutdown_start[AMDSMI_MAX_STRING_LENGTH];
2255  char last_shutdown_end[AMDSMI_MAX_STRING_LENGTH];
2256  char last_reset_start[AMDSMI_MAX_STRING_LENGTH];
2257  char last_reset_end[AMDSMI_MAX_STRING_LENGTH];
2258  char current_active_time[AMDSMI_MAX_STRING_LENGTH];
2259  char current_running_time[AMDSMI_MAX_STRING_LENGTH];
2260  char total_active_time[AMDSMI_MAX_STRING_LENGTH];
2261  char total_running_time[AMDSMI_MAX_STRING_LENGTH];
2262  uint64_t reserved[11];
2263 } amdsmi_sched_info_t;
2264 
2270 typedef struct {
2271  amdsmi_sched_info_t sched;
2272  amdsmi_guard_info_t guard;
2273  uint64_t reserved[8];
2274 } amdsmi_vf_data_t;
2275 
2281 typedef struct {
2282  uint64_t total;
2283  uint64_t available;
2284  uint64_t optimal;
2285  uint64_t min_value;
2286  uint64_t max_value;
2287  uint64_t reserved[2];
2288 } amdsmi_profile_caps_info_t;
2289 
2295 typedef struct {
2296  uint8_t profile_count;
2297  uint8_t current_profile_index;
2298  struct {
2299  uint32_t vf_count;
2300  amdsmi_profile_caps_info_t profile_caps[AMDSMI_PROFILE_CAPABILITY__MAX];
2301  } profiles[AMDSMI_MAX_PROFILE_COUNT];
2302  uint32_t reserved[6];
2303 } amdsmi_profile_info_t;
2304 
2310 typedef struct {
2311  char driver_version[AMDSMI_MAX_STRING_LENGTH];
2312  uint32_t fb_usage;
2313  uint64_t reserved[23];
2314 } amdsmi_guest_data_t;
2315 
2321 typedef struct {
2322  uint32_t dfc_fw_version;
2323  uint32_t dfc_fw_total_entries;
2324  uint32_t dfc_gart_wr_guest_min;
2325  uint32_t dfc_gart_wr_guest_max;
2326  uint32_t reserved[12];
2327 } amdsmi_dfc_fw_header_t;
2328 
2334 typedef struct {
2335  uint32_t oldest;
2336  uint32_t latest;
2337 } amdsmi_dfc_fw_white_list_t;
2338 
2344 typedef struct {
2345  uint8_t ta_uuid[AMDSMI_MAX_UUID_ELEMENTS];
2346 } amdsmi_dfc_fw_ta_uuid_t;
2347 
2353 typedef struct {
2354  uint32_t dfc_fw_type;
2355  uint32_t verification_enabled;
2356  uint32_t customer_ordinal;
2357  uint32_t reserved[13];
2358  union {
2359  amdsmi_dfc_fw_white_list_t white_list[AMDSMI_MAX_WHITE_LIST_ELEMENTS];
2360  amdsmi_dfc_fw_ta_uuid_t ta_white_list[AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS];
2361  };
2362  uint32_t black_list[AMDSMI_MAX_BLACK_LIST_ELEMENTS];
2363 } amdsmi_dfc_fw_data_t;
2364 
2370 typedef struct {
2371  amdsmi_dfc_fw_header_t header;
2372  amdsmi_dfc_fw_data_t data[AMDSMI_DFC_FW_NUMBER_OF_ENTRIES];
2373 } amdsmi_dfc_fw_t;
2374 
2384 typedef struct {
2385  uint64_t retired_page;
2386  uint64_t ts;
2387  unsigned char err_type;
2388  union {
2389  unsigned char bank;
2390  unsigned char cu;
2391  };
2392  unsigned char mem_channel;
2393  unsigned char mcumc_id;
2394  uint32_t reserved[3];
2395 } amdsmi_eeprom_table_record_t;
2396 
2402 typedef struct {
2403  uint64_t timestamp;
2404  uint32_t vf_idx;
2405  uint32_t fw_id;
2406  uint16_t status;
2407  uint32_t reserved[3];
2408 } amdsmi_fw_load_error_record_t;
2409 
2415 typedef struct {
2416  uint8_t num_err_records;
2417  amdsmi_fw_load_error_record_t err_records[AMDSMI_MAX_ERR_RECORDS];
2418  uint64_t reserved[7];
2419 } amdsmi_fw_error_record_t;
2420 
2426 typedef struct {
2427  uint64_t weight;
2428  amdsmi_link_status_t link_status;
2429  amdsmi_link_type_t link_type;
2430  uint8_t num_hops;
2431  uint8_t fb_sharing;
2432  uint32_t reserved[10];
2433 } amdsmi_link_topology_t;
2434 
2440 typedef struct {
2441  uint32_t count;
2442  amdsmi_processor_handle processor_list[AMDSMI_MAX_DEVICES];
2443  uint64_t reserved[15];
2444 } amdsmi_topology_nearest_t;
2445 
2451 typedef union {
2452  struct cap_ {
2453  uint32_t mode_custom_cap :1;
2454  uint32_t mode_1_cap :1;
2455  uint32_t mode_2_cap :1;
2456  uint32_t mode_4_cap :1;
2457  uint32_t mode_8_cap :1;
2458  uint32_t reserved :27;
2459  } cap;
2460  uint32_t xgmi_fb_sharing_cap_mask;
2461 } amdsmi_xgmi_fb_sharing_caps_t;
2462 
2468 typedef struct {
2469  amdsmi_metric_unit_t unit;
2470  amdsmi_metric_name_t name;
2471  amdsmi_metric_category_t category;
2472  uint32_t flags;
2473  uint32_t vf_mask;
2474  uint64_t val;
2475  amdsmi_metric_res_group_t res_group;
2476  amdsmi_metric_res_subgroup_t res_subgroup;
2477  uint32_t res_instance;
2478  uint32_t reserved[5];
2479 } amdsmi_metric_t;
2480 
2486 typedef struct {
2487  uint32_t major;
2488  uint32_t minor;
2489  uint32_t release;
2490 } amdsmi_version_t;
2491 
2492 typedef struct {
2493  amdsmi_accelerator_partition_profile_t profile;
2494  uint32_t vf_mode;
2495  uint64_t reserved[6];
2496 } amdsmi_accelerator_partition_profile_global_t;
2497 
2498 typedef struct {
2499  uint32_t num_profiles;
2500  uint32_t num_resource_profiles;
2501  amdsmi_accelerator_partition_resource_profile_t resource_profiles[AMDSMI_MAX_CP_PROFILE_RESOURCES];
2502  uint32_t default_profile_index;
2503  amdsmi_accelerator_partition_profile_global_t profiles[AMDSMI_MAX_ACCELERATOR_PROFILE];
2504  uint64_t reserved[30];
2505 } amdsmi_accelerator_partition_profile_config_global_t;
2506 
2512 #define AMDSMI_MAX_NIC_PORTS 32
2513 #define AMDSMI_MAX_NIC_RDMA_DEV 32
2514 #define AMDSMI_MAX_NIC_FW 16
2515 
2522 typedef enum {
2523  AMDSMI_NIC_LINK_TYPE_UNKNOWN,
2524  AMDSMI_NIC_LINK_TYPE_PCIE,
2525  AMDSMI_NIC_LINK_TYPE_NUMA,
2526  AMDSMI_NIC_LINK_TYPE_X_NUMA,
2527  } amdsmi_nic_link_type_t;
2528 
2536 typedef struct {
2537  char name[AMDSMI_MAX_STRING_LENGTH];
2538  uint64_t value;
2539 } amdsmi_nic_stat_t;
2540 
2546 typedef struct {
2547  uint16_t vendor_id;
2548  uint16_t subvendor_id;
2549  uint16_t device_id;
2550  uint16_t subsystem_id;
2551  uint8_t revision;
2552  char permanent_address[AMDSMI_MAX_STRING_LENGTH];
2553  char product_name[AMDSMI_MAX_STRING_LENGTH];
2554  char part_number[AMDSMI_MAX_STRING_LENGTH];
2555  char serial_number[AMDSMI_MAX_STRING_LENGTH];
2556  char vendor_name[AMDSMI_MAX_STRING_LENGTH];
2557 } amdsmi_nic_asic_info_t;
2558 
2564 typedef struct {
2565  amdsmi_bdf_t bdf;
2566  uint8_t max_pcie_width;
2567  uint32_t max_pcie_speed;
2568  char pcie_interface_version[AMDSMI_MAX_STRING_LENGTH];
2569  char slot_type[AMDSMI_MAX_STRING_LENGTH];
2570 } amdsmi_nic_bus_info_t;
2571 
2577 typedef struct {
2578  uint8_t node;
2579  char affinity[AMDSMI_MAX_STRING_LENGTH];
2580 } amdsmi_nic_numa_info_t;
2581 
2587 typedef struct {
2588  char name[AMDSMI_MAX_STRING_LENGTH];
2589  char version[AMDSMI_MAX_STRING_LENGTH];
2590 } amdsmi_nic_fw_t;
2591 
2597 typedef struct {
2598  uint32_t num_fw;
2599  amdsmi_nic_fw_t fw[AMDSMI_MAX_NIC_FW];
2600 } amdsmi_nic_fw_info_t;
2601 
2624 typedef struct {
2625  amdsmi_bdf_t bdf;
2626  uint32_t port_num;
2627  char type[AMDSMI_MAX_STRING_LENGTH];
2628  char flavour[AMDSMI_MAX_STRING_LENGTH];
2629  char netdev[AMDSMI_MAX_STRING_LENGTH];
2630  uint8_t ifindex;
2631  char mac_address[AMDSMI_MAX_STRING_LENGTH];
2632  uint8_t carrier;
2633  uint16_t mtu;
2634  char link_state[AMDSMI_MAX_STRING_LENGTH];
2635  uint32_t link_speed;
2636  uint32_t active_fec;
2637  char autoneg[AMDSMI_MAX_STRING_LENGTH];
2638  char pause_autoneg[AMDSMI_MAX_STRING_LENGTH];
2639  char pause_rx[AMDSMI_MAX_STRING_LENGTH];
2640  char pause_tx[AMDSMI_MAX_STRING_LENGTH];
2641 } amdsmi_nic_port_t;
2642 
2648 typedef struct {
2649  uint32_t num_ports;
2650  amdsmi_nic_port_t ports[AMDSMI_MAX_NIC_PORTS];
2651 } amdsmi_nic_port_info_t;
2652 
2658 typedef struct {
2659  char name[AMDSMI_MAX_STRING_LENGTH];
2660  char version[AMDSMI_MAX_STRING_LENGTH];
2661 } amdsmi_nic_driver_info_t;
2662 
2668 typedef struct {
2669  char netdev[AMDSMI_MAX_STRING_LENGTH];
2670  char state[AMDSMI_MAX_STRING_LENGTH];
2671  uint8_t rdma_port;
2672  uint16_t max_mtu;
2673  uint16_t active_mtu;
2674 } amdsmi_nic_rdma_port_info_t;
2675 
2681 typedef struct {
2682  char rdma_dev[AMDSMI_MAX_STRING_LENGTH];
2683  char node_guid[AMDSMI_MAX_STRING_LENGTH];
2684  char node_type[AMDSMI_MAX_STRING_LENGTH];
2685  char sys_image_guid[AMDSMI_MAX_STRING_LENGTH];
2686  char fw_ver[AMDSMI_MAX_STRING_LENGTH];
2687  uint8_t num_rdma_ports;
2688  amdsmi_nic_rdma_port_info_t rdma_port_info[AMDSMI_MAX_NIC_PORTS];
2689 } amdsmi_nic_rdma_dev_info_t;
2690 
2696 typedef struct {
2697  uint8_t num_rdma_dev;
2698  amdsmi_nic_rdma_dev_info_t rdma_dev_info[AMDSMI_MAX_NIC_RDMA_DEV];
2699 } amdsmi_nic_rdma_devices_info_t;
2700 
2701 /*****************************************************************************/
2730 amdsmi_status_t amdsmi_init(uint64_t init_flags);
2731 
2746 amdsmi_status_t amdsmi_shut_down(void);
2747 
2750 /*****************************************************************************/
2783 amdsmi_status_t amdsmi_get_processor_handles_by_type(amdsmi_socket_handle socket_handle,
2784  processor_type_t processor_type,
2785  amdsmi_processor_handle *processor_handles,
2786  uint32_t *processor_count);
2787 
2807 amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle,
2808  processor_type_t *processor_type);
2809 
2841 amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count, amdsmi_socket_handle *socket_handles);
2842 
2884 amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle,
2885  uint32_t *processor_count,
2886  amdsmi_processor_handle *processor_handles);
2887 
2907 amdsmi_status_t amdsmi_get_socket_info(amdsmi_socket_handle socket_handle, size_t len, char *name);
2908 
2926 amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_processor_handle *processor_handle);
2927 
2942 amdsmi_status_t amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);
2943 
2963 amdsmi_status_t amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid);
2964 
2982  amdsmi_status_t amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle, amdsmi_virtualization_mode_t *mode);
2983 
3009 amdsmi_status_t amdsmi_get_cpu_affinity_with_scope(amdsmi_processor_handle processor_handle,
3010  uint32_t cpu_set_size, uint64_t *cpu_set, amdsmi_affinity_scope_t scope);
3011 
3032 amdsmi_status_t amdsmi_get_node_handle(amdsmi_processor_handle processor_handle, amdsmi_node_handle *node_handle);
3033 
3048 amdsmi_status_t amdsmi_get_index_from_processor_handle(amdsmi_processor_handle processor_handle, uint32_t *processor_index);
3049 
3066 amdsmi_status_t amdsmi_get_processor_handle_from_index(uint32_t processor_index, amdsmi_processor_handle *processor_handle);
3067 
3081 amdsmi_status_t amdsmi_get_processor_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);
3082 
3097 amdsmi_status_t amdsmi_get_processor_handle_from_uuid(const char *uuid, amdsmi_processor_handle *processor_handle);
3098 
3113 amdsmi_status_t amdsmi_get_vf_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_vf_handle_t *vf_handle);
3114 
3129 amdsmi_status_t amdsmi_get_vf_handle_from_uuid(const char *uuid, amdsmi_vf_handle_t *vf_handle);
3130 
3146 amdsmi_status_t amdsmi_get_vf_handle_from_vf_index(amdsmi_processor_handle processor_handle, uint32_t fcn_idx, amdsmi_vf_handle_t *vf_handle);
3147 
3161 amdsmi_status_t amdsmi_get_vf_bdf(amdsmi_vf_handle_t vf_handle, amdsmi_bdf_t *bdf);
3162 
3181 amdsmi_status_t amdsmi_get_vf_uuid(amdsmi_vf_handle_t processor_handle, unsigned int *uuid_length, char *uuid);
3182 
3218 amdsmi_status_t amdsmi_get_nic_processor_handles(amdsmi_socket_handle socket_handle,
3219  uint32_t *processor_count,
3220  amdsmi_processor_handle *processor_handles);
3221 
3235 amdsmi_status_t amdsmi_get_nic_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);
3236 
3239 /*****************************************************************************/
3260 amdsmi_status_t amdsmi_get_lib_version(amdsmi_version_t *version);
3261 
3264 /*****************************************************************************/
3289 amdsmi_status_t amdsmi_status_code_to_string(amdsmi_status_t status, const char **status_string);
3290 
3293 /*****************************************************************************/
3313 amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info);
3314 
3328 amdsmi_status_t amdsmi_get_gpu_driver_model(amdsmi_processor_handle processor_handle, amdsmi_driver_model_type_t *model);
3329 
3332 /*****************************************************************************/
3359 amdsmi_status_t amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info);
3360 
3379 amdsmi_status_t
3380 amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind,
3381  amdsmi_power_cap_info_t *info);
3382 
3397 amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle, amdsmi_pcie_info_t *info);
3398 
3420 amdsmi_status_t amdsmi_get_gpu_pci_bandwidth(amdsmi_processor_handle processor_handle, amdsmi_pcie_bandwidth_t *bandwidth);
3421 
3436 amdsmi_status_t amdsmi_get_gpu_vram_info(amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info);
3437 
3452 amdsmi_status_t amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info);
3453 
3468 amdsmi_status_t amdsmi_get_fb_layout(amdsmi_processor_handle processor_handle, amdsmi_pf_fb_info_t *info);
3469 
3472 /*****************************************************************************/
3491 amdsmi_status_t
3492 amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info);
3493 
3509 amdsmi_status_t
3510 amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info);
3511 
3526 amdsmi_status_t amdsmi_get_fw_error_records(amdsmi_processor_handle processor_handle, amdsmi_fw_error_record_t *records);
3527 
3541 amdsmi_status_t amdsmi_get_dfc_fw_table(amdsmi_processor_handle processor_handle, amdsmi_dfc_fw_t *info);
3542 
3545 /*****************************************************************************/
3564 amdsmi_status_t amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info);
3565 
3583 amdsmi_status_t amdsmi_get_power_info(amdsmi_processor_handle processor_handle, amdsmi_power_info_t *info);
3584 
3598 amdsmi_status_t
3599 amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled);
3600 
3620 amdsmi_status_t amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info);
3621 
3651 amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle, amdsmi_temperature_type_t sensor_type,
3652  amdsmi_temperature_metric_t metric, int64_t *temperature);
3653 
3675 amdsmi_status_t amdsmi_get_gpu_metrics(amdsmi_processor_handle processor_handle, uint32_t *metrics_size,
3676  amdsmi_metric_t *metrics);
3677 
3680 /*****************************************************************************/
3699  amdsmi_status_t
3700  amdsmi_get_gpu_memory_partition_config(amdsmi_processor_handle processor_handle,
3701  amdsmi_memory_partition_config_t *config);
3702 
3726 amdsmi_status_t
3727 amdsmi_set_gpu_memory_partition_mode(amdsmi_processor_handle processor_handle,
3728  amdsmi_memory_partition_type_t mode);
3729 
3732 /*****************************************************************************/
3754 amdsmi_status_t
3755 amdsmi_get_gpu_accelerator_partition_profile_config(amdsmi_processor_handle processor_handle,
3756  amdsmi_accelerator_partition_profile_config_t *profile_config);
3757 
3778 amdsmi_status_t
3779 amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle,
3780  amdsmi_accelerator_partition_profile_t *profile,
3781  uint32_t *partition_id);
3782 
3800 amdsmi_status_t
3801 amdsmi_set_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle,
3802  uint32_t profile_index);
3803 
3826 amdsmi_status_t
3827 amdsmi_get_gpu_accelerator_partition_profile_config_global(amdsmi_processor_handle processor_handle,
3828  amdsmi_accelerator_partition_profile_config_global_t *config);
3829 
3832 /*****************************************************************************/
3851 amdsmi_status_t amdsmi_get_link_metrics(amdsmi_processor_handle processor_handle, amdsmi_link_metrics_t *link_metrics);
3852 
3877 amdsmi_status_t
3878 amdsmi_get_link_topology_nearest(amdsmi_processor_handle processor_handle,
3879  amdsmi_link_type_t link_type,
3880  amdsmi_topology_nearest_t* topology_nearest_info);
3881 
3908 amdsmi_status_t amdsmi_topo_get_p2p_status(amdsmi_processor_handle processor_handle_src,
3909  amdsmi_processor_handle processor_handle_dst,
3910  amdsmi_link_type_t *type, amdsmi_p2p_capability_t *cap);
3911 
3931 amdsmi_status_t amdsmi_topo_get_numa_node_number(amdsmi_processor_handle processor_handle, uint32_t *numa_node);
3932 
3949 amdsmi_status_t amdsmi_get_link_topology(amdsmi_processor_handle processor_handle_src,
3950  amdsmi_processor_handle processor_handle_dst,
3951  amdsmi_link_topology_t *topology_info);
3952 
3967 amdsmi_status_t amdsmi_get_xgmi_fb_sharing_caps(amdsmi_processor_handle processor_handle,
3968  amdsmi_xgmi_fb_sharing_caps_t *caps);
3969 
3988 amdsmi_status_t amdsmi_get_xgmi_fb_sharing_mode_info(amdsmi_processor_handle processor_handle_src,
3989  amdsmi_processor_handle processor_handle_dst,
3990  amdsmi_xgmi_fb_sharing_mode_t mode,
3991  uint8_t *fb_sharing);
3992 
4006 amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode(amdsmi_processor_handle processor_handle,
4007  amdsmi_xgmi_fb_sharing_mode_t mode);
4008 
4026 amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode_v2(amdsmi_processor_handle *processor_list,
4027  uint32_t num_processors,
4028  amdsmi_xgmi_fb_sharing_mode_t mode);
4029 
4032 /*****************************************************************************/
4058 amdsmi_status_t amdsmi_get_soc_pstate(amdsmi_processor_handle processor_handle,
4059  amdsmi_dpm_policy_t* policy);
4060 
4082 amdsmi_status_t amdsmi_set_soc_pstate(amdsmi_processor_handle processor_handle,
4083  uint32_t policy_id);
4084 
4104 amdsmi_status_t amdsmi_get_xgmi_plpd(amdsmi_processor_handle processor_handle,
4105  amdsmi_dpm_policy_t *xgmi_plpd);
4106 
4128 amdsmi_status_t amdsmi_set_xgmi_plpd(amdsmi_processor_handle processor_handle,
4129  uint32_t policy_id);
4130 
4133 /*****************************************************************************/
4160 amdsmi_status_t amdsmi_set_power_cap(amdsmi_processor_handle processor_handle,
4161  uint32_t sensor_ind, uint64_t cap);
4162 
4182 amdsmi_status_t amdsmi_get_supported_power_cap(amdsmi_processor_handle processor_handle,
4183  uint32_t *sensor_count,
4184  uint32_t *sensor_inds,
4185  amdsmi_power_cap_type_t *sensor_types);
4186 
4189 /*****************************************************************************/
4210 amdsmi_status_t amdsmi_get_gpu_cache_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info);
4211 
4214 /*****************************************************************************/
4244 amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle,
4245  amdsmi_gpu_block_t block, amdsmi_error_count_t *ec);
4246 
4274 amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle,
4275  uint64_t *enabled_blocks);
4276 
4293 amdsmi_status_t
4294 amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec);
4295 
4298 /*****************************************************************************/
4339 amdsmi_status_t
4340 amdsmi_get_gpu_cper_entries(amdsmi_processor_handle processor_handle, uint32_t severity_mask, char *cper_data,
4341  uint64_t *buf_size, amdsmi_cper_hdr_t** cper_hdrs, uint64_t *entry_count, uint64_t *cursor);
4342 
4369 amdsmi_status_t amdsmi_get_afids_from_cper(char *cper_buffer, uint32_t buf_size, uint64_t *afids, uint32_t *num_afids);
4370 
4385 amdsmi_status_t amdsmi_get_gpu_ras_feature_info(amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature);
4386 
4406 amdsmi_status_t amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *bad_page_size,
4407  amdsmi_eeprom_table_record_t *bad_pages);
4408 
4425 amdsmi_status_t amdsmi_get_gpu_ras_policy_info(amdsmi_processor_handle processor_handle,
4426  amdsmi_gpu_ras_policy_info_t *info);
4427 
4453 amdsmi_status_t amdsmi_get_bad_page_threshold(amdsmi_processor_handle processor_handle, uint32_t *threshold);
4454 
4457 /*****************************************************************************/
4482 amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle);
4483 
4507 amdsmi_status_t amdsmi_get_npm_info(amdsmi_node_handle node_handle, amdsmi_npm_info_t *info);
4508 
4511 /*****************************************************************************/
4536 amdsmi_status_t
4537 amdsmi_get_gpu_ptl_state(amdsmi_processor_handle processor_handle, bool *enabled);
4538 
4557 amdsmi_status_t amdsmi_set_gpu_ptl_state(amdsmi_processor_handle processor_handle, bool enable);
4558 
4581 amdsmi_status_t
4582 amdsmi_get_gpu_ptl_formats(amdsmi_processor_handle processor_handle,
4583  amdsmi_ptl_data_format_t *data_format1,
4584  amdsmi_ptl_data_format_t *data_format2);
4585 
4610 amdsmi_status_t
4611 amdsmi_set_gpu_ptl_formats(amdsmi_processor_handle processor_handle,
4612  amdsmi_ptl_data_format_t data_format1,
4613  amdsmi_ptl_data_format_t data_format2);
4614 
4617 /*****************************************************************************/
4639 amdsmi_status_t
4640 amdsmi_get_num_vf(amdsmi_processor_handle processor_handle, uint32_t *num_vf_enabled,
4641  uint32_t *num_vf_supported);
4642 
4661 amdsmi_status_t
4662 amdsmi_get_vf_partition_info(amdsmi_processor_handle processor_handle, unsigned int vf_buffer_num,
4663  amdsmi_partition_info_t *info);
4664 
4679 amdsmi_status_t
4680 amdsmi_get_partition_profile_info(amdsmi_processor_handle processor_handle,
4681  amdsmi_profile_info_t *profile_info);
4682 
4685 /*****************************************************************************/
4704 amdsmi_status_t
4705 amdsmi_get_vf_info(amdsmi_vf_handle_t vf_handle, amdsmi_vf_info_t *config);
4706 
4721 amdsmi_status_t
4722 amdsmi_get_vf_data(amdsmi_vf_handle_t vf_handle, amdsmi_vf_data_t *info);
4723 
4726 /*****************************************************************************/
4766 amdsmi_status_t
4767 amdsmi_event_create(amdsmi_processor_handle *processor_list, uint32_t num_devices,
4768  uint64_t event_types, amdsmi_event_set *set);
4769 
4801 amdsmi_status_t
4802 amdsmi_event_read(amdsmi_event_set set, int64_t timeout_usec, amdsmi_event_entry_t *event);
4803 
4815 amdsmi_status_t
4816 amdsmi_event_destroy(amdsmi_event_set set);
4817 
4820 /*****************************************************************************/
4842 amdsmi_status_t
4843 amdsmi_get_guest_data(amdsmi_vf_handle_t vf_handle, amdsmi_guest_data_t *info);
4844 
4860 amdsmi_status_t
4861 amdsmi_get_vf_fw_info(amdsmi_vf_handle_t vf_handle, amdsmi_fw_info_t *info);
4862 
4865 /*****************************************************************************/
4882 amdsmi_status_t amdsmi_clear_vf_fb(amdsmi_vf_handle_t vf_handle);
4883 
4897 amdsmi_status_t amdsmi_set_num_vf(amdsmi_processor_handle processor_handle, uint32_t num_vf);
4898 
4901 /*****************************************************************************/
4920 amdsmi_status_t amdsmi_get_nic_driver_info(amdsmi_processor_handle processor_handle, amdsmi_nic_driver_info_t *info);
4921 
4936 amdsmi_status_t amdsmi_get_nic_asic_info(amdsmi_processor_handle processor_handle, amdsmi_nic_asic_info_t *info);
4937 
4952 amdsmi_status_t amdsmi_get_nic_bus_info(amdsmi_processor_handle processor_handle, amdsmi_nic_bus_info_t *info);
4953 
4968 amdsmi_status_t amdsmi_get_nic_numa_info(amdsmi_processor_handle processor_handle, amdsmi_nic_numa_info_t *info);
4969 
4984 amdsmi_status_t amdsmi_get_nic_port_info(amdsmi_processor_handle processor_handle, amdsmi_nic_port_info_t *info);
4985 
5000 amdsmi_status_t amdsmi_get_nic_rdma_dev_info(amdsmi_processor_handle processor_handle, amdsmi_nic_rdma_devices_info_t *info);
5001 
5024 amdsmi_status_t amdsmi_get_nic_port_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index,
5025  uint32_t *num_stats, amdsmi_nic_stat_t *stats);
5026 
5053 amdsmi_status_t amdsmi_get_nic_vendor_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index,
5054  uint32_t *num_stats, amdsmi_nic_stat_t *stats);
5055 
5078 amdsmi_status_t amdsmi_get_nic_rdma_port_statistics(amdsmi_processor_handle processor_handle, uint32_t rdma_port_index,
5079  uint32_t *num_stats, amdsmi_nic_stat_t *stats);
5080 
5097 amdsmi_status_t amdsmi_topo_get_nic_link_type(amdsmi_processor_handle nic_handle,
5098  amdsmi_processor_handle processor_handle, amdsmi_nic_link_type_t *type);
5099 
5102 #ifdef __cplusplus
5103 }
5104 #endif
5105 
5106 #endif // __AMDSMI_H__
5107 
amdsmi_event_reset_t
amdsmi_event_reset_t
Event Reset.
Definition: amdsmi.h:1456
amdsmi_vf_mode_t
amdsmi_vf_mode_t
Definition: amdsmi.h:2115
AMDSMI_VF_MODE_ALL
@ AMDSMI_VF_MODE_ALL
All VF counts supported.
Definition: amdsmi.h:2120
AMDSMI_MAX_ACCELERATOR_PROFILE
#define AMDSMI_MAX_ACCELERATOR_PROFILE
Maximum number of accelerator profiles.
Definition: amdsmi.h:167
AMDSMI_MAX_WHITE_LIST_ELEMENTS
#define AMDSMI_MAX_WHITE_LIST_ELEMENTS
Maximum number of white list elements for device access control.
Definition: amdsmi.h:186
amdsmi_event_fw_t
amdsmi_event_fw_t
Event Firmware.
Definition: amdsmi.h:1402
amdsmi_metric_category_t
amdsmi_metric_category_t
Metric Category.
Definition: amdsmi.h:1905
amdsmi_npm_status_t
amdsmi_npm_status_t
NPM status.
Definition: amdsmi.h:628
amdsmi_link_type_t
amdsmi_link_type_t
Link type.
Definition: amdsmi.h:450
AMDSMI_LINK_TYPE_NOT_APPLICABLE
@ AMDSMI_LINK_TYPE_NOT_APPLICABLE
Not Applicable Link Type.
Definition: amdsmi.h:454
AMDSMI_LINK_TYPE_INTERNAL
@ AMDSMI_LINK_TYPE_INTERNAL
Internal Link Type, within chip.
Definition: amdsmi.h:451
AMDSMI_LINK_TYPE_UNKNOWN
@ AMDSMI_LINK_TYPE_UNKNOWN
Unknown Link Type.
Definition: amdsmi.h:455
AMDSMI_LINK_TYPE_PCIE
@ AMDSMI_LINK_TYPE_PCIE
Peripheral Component Interconnect Express Link Type.
Definition: amdsmi.h:452
AMDSMI_LINK_TYPE_XGMI
@ AMDSMI_LINK_TYPE_XGMI
GPU Memory Interconnect (multi GPU communication)
Definition: amdsmi.h:453
amdsmi_event_xgmi_t
amdsmi_event_xgmi_t
Event XGMI.
Definition: amdsmi.h:1706
AMDSMI_MAX_PROFILE_COUNT
#define AMDSMI_MAX_PROFILE_COUNT
Maximum number of profiles supported.
Definition: amdsmi.h:191
amdsmi_event_ecc_t
amdsmi_event_ecc_t
Event ECC.
Definition: amdsmi.h:1494
amdsmi_event_gpumon_t
amdsmi_event_gpumon_t
Event GPU Monitor.
Definition: amdsmi.h:1671
amdsmi_accelerator_partition_type_t
amdsmi_accelerator_partition_type_t
Accelerator Partition.
Definition: amdsmi.h:236
AMDSMI_ACCELERATOR_PARTITION_DPX
@ AMDSMI_ACCELERATOR_PARTITION_DPX
Definition: amdsmi.h:240
AMDSMI_ACCELERATOR_PARTITION_QPX
@ AMDSMI_ACCELERATOR_PARTITION_QPX
Definition: amdsmi.h:244
AMDSMI_ACCELERATOR_PARTITION_INVALID
@ AMDSMI_ACCELERATOR_PARTITION_INVALID
Invalid accelerator partition type.
Definition: amdsmi.h:237
AMDSMI_ACCELERATOR_PARTITION_SPX
@ AMDSMI_ACCELERATOR_PARTITION_SPX
Definition: amdsmi.h:238
AMDSMI_ACCELERATOR_PARTITION_TPX
@ AMDSMI_ACCELERATOR_PARTITION_TPX
Definition: amdsmi.h:242
AMDSMI_ACCELERATOR_PARTITION_CPX
@ AMDSMI_ACCELERATOR_PARTITION_CPX
Definition: amdsmi.h:246
amdsmi_event_guard_t
amdsmi_event_guard_t
Event Guard.
Definition: amdsmi.h:1660
amdsmi_vf_config_flags_t
amdsmi_vf_config_flags_t
VF Config Flags.
Definition: amdsmi.h:1774
amdsmi_power_cap_type_t
amdsmi_power_cap_type_t
Power Cap Package Power Tracking (PPT) type.
Definition: amdsmi.h:780
AMDSMI_POWER_CAP_TYPE_PPT1
@ AMDSMI_POWER_CAP_TYPE_PPT1
PPT1 power cap; higher limit, raw input.
Definition: amdsmi.h:782
AMDSMI_POWER_CAP_TYPE_PPT0
@ AMDSMI_POWER_CAP_TYPE_PPT0
PPT0 power cap; lower limit, filtered input.
Definition: amdsmi.h:781
amdsmi_clk_type_t
amdsmi_clk_type_t
Clock types.
Definition: amdsmi.h:302
AMDSMI_CLK_TYPE_DCLK1
@ AMDSMI_CLK_TYPE_DCLK1
Display 2 clock, timing signals for display output.
Definition: amdsmi.h:316
AMDSMI_CLK_TYPE_MEM
@ AMDSMI_CLK_TYPE_MEM
Memory clock speed, system operating frequency.
Definition: amdsmi.h:311
AMDSMI_CLK_TYPE_SYS
@ AMDSMI_CLK_TYPE_SYS
System clock.
Definition: amdsmi.h:303
AMDSMI_CLK_TYPE_SOC
@ AMDSMI_CLK_TYPE_SOC
System On Chip clock, integrated circuit frequency.
Definition: amdsmi.h:310
AMDSMI_CLK_TYPE_GFX
@ AMDSMI_CLK_TYPE_GFX
Graphics clock.
Definition: amdsmi.h:305
AMDSMI_CLK_TYPE_DCLK0
@ AMDSMI_CLK_TYPE_DCLK0
Display 1 clock, timing signals for display output.
Definition: amdsmi.h:315
AMDSMI_CLK_TYPE_DCEF
@ AMDSMI_CLK_TYPE_DCEF
Definition: amdsmi.h:308
AMDSMI_CLK_TYPE_VCLK1
@ AMDSMI_CLK_TYPE_VCLK1
Video 1 clock, video processing units.
Definition: amdsmi.h:314
AMDSMI_CLK_TYPE_DF
@ AMDSMI_CLK_TYPE_DF
Definition: amdsmi.h:306
AMDSMI_CLK_TYPE_VCLK0
@ AMDSMI_CLK_TYPE_VCLK0
Video 0 clock, video processing units.
Definition: amdsmi.h:313
AMDSMI_CLK_TYPE_PCIE
@ AMDSMI_CLK_TYPE_PCIE
PCI Express clock, high bandwidth peripherals.
Definition: amdsmi.h:312
amdsmi_accelerator_partition_resource_type_t
amdsmi_accelerator_partition_resource_type_t
Accelerator Partition Resource Types.
Definition: amdsmi.h:288
AMDSMI_ACCELERATOR_DMA
@ AMDSMI_ACCELERATOR_DMA
Direct Memory Access, high speed data transfers.
Definition: amdsmi.h:292
AMDSMI_ACCELERATOR_XCC
@ AMDSMI_ACCELERATOR_XCC
Compute complex or stream processors.
Definition: amdsmi.h:289
AMDSMI_ACCELERATOR_DECODER
@ AMDSMI_ACCELERATOR_DECODER
Video decoding.
Definition: amdsmi.h:291
AMDSMI_ACCELERATOR_JPEG
@ AMDSMI_ACCELERATOR_JPEG
Encoding and Decoding jpeg engines.
Definition: amdsmi.h:293
AMDSMI_ACCELERATOR_ENCODER
@ AMDSMI_ACCELERATOR_ENCODER
Video encoding.
Definition: amdsmi.h:290
AMDSMI_MAX_ERR_RECORDS
#define AMDSMI_MAX_ERR_RECORDS
Maximum number of error records that can be stored.
Definition: amdsmi.h:190
amdsmi_card_form_factor_t
amdsmi_card_form_factor_t
Card Form Factor.
Definition: amdsmi.h:438
AMDSMI_CARD_FORM_FACTOR_OAM
@ AMDSMI_CARD_FORM_FACTOR_OAM
OAM form factor.
Definition: amdsmi.h:440
AMDSMI_CARD_FORM_FACTOR_UNKNOWN
@ AMDSMI_CARD_FORM_FACTOR_UNKNOWN
Unknown Form factor.
Definition: amdsmi.h:442
AMDSMI_CARD_FORM_FACTOR_PCIE
@ AMDSMI_CARD_FORM_FACTOR_PCIE
PCIE card form factor.
Definition: amdsmi.h:439
AMDSMI_CARD_FORM_FACTOR_CEM
@ AMDSMI_CARD_FORM_FACTOR_CEM
CEM form factor.
Definition: amdsmi.h:441
amdsmi_node_handle
void * amdsmi_node_handle
opaque handler point to underlying implementation
Definition: amdsmi.h:207
AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK
#define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK
Common defines.
Definition: amdsmi.h:152
amdsmi_guard_type_t
amdsmi_guard_type_t
Guard Event.
Definition: amdsmi.h:1810
amdsmi_pp_throttler_type_t
amdsmi_pp_throttler_type_t
This enum determines which type of PP throttler event occurred.
Definition: amdsmi.h:1720
amdsmi_profile_capability_type_t
amdsmi_profile_capability_type_t
Profile Capability.
Definition: amdsmi.h:1892
AMDSMI_PROFILE_CAPABILITY_DECODE
@ AMDSMI_PROFILE_CAPABILITY_DECODE
decode engine
Definition: amdsmi.h:1895
AMDSMI_PROFILE_CAPABILITY_MEMORY
@ AMDSMI_PROFILE_CAPABILITY_MEMORY
memory
Definition: amdsmi.h:1893
AMDSMI_PROFILE_CAPABILITY_ENCODE
@ AMDSMI_PROFILE_CAPABILITY_ENCODE
encode engine
Definition: amdsmi.h:1894
AMDSMI_PROFILE_CAPABILITY_COMPUTE
@ AMDSMI_PROFILE_CAPABILITY_COMPUTE
compute engine
Definition: amdsmi.h:1896
amdsmi_init_flags_t
amdsmi_init_flags_t
Initialization flags.
Definition: amdsmi.h:48
AMDSMI_INIT_AMD_GPUS
@ AMDSMI_INIT_AMD_GPUS
Initialize AMD GPUS.
Definition: amdsmi.h:51
AMDSMI_INIT_ALL_PROCESSORS
@ AMDSMI_INIT_ALL_PROCESSORS
Initialize all processors.
Definition: amdsmi.h:49
AMDSMI_INIT_AMD_CPUS
@ AMDSMI_INIT_AMD_CPUS
Initialize AMD CPUS.
Definition: amdsmi.h:50
AMDSMI_INIT_NON_AMD_GPUS
@ AMDSMI_INIT_NON_AMD_GPUS
Initialize Non-AMD GPUS.
Definition: amdsmi.h:53
AMDSMI_INIT_AMD_NICS
@ AMDSMI_INIT_AMD_NICS
Initialize AMD NICS.
Definition: amdsmi.h:56
AMDSMI_INIT_NON_AMD_CPUS
@ AMDSMI_INIT_NON_AMD_CPUS
Initialize Non-AMD CPUS.
Definition: amdsmi.h:52
AMDSMI_INIT_AMD_APUS
@ AMDSMI_INIT_AMD_APUS
Definition: amdsmi.h:54
amdsmi_event_pp_t
amdsmi_event_pp_t
Event PP.
Definition: amdsmi.h:1563
amdsmi_event_vbios_t
amdsmi_event_vbios_t
Event VBios.
Definition: amdsmi.h:1633
amdsmi_event_set
void * amdsmi_event_set
Opague Handler point to underlying implementation.
Definition: amdsmi.h:1284
AMDSMI_MAX_NIC_FW
#define AMDSMI_MAX_NIC_FW
Maximum number of NIC firmwares.
Definition: amdsmi.h:2514
amdsmi_vram_type_t
amdsmi_vram_type_t
vRam Types. This enum is used to identify various VRam types.
Definition: amdsmi.h:256
AMDSMI_VRAM_TYPE_GDDR2
@ AMDSMI_VRAM_TYPE_GDDR2
Graphics Double Data Rate, Generation 2.
Definition: amdsmi.h:271
AMDSMI_VRAM_TYPE_HBM2E
@ AMDSMI_VRAM_TYPE_HBM2E
High Bandwidth Memory, Generation 2 Enhanced.
Definition: amdsmi.h:261
AMDSMI_VRAM_TYPE_GDDR6
@ AMDSMI_VRAM_TYPE_GDDR6
Graphics Double Data Rate, Generation 6.
Definition: amdsmi.h:275
AMDSMI_VRAM_TYPE_HBM
@ AMDSMI_VRAM_TYPE_HBM
High Bandwidth Memory.
Definition: amdsmi.h:259
AMDSMI_VRAM_TYPE_GDDR3
@ AMDSMI_VRAM_TYPE_GDDR3
Graphics Double Data Rate, Generation 3.
Definition: amdsmi.h:272
AMDSMI_VRAM_TYPE_GDDR1
@ AMDSMI_VRAM_TYPE_GDDR1
Graphics Double Data Rate, Generation 1.
Definition: amdsmi.h:270
AMDSMI_VRAM_TYPE_HBM3
@ AMDSMI_VRAM_TYPE_HBM3
High Bandwidth Memory, Generation 3.
Definition: amdsmi.h:262
AMDSMI_VRAM_TYPE_LPDDR5
@ AMDSMI_VRAM_TYPE_LPDDR5
Low Power Double Data Rate, Generation 5.
Definition: amdsmi.h:279
AMDSMI_VRAM_TYPE_HBM3E
@ AMDSMI_VRAM_TYPE_HBM3E
High Bandwidth Memory, Generation 3 Enhanced.
Definition: amdsmi.h:263
AMDSMI_VRAM_TYPE_GDDR5
@ AMDSMI_VRAM_TYPE_GDDR5
Graphics Double Data Rate, Generation 5.
Definition: amdsmi.h:274
AMDSMI_VRAM_TYPE_DDR3
@ AMDSMI_VRAM_TYPE_DDR3
Double Data Rate, Generation 3.
Definition: amdsmi.h:266
AMDSMI_VRAM_TYPE_GDDR4
@ AMDSMI_VRAM_TYPE_GDDR4
Graphics Double Data Rate, Generation 4.
Definition: amdsmi.h:273
AMDSMI_VRAM_TYPE_DDR2
@ AMDSMI_VRAM_TYPE_DDR2
Double Data Rate, Generation 2.
Definition: amdsmi.h:265
AMDSMI_VRAM_TYPE_GDDR7
@ AMDSMI_VRAM_TYPE_GDDR7
Graphics Double Data Rate, Generation 7.
Definition: amdsmi.h:276
AMDSMI_VRAM_TYPE_HBM2
@ AMDSMI_VRAM_TYPE_HBM2
High Bandwidth Memory, Generation 2.
Definition: amdsmi.h:260
AMDSMI_VRAM_TYPE_LPDDR4
@ AMDSMI_VRAM_TYPE_LPDDR4
Low Power Double Data Rate, Generation 4.
Definition: amdsmi.h:278
AMDSMI_VRAM_TYPE_DDR5
@ AMDSMI_VRAM_TYPE_DDR5
Double Data Rate, Generation 5.
Definition: amdsmi.h:268
AMDSMI_VRAM_TYPE_DDR4
@ AMDSMI_VRAM_TYPE_DDR4
Double Data Rate, Generation 4.
Definition: amdsmi.h:267
AMDSMI_VRAM_TYPE_UNKNOWN
@ AMDSMI_VRAM_TYPE_UNKNOWN
Unknown memory type.
Definition: amdsmi.h:257
amdsmi_event_vf_max_t
amdsmi_event_vf_max_t
Event VF.
Definition: amdsmi.h:1614
amdsmi_metric_type_t
amdsmi_metric_type_t
Metric Type.
Definition: amdsmi.h:2088
AMDSMI_METRIC_TYPE_COUNTER
@ AMDSMI_METRIC_TYPE_COUNTER
counter metric
Definition: amdsmi.h:2089
AMDSMI_METRIC_TYPE_CHIPLET
@ AMDSMI_METRIC_TYPE_CHIPLET
chiplet metric
Definition: amdsmi.h:2090
AMDSMI_METRIC_TYPE_ACC
@ AMDSMI_METRIC_TYPE_ACC
accumulated metric
Definition: amdsmi.h:2092
AMDSMI_METRIC_TYPE_INST
@ AMDSMI_METRIC_TYPE_INST
instantaneous metric
Definition: amdsmi.h:2091
AMDSMI_MAX_ACCELERATOR_PARTITIONS
#define AMDSMI_MAX_ACCELERATOR_PARTITIONS
Maximum number of accelerator partitions.
Definition: amdsmi.h:166
amdsmi_cper_notify_type_t
amdsmi_cper_notify_type_t
Cper notify.
Definition: amdsmi.h:1115
AMDSMI_CPER_NOTIFY_TYPE_DMAR
@ AMDSMI_CPER_NOTIFY_TYPE_DMAR
Direct Memory Access Remapping Error.
Definition: amdsmi.h:1123
AMDSMI_CPER_NOTIFY_TYPE_NMI
@ AMDSMI_CPER_NOTIFY_TYPE_NMI
Non_Maskable Interrupt.
Definition: amdsmi.h:1121
AMDSMI_CPER_NOTIFY_TYPE_SEI
@ AMDSMI_CPER_NOTIFY_TYPE_SEI
System Error Interface.
Definition: amdsmi.h:1125
AMDSMI_CPER_NOTIFY_TYPE_CMC
@ AMDSMI_CPER_NOTIFY_TYPE_CMC
Corrected Memory Check.
Definition: amdsmi.h:1116
AMDSMI_CPER_NOTIFY_TYPE_CPE
@ AMDSMI_CPER_NOTIFY_TYPE_CPE
Corrected Platform Error.
Definition: amdsmi.h:1117
AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT
@ AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT
Compute Express Link Component Error.
Definition: amdsmi.h:1127
AMDSMI_CPER_NOTIFY_TYPE_SEA
@ AMDSMI_CPER_NOTIFY_TYPE_SEA
System Error Architecture.
Definition: amdsmi.h:1124
AMDSMI_CPER_NOTIFY_TYPE_PEI
@ AMDSMI_CPER_NOTIFY_TYPE_PEI
Platform Error Interface.
Definition: amdsmi.h:1126
AMDSMI_CPER_NOTIFY_TYPE_MCE
@ AMDSMI_CPER_NOTIFY_TYPE_MCE
Machine Check Exception.
Definition: amdsmi.h:1118
AMDSMI_CPER_NOTIFY_TYPE_BOOT
@ AMDSMI_CPER_NOTIFY_TYPE_BOOT
Boot Error.
Definition: amdsmi.h:1122
AMDSMI_CPER_NOTIFY_TYPE_PCIE
@ AMDSMI_CPER_NOTIFY_TYPE_PCIE
PCI Express Error.
Definition: amdsmi.h:1119
AMDSMI_CPER_NOTIFY_TYPE_INIT
@ AMDSMI_CPER_NOTIFY_TYPE_INIT
Initialization Error.
Definition: amdsmi.h:1120
AMDSMI_MAX_CP_PROFILE_RESOURCES
#define AMDSMI_MAX_CP_PROFILE_RESOURCES
Maximum number of compute profile resources.
Definition: amdsmi.h:165
processor_type_t
processor_type_t
Processor types detectable by AMD SMI.
Definition: amdsmi.h:72
AMDSMI_PROCESSOR_TYPE_AMD_APU
@ AMDSMI_PROCESSOR_TYPE_AMD_APU
AMD Accelerated processor type, GPU and CPU on a single die.
Definition: amdsmi.h:79
AMDSMI_PROCESSOR_TYPE_UNKNOWN
@ AMDSMI_PROCESSOR_TYPE_UNKNOWN
Unknown processor type.
Definition: amdsmi.h:73
AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU
@ AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU
Non-AMD CPU processor type.
Definition: amdsmi.h:77
AMDSMI_PROCESSOR_TYPE_AMD_CPU
@ AMDSMI_PROCESSOR_TYPE_AMD_CPU
AMD CPU processor type, a physical component that holds the CPU.
Definition: amdsmi.h:75
AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE
@ AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE
AMD CPU-Core processor type, individual processing units within the CPU.
Definition: amdsmi.h:78
AMDSMI_PROCESSOR_TYPE_AMD_GPU
@ AMDSMI_PROCESSOR_TYPE_AMD_GPU
AMD Graphics processor type.
Definition: amdsmi.h:74
AMDSMI_PROCESSOR_TYPE_BRCM_NIC
@ AMDSMI_PROCESSOR_TYPE_BRCM_NIC
Broadcom Network Interface Card processor type.
Definition: amdsmi.h:81
AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU
@ AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU
Non-AMD Graphics processor type.
Definition: amdsmi.h:76
AMDSMI_PROCESSOR_TYPE_AMD_NIC
@ AMDSMI_PROCESSOR_TYPE_AMD_NIC
AMD Network Interface Card processor type.
Definition: amdsmi.h:80
AMDSMI_PROCESSOR_TYPE_BRCM_SWITCH
@ AMDSMI_PROCESSOR_TYPE_BRCM_SWITCH
Broadcom Switch processor type.
Definition: amdsmi.h:82
amdsmi_fw_block_t
amdsmi_fw_block_t
The values of this enum are used to identify the various firmware blocks.
Definition: amdsmi.h:508
AMDSMI_FW_ID_ASD
@ AMDSMI_FW_ID_ASD
Asynchronous Shader Dispatcher.
Definition: amdsmi.h:582
AMDSMI_FW_ID_RS64_ME_P0_DATA
@ AMDSMI_FW_ID_RS64_ME_P0_DATA
Hardware Block RS64 - Micro Engine Partition 0 Data.
Definition: amdsmi.h:564
AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM
@ AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM
Rasterizier and L2 Cache Restore List System RAM Memory.
Definition: amdsmi.h:535
AMDSMI_FW_ID_SDMA7
@ AMDSMI_FW_ID_SDMA7
System Direct Memory Access 7 (high speed data transfers)
Definition: amdsmi.h:527
AMDSMI_FW_ID_PSP_BL
@ AMDSMI_FW_ID_PSP_BL
Platform Security Processor Bootloader (initial firmware)
Definition: amdsmi.h:547
AMDSMI_FW_ID_RLC
@ AMDSMI_FW_ID_RLC
Rasterizer and L2 Cache (rasterization processs)
Definition: amdsmi.h:519
AMDSMI_FW_ID_RS64_PFP
@ AMDSMI_FW_ID_RS64_PFP
Hardware Block RS64 - Pixel Front End Processor.
Definition: amdsmi.h:566
AMDSMI_FW_ID_SDMA_TH1
@ AMDSMI_FW_ID_SDMA_TH1
System Direct Memory Access - Thread Handler 1.
Definition: amdsmi.h:555
AMDSMI_FW_ID_MMSCH
@ AMDSMI_FW_ID_MMSCH
Multi-Media Shader Hardware Scheduler.
Definition: amdsmi.h:538
AMDSMI_FW_ID_RLX6
@ AMDSMI_FW_ID_RLX6
Hardware Block RLX6.
Definition: amdsmi.h:561
AMDSMI_FW_ID_PSP_SOSDRV
@ AMDSMI_FW_ID_PSP_SOSDRV
Platform Security Processor Secure Operating System Driver.
Definition: amdsmi.h:540
AMDSMI_FW_ID_TA_RAS
@ AMDSMI_FW_ID_TA_RAS
Trusted Applications - Reliablity Availability and Serviceability.
Definition: amdsmi.h:583
AMDSMI_FW_ID_PSP_KEYDB
@ AMDSMI_FW_ID_PSP_KEYDB
Platform Security Processor Table of Contents.
Definition: amdsmi.h:542
AMDSMI_FW_ID_RLC_SRLS
@ AMDSMI_FW_ID_RLC_SRLS
Rasterizier and L2 Cache - Shared Resource Local Segment.
Definition: amdsmi.h:587
AMDSMI_FW_ID_VCE
@ AMDSMI_FW_ID_VCE
Video Coding Engine (Encoding video)
Definition: amdsmi.h:530
AMDSMI_FW_ID_DMCU_ISR
@ AMDSMI_FW_ID_DMCU_ISR
Digital Micro Controller Unit - Interrupt Service Routine (interrupt handlers)
Definition: amdsmi.h:533
AMDSMI_FW_ID_SDMA6
@ AMDSMI_FW_ID_SDMA6
System Direct Memory Access 6 (high speed data transfers)
Definition: amdsmi.h:526
AMDSMI_FW_ID_PSP_DBG
@ AMDSMI_FW_ID_PSP_DBG
Platform Security Processor - Debug.
Definition: amdsmi.h:576
AMDSMI_FW_ID_CP_CE
@ AMDSMI_FW_ID_CP_CE
Compute Processor - Command_Engine (fetch, decode, dispatch)
Definition: amdsmi.h:512
AMDSMI_FW_ID_P2S_TABLE
@ AMDSMI_FW_ID_P2S_TABLE
Processor-to-System Table Firmware.
Definition: amdsmi.h:592
AMDSMI_FW_ID_DRV_CAP
@ AMDSMI_FW_ID_DRV_CAP
Driver Capabilities (capabilities, features)
Definition: amdsmi.h:545
AMDSMI_FW_ID_RS64_ME_P1_DATA
@ AMDSMI_FW_ID_RS64_ME_P1_DATA
Hardware Block RS64 - Micro Engine Partition 1 Data.
Definition: amdsmi.h:565
AMDSMI_FW_ID_MES_THREAD1
@ AMDSMI_FW_ID_MES_THREAD1
Micro Engine Scheduler - Thread 1.
Definition: amdsmi.h:559
AMDSMI_FW_ID_PM
@ AMDSMI_FW_ID_PM
Power Management Firmware.
Definition: amdsmi.h:588
AMDSMI_FW_ID_SDMA0
@ AMDSMI_FW_ID_SDMA0
System Direct Memory Access 0 (high speed data transfers)
Definition: amdsmi.h:520
AMDSMI_FW_ID_ISP
@ AMDSMI_FW_ID_ISP
Image Signal Processor (processing raw image data from sensors)
Definition: amdsmi.h:531
AMDSMI_FW_ID_PSP_SOC
@ AMDSMI_FW_ID_PSP_SOC
Platform Security Processor - System On a Chip.
Definition: amdsmi.h:575
AMDSMI_FW_ID_CP_PM4
@ AMDSMI_FW_ID_CP_PM4
Compute Processor Packet Processor 4 (processing command packets)
Definition: amdsmi.h:548
AMDSMI_FW_ID_RLC_P
@ AMDSMI_FW_ID_RLC_P
Rasterizier and L2 Cache Partition.
Definition: amdsmi.h:549
AMDSMI_FW_ID_SDMA_TH0
@ AMDSMI_FW_ID_SDMA_TH0
System Direct Memory Access - Thread Handler 0.
Definition: amdsmi.h:554
AMDSMI_FW_ID_MC
@ AMDSMI_FW_ID_MC
Memory Contoller (RAM and VRAM)
Definition: amdsmi.h:546
AMDSMI_FW_ID_VCN
@ AMDSMI_FW_ID_VCN
Video Core Next (encoding and decoding)
Definition: amdsmi.h:528
AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1
@ AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1
Hardware Block RLX6 Core 1 - Dynamic RAM Boot.
Definition: amdsmi.h:579
AMDSMI_FW_ID_MES_STACK
@ AMDSMI_FW_ID_MES_STACK
Micro Engine Scheduler - Stack.
Definition: amdsmi.h:558
AMDSMI_FW_ID_XGMI
@ AMDSMI_FW_ID_XGMI
XGMI (Interconnect) Firmware.
Definition: amdsmi.h:585
AMDSMI_FW_ID_PSP_TOC
@ AMDSMI_FW_ID_PSP_TOC
Platform Security Processor Table of Contents.
Definition: amdsmi.h:541
AMDSMI_FW_ID_IMU_IRAM
@ AMDSMI_FW_ID_IMU_IRAM
Input/Output Memory Management Unit - Instruction RAM.
Definition: amdsmi.h:553
AMDSMI_FW_ID_SEC_POLICY_STAGE2
@ AMDSMI_FW_ID_SEC_POLICY_STAGE2
Security Policy Stage 2 (security features)
Definition: amdsmi.h:550
AMDSMI_FW_ID_RS64_MEC_P2_DATA
@ AMDSMI_FW_ID_RS64_MEC_P2_DATA
Hardware Block RS64 - Micro Engine Controller Partition 2 Data.
Definition: amdsmi.h:572
AMDSMI_FW_ID_PLDM_BUNDLE
@ AMDSMI_FW_ID_PLDM_BUNDLE
Platform Level Data Model Firmware Bundle.
Definition: amdsmi.h:593
AMDSMI_FW_ID_TA_XGMI
@ AMDSMI_FW_ID_TA_XGMI
Trusted Applications - Reliablity XGMI.
Definition: amdsmi.h:584
AMDSMI_FW_ID_RS64_ME
@ AMDSMI_FW_ID_RS64_ME
Hardware Block RS64 - Micro Engine.
Definition: amdsmi.h:563
AMDSMI_FW_ID_SDMA3
@ AMDSMI_FW_ID_SDMA3
System Direct Memory Access 3 (high speed data transfers)
Definition: amdsmi.h:523
AMDSMI_FW_ID_SDMA1
@ AMDSMI_FW_ID_SDMA1
System Direct Memory Access 1 (high speed data transfers)
Definition: amdsmi.h:521
AMDSMI_FW_ID_CP_ME
@ AMDSMI_FW_ID_CP_ME
Compute Processor - Micro Engine (specialize processing)
Definition: amdsmi.h:514
AMDSMI_FW_ID_RS64_MEC_P3_DATA
@ AMDSMI_FW_ID_RS64_MEC_P3_DATA
Hardware Block RS64 - Micro Engine Controller Partition 3 Data.
Definition: amdsmi.h:573
AMDSMI_FW_ID_CP_MEC_JT1
@ AMDSMI_FW_ID_CP_MEC_JT1
Compute Processor - Micro Engine Controler Job Table 1 (queues, scheduling)
Definition: amdsmi.h:515
AMDSMI_FW_ID_UVD
@ AMDSMI_FW_ID_UVD
Unified Video Decoder (decode specific video formats)
Definition: amdsmi.h:529
AMDSMI_FW_ID_RLC_V
@ AMDSMI_FW_ID_RLC_V
Rasterizier and L2 Cache Virtual memory.
Definition: amdsmi.h:537
AMDSMI_FW_ID_SMC
@ AMDSMI_FW_ID_SMC
System Management Controller Firmware.
Definition: amdsmi.h:589
AMDSMI_FW_ID_SDMA4
@ AMDSMI_FW_ID_SDMA4
System Direct Memory Access 4 (high speed data transfers)
Definition: amdsmi.h:524
AMDSMI_FW_ID_MES_KIQ
@ AMDSMI_FW_ID_MES_KIQ
Micro Engine Scheduler - Kernel Indirect Queue.
Definition: amdsmi.h:557
AMDSMI_FW_ID_DMCU
@ AMDSMI_FW_ID_DMCU
Display Micro-Controller Unit.
Definition: amdsmi.h:590
AMDSMI_FW_ID_RLC_SRLG
@ AMDSMI_FW_ID_RLC_SRLG
Rasterizier and L2 Cache - Shared Resource Local Group.
Definition: amdsmi.h:586
AMDSMI_FW_ID_RS64_PFP_P1_DATA
@ AMDSMI_FW_ID_RS64_PFP_P1_DATA
Hardware Block RS64 - Pixel Front End Processor Partition 1 Data.
Definition: amdsmi.h:568
AMDSMI_FW_ID_RLX6_DRAM_BOOT
@ AMDSMI_FW_ID_RLX6_DRAM_BOOT
Hardware Block RLX6 - Dynamic Ram Boot.
Definition: amdsmi.h:562
AMDSMI_FW_ID_IMU_DRAM
@ AMDSMI_FW_ID_IMU_DRAM
Input/Output Memory Management Unit - Dynamic RAM.
Definition: amdsmi.h:552
AMDSMI_FW_ID_CP_MEC1
@ AMDSMI_FW_ID_CP_MEC1
Compute Processor - Micro Engine Controler 1 (scheduling, managing resources)
Definition: amdsmi.h:517
AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL
@ AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL
Rasterizier and L2 Cache Restore List Control.
Definition: amdsmi.h:536
AMDSMI_FW_ID_RS64_MEC_P0_DATA
@ AMDSMI_FW_ID_RS64_MEC_P0_DATA
Hardware Block RS64 - Micro Engine Controller Partition 0 Data.
Definition: amdsmi.h:570
AMDSMI_FW_ID_RLX6_CORE1
@ AMDSMI_FW_ID_RLX6_CORE1
Hardware Block RLX6 - Core 1.
Definition: amdsmi.h:578
AMDSMI_FW_ID_RS64_MEC_P1_DATA
@ AMDSMI_FW_ID_RS64_MEC_P1_DATA
Hardware Block RS64 - Micro Engine Controller Partition 1 Data.
Definition: amdsmi.h:571
AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM
@ AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM
Rasterizier and L2 Cache Restore List Graphics Processor Memory.
Definition: amdsmi.h:534
AMDSMI_FW_ID_PSP_INTF
@ AMDSMI_FW_ID_PSP_INTF
Platform Security Processor - Interface.
Definition: amdsmi.h:577
AMDSMI_FW_ID_CP_MEC_JT2
@ AMDSMI_FW_ID_CP_MEC_JT2
Compute Processor - Micro Engine Controler Job Table 2 (queues, scheduling)
Definition: amdsmi.h:516
AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST
@ AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST
Rasterizier and L2 Cache - Save Restore List.
Definition: amdsmi.h:581
AMDSMI_FW_ID_CP_PFP
@ AMDSMI_FW_ID_CP_PFP
Compute Processor - Pixel Front End Processor (pixelating process)
Definition: amdsmi.h:513
AMDSMI_FW_ID_PSP_RAS
@ AMDSMI_FW_ID_PSP_RAS
Platform Security Processor - Reliability, Availability, and Serviceability Firmware.
Definition: amdsmi.h:591
AMDSMI_FW_ID_MES_THREAD1_STACK
@ AMDSMI_FW_ID_MES_THREAD1_STACK
Micro Engine Scheduler - Thread 1 Stack.
Definition: amdsmi.h:560
AMDSMI_FW_ID_SMU
@ AMDSMI_FW_ID_SMU
Definition: amdsmi.h:509
AMDSMI_FW_ID_PPTABLE
@ AMDSMI_FW_ID_PPTABLE
Power Policy Table (power management policies)
Definition: amdsmi.h:574
AMDSMI_FW_ID_PSP_SPL
@ AMDSMI_FW_ID_PSP_SPL
Platform Security Processor Secure Program Loader.
Definition: amdsmi.h:544
AMDSMI_FW_ID_REG_ACCESS_WHITELIST
@ AMDSMI_FW_ID_REG_ACCESS_WHITELIST
Register Access Whitelist (Prevent unathorizied access)
Definition: amdsmi.h:551
AMDSMI_FW_ID_PSP_SYSDRV
@ AMDSMI_FW_ID_PSP_SYSDRV
Platform Security Processor System Driver.
Definition: amdsmi.h:539
AMDSMI_FW_ID_RS64_PFP_P0_DATA
@ AMDSMI_FW_ID_RS64_PFP_P0_DATA
Hardware Block RS64 - Pixel Front End Processor Partition 0 Data.
Definition: amdsmi.h:567
AMDSMI_FW_ID_SDMA5
@ AMDSMI_FW_ID_SDMA5
System Direct Memory Access 5 (high speed data transfers)
Definition: amdsmi.h:525
AMDSMI_FW_ID_SDMA2
@ AMDSMI_FW_ID_SDMA2
System Direct Memory Access 2 (high speed data transfers)
Definition: amdsmi.h:522
AMDSMI_FW_ID_CP_MES
@ AMDSMI_FW_ID_CP_MES
Compute Processor - Micro Engine Scheduler.
Definition: amdsmi.h:556
AMDSMI_FW_ID_DMCU_ERAM
@ AMDSMI_FW_ID_DMCU_ERAM
Digital Micro Controller Unit - Embedded RAM (memory used by DMU)
Definition: amdsmi.h:532
AMDSMI_FW_ID_RLCV_LX7
@ AMDSMI_FW_ID_RLCV_LX7
Hardware Block RLCV - Subsystem LX7.
Definition: amdsmi.h:580
AMDSMI_FW_ID_RS64_MEC
@ AMDSMI_FW_ID_RS64_MEC
Hardware Block RS64 - Micro Engine Controller.
Definition: amdsmi.h:569
AMDSMI_FW_ID_DFC
@ AMDSMI_FW_ID_DFC
Data Fabric Controler (bandwidth and coherency)
Definition: amdsmi.h:543
AMDSMI_FW_ID_CP_MEC2
@ AMDSMI_FW_ID_CP_MEC2
Compute Processor - Micro Engine Controler 2 (scheduling, managing resources)
Definition: amdsmi.h:518
amdsmi_driver_t
amdsmi_driver_t
Driver.
Definition: amdsmi.h:1826
AMDSMI_MAX_NIC_PORTS
#define AMDSMI_MAX_NIC_PORTS
Maximum size definitions AMDSMI NIC.
Definition: amdsmi.h:2512
AMDSMI_MAX_DATE_STRING_LENGTH
#define AMDSMI_MAX_DATE_STRING_LENGTH
Maximum size definitions for date strings.
Definition: amdsmi.h:1277
AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS
#define AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS
Maximum number of TA (Trusted Application) white list elements.
Definition: amdsmi.h:189
amdsmi_virtualization_mode_t
amdsmi_virtualization_mode_t
Variant placeholder.
Definition: amdsmi.h:605
AMDSMI_VIRTUALIZATION_MODE_BAREMETAL
@ AMDSMI_VIRTUALIZATION_MODE_BAREMETAL
Baremetal Virtualization Mode.
Definition: amdsmi.h:607
AMDSMI_VIRTUALIZATION_MODE_UNKNOWN
@ AMDSMI_VIRTUALIZATION_MODE_UNKNOWN
Unknown Virtualization Mode.
Definition: amdsmi.h:606
AMDSMI_VIRTUALIZATION_MODE_HOST
@ AMDSMI_VIRTUALIZATION_MODE_HOST
Host Virtualization Mode.
Definition: amdsmi.h:608
AMDSMI_VIRTUALIZATION_MODE_GUEST
@ AMDSMI_VIRTUALIZATION_MODE_GUEST
Guest Virtualization Mode.
Definition: amdsmi.h:609
AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH
@ AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH
Passthrough Virtualization Mode.
Definition: amdsmi.h:610
AMDSMI_MAX_STRING_LENGTH
#define AMDSMI_MAX_STRING_LENGTH
Maximum length for string buffers.
Definition: amdsmi.h:163
amdsmi_guest_fw_engine_id_t
amdsmi_guest_fw_engine_id_t
The values of this enum are used to identify the various firmware blocks.
Definition: amdsmi.h:1744
amdsmi_metric_unit_t
amdsmi_metric_unit_t
Metric Unit.
Definition: amdsmi.h:2065
amdsmi_link_status_t
amdsmi_link_status_t
Link Status.
Definition: amdsmi.h:638
amdsmi_ecc_correction_schema_support_t
amdsmi_ecc_correction_schema_support_t
The values of this enum are used to identify supported ecc correction schema.
Definition: amdsmi.h:1732
amdsmi_event_driver_t
amdsmi_event_driver_t
Event Driver.
Definition: amdsmi.h:1333
AMDSMI_MAX_BLACK_LIST_ELEMENTS
#define AMDSMI_MAX_BLACK_LIST_ELEMENTS
Maximum number of black list elements for device access control.
Definition: amdsmi.h:187
amdsmi_memory_partition_type_t
amdsmi_memory_partition_type_t
Memory Partitions.
Definition: amdsmi.h:214
AMDSMI_MEMORY_PARTITION_NPS8
@ AMDSMI_MEMORY_PARTITION_NPS8
Definition: amdsmi.h:224
AMDSMI_MEMORY_PARTITION_NPS1
@ AMDSMI_MEMORY_PARTITION_NPS1
Definition: amdsmi.h:216
AMDSMI_MEMORY_PARTITION_NPS2
@ AMDSMI_MEMORY_PARTITION_NPS2
Definition: amdsmi.h:218
AMDSMI_MEMORY_PARTITION_NPS4
@ AMDSMI_MEMORY_PARTITION_NPS4
Definition: amdsmi.h:221
AMDSMI_MAX_NIC_RDMA_DEV
#define AMDSMI_MAX_NIC_RDMA_DEV
Maximum number of NIC RDMA devices.
Definition: amdsmi.h:2513
amdsmi_event_iov_t
amdsmi_event_iov_t
Event IOV.
Definition: amdsmi.h:1469
amdsmi_guard_state_t
amdsmi_guard_state_t
Guard State.
Definition: amdsmi.h:1840
amdsmi_sched_block_t
amdsmi_sched_block_t
Schedule Block.
Definition: amdsmi.h:1851
amdsmi_nic_link_type_t
amdsmi_nic_link_type_t
NIC Link Types. This enum is used to identify the link type between NIC and GPU processors based on t...
Definition: amdsmi.h:2522
AMDSMI_NIC_LINK_TYPE_X_NUMA
@ AMDSMI_NIC_LINK_TYPE_X_NUMA
two processors connect via different PCIe switches but on different CPUs
Definition: amdsmi.h:2526
AMDSMI_NIC_LINK_TYPE_UNKNOWN
@ AMDSMI_NIC_LINK_TYPE_UNKNOWN
unknown type.
Definition: amdsmi.h:2523
AMDSMI_NIC_LINK_TYPE_NUMA
@ AMDSMI_NIC_LINK_TYPE_NUMA
two processors connect via different PCIe switches but on the same CPU
Definition: amdsmi.h:2525
AMDSMI_NIC_LINK_TYPE_PCIE
@ AMDSMI_NIC_LINK_TYPE_PCIE
two processors connect via same PCIe
Definition: amdsmi.h:2524
amdsmi_processor_handle
void * amdsmi_processor_handle
opaque handler point to underlying implementation
Definition: amdsmi.h:64
amdsmi_event_gpu_t
amdsmi_event_gpu_t
Below are the error subcodes of each category.
Definition: amdsmi.h:1315
amdsmi_cache_property_type_t
amdsmi_cache_property_type_t
cache properties
Definition: amdsmi.h:463
AMDSMI_CACHE_PROPERTY_ENABLED
@ AMDSMI_CACHE_PROPERTY_ENABLED
Cache enabled.
Definition: amdsmi.h:464
AMDSMI_CACHE_PROPERTY_INST_CACHE
@ AMDSMI_CACHE_PROPERTY_INST_CACHE
Instruction cache.
Definition: amdsmi.h:466
AMDSMI_CACHE_PROPERTY_DATA_CACHE
@ AMDSMI_CACHE_PROPERTY_DATA_CACHE
Data cache.
Definition: amdsmi.h:465
AMDSMI_CACHE_PROPERTY_SIMD_CACHE
@ AMDSMI_CACHE_PROPERTY_SIMD_CACHE
Single Instruction, Multiple Data Cache.
Definition: amdsmi.h:468
AMDSMI_CACHE_PROPERTY_CPU_CACHE
@ AMDSMI_CACHE_PROPERTY_CPU_CACHE
CPU cache.
Definition: amdsmi.h:467
amdsmi_event_mmsch_t
amdsmi_event_mmsch_t
Event MM Schedule.
Definition: amdsmi.h:1695
AMDSMI_MAX_DEVICES
#define AMDSMI_MAX_DEVICES
Maximum number of devices supported.
Definition: amdsmi.h:162
amdsmi_status_t
amdsmi_status_t
Error codes returned by amdsmi functions.
Definition: amdsmi.h:93
AMDSMI_STATUS_NOT_INIT
@ AMDSMI_STATUS_NOT_INIT
Processor not initialized.
Definition: amdsmi.h:119
AMDSMI_STATUS_NON_AMD_CPU
@ AMDSMI_STATUS_NON_AMD_CPU
System has different cpu than AMD.
Definition: amdsmi.h:129
AMDSMI_STATUS_DIRECTORY_NOT_FOUND
@ AMDSMI_STATUS_DIRECTORY_NOT_FOUND
Error when a directory is not found, maps to ENOTDIR.
Definition: amdsmi.h:115
AMDSMI_STATUS_INVAL
@ AMDSMI_STATUS_INVAL
Invalid parameters.
Definition: amdsmi.h:96
AMDSMI_STATUS_BUSY
@ AMDSMI_STATUS_BUSY
Processor busy.
Definition: amdsmi.h:117
AMDSMI_STATUS_UNKNOWN_ERROR
@ AMDSMI_STATUS_UNKNOWN_ERROR
An unknown error occurred.
Definition: amdsmi.h:144
AMDSMI_STATUS_DRIVER_NOT_LOADED
@ AMDSMI_STATUS_DRIVER_NOT_LOADED
Processor driver not loaded.
Definition: amdsmi.h:121
AMDSMI_STATUS_FILE_ERROR
@ AMDSMI_STATUS_FILE_ERROR
Problem accessing a file.
Definition: amdsmi.h:109
AMDSMI_STATUS_DRM_ERROR
@ AMDSMI_STATUS_DRM_ERROR
Error when call libdrm.
Definition: amdsmi.h:101
AMDSMI_STATUS_CORRUPTED_EEPROM
@ AMDSMI_STATUS_CORRUPTED_EEPROM
EEPROM is corrupted.
Definition: amdsmi.h:141
AMDSMI_STATUS_ARG_PTR_NULL
@ AMDSMI_STATUS_ARG_PTR_NULL
Parsed argument is invalid.
Definition: amdsmi.h:138
AMDSMI_STATUS_IO
@ AMDSMI_STATUS_IO
I/O Error.
Definition: amdsmi.h:107
AMDSMI_STATUS_NO_HSMP_DRV
@ AMDSMI_STATUS_NO_HSMP_DRV
HSMP driver not found.
Definition: amdsmi.h:132
AMDSMI_STATUS_HSMP_TIMEOUT
@ AMDSMI_STATUS_HSMP_TIMEOUT
HSMP message timed out.
Definition: amdsmi.h:135
AMDSMI_STATUS_NO_DATA
@ AMDSMI_STATUS_NO_DATA
No data was found for a given input.
Definition: amdsmi.h:124
AMDSMI_STATUS_RETRY
@ AMDSMI_STATUS_RETRY
Retry operation.
Definition: amdsmi.h:104
AMDSMI_STATUS_UNEXPECTED_SIZE
@ AMDSMI_STATUS_UNEXPECTED_SIZE
An unexpected amount of data was read.
Definition: amdsmi.h:126
AMDSMI_STATUS_SETTING_UNAVAILABLE
@ AMDSMI_STATUS_SETTING_UNAVAILABLE
Setting is not available.
Definition: amdsmi.h:140
AMDSMI_STATUS_FILE_NOT_FOUND
@ AMDSMI_STATUS_FILE_NOT_FOUND
file or directory not found
Definition: amdsmi.h:137
AMDSMI_STATUS_INTERNAL_EXCEPTION
@ AMDSMI_STATUS_INTERNAL_EXCEPTION
An internal exception was caught.
Definition: amdsmi.h:111
AMDSMI_STATUS_NO_HSMP_SUP
@ AMDSMI_STATUS_NO_HSMP_SUP
HSMP not supported.
Definition: amdsmi.h:133
AMDSMI_STATUS_MAP_ERROR
@ AMDSMI_STATUS_MAP_ERROR
The internal library error did not map to a status code.
Definition: amdsmi.h:143
AMDSMI_STATUS_FAIL_LOAD_SYMBOL
@ AMDSMI_STATUS_FAIL_LOAD_SYMBOL
Fail to load symbol.
Definition: amdsmi.h:100
AMDSMI_STATUS_INSUFFICIENT_SIZE
@ AMDSMI_STATUS_INSUFFICIENT_SIZE
Not enough resources were available for the operation.
Definition: amdsmi.h:125
AMDSMI_STATUS_INIT_ERROR
@ AMDSMI_STATUS_INIT_ERROR
An error occurred when initializing internal data structures.
Definition: amdsmi.h:113
AMDSMI_STATUS_OUT_OF_RESOURCES
@ AMDSMI_STATUS_OUT_OF_RESOURCES
Not enough memory.
Definition: amdsmi.h:110
AMDSMI_STATUS_NO_SLOT
@ AMDSMI_STATUS_NO_SLOT
No more free slot.
Definition: amdsmi.h:120
AMDSMI_STATUS_NO_MSR_DRV
@ AMDSMI_STATUS_NO_MSR_DRV
MSR driver not found.
Definition: amdsmi.h:131
AMDSMI_STATUS_INTERRUPT
@ AMDSMI_STATUS_INTERRUPT
An interrupt occurred during execution of function.
Definition: amdsmi.h:106
AMDSMI_STATUS_SUCCESS
@ AMDSMI_STATUS_SUCCESS
Call succeeded.
Definition: amdsmi.h:94
AMDSMI_STATUS_NO_ENERGY_DRV
@ AMDSMI_STATUS_NO_ENERGY_DRV
Energy driver not found.
Definition: amdsmi.h:130
AMDSMI_STATUS_ADDRESS_FAULT
@ AMDSMI_STATUS_ADDRESS_FAULT
Bad address.
Definition: amdsmi.h:108
AMDSMI_STATUS_MORE_DATA
@ AMDSMI_STATUS_MORE_DATA
There is more data than the buffer size the user passed.
Definition: amdsmi.h:123
AMDSMI_STATUS_NOT_YET_IMPLEMENTED
@ AMDSMI_STATUS_NOT_YET_IMPLEMENTED
Not implemented yet.
Definition: amdsmi.h:98
AMDSMI_STATUS_NO_DRV
@ AMDSMI_STATUS_NO_DRV
No Energy and HSMP driver present.
Definition: amdsmi.h:136
AMDSMI_STATUS_NO_PERM
@ AMDSMI_STATUS_NO_PERM
Permission Denied.
Definition: amdsmi.h:105
AMDSMI_STATUS_NOT_FOUND
@ AMDSMI_STATUS_NOT_FOUND
Processor Not found.
Definition: amdsmi.h:118
AMDSMI_STATUS_FAIL_LOAD_MODULE
@ AMDSMI_STATUS_FAIL_LOAD_MODULE
Fail to load lib.
Definition: amdsmi.h:99
AMDSMI_STATUS_AMDGPU_RESTART_ERR
@ AMDSMI_STATUS_AMDGPU_RESTART_ERR
AMDGPU restart failed.
Definition: amdsmi.h:139
AMDSMI_STATUS_NOT_SUPPORTED
@ AMDSMI_STATUS_NOT_SUPPORTED
Command not supported.
Definition: amdsmi.h:97
AMDSMI_STATUS_UNEXPECTED_DATA
@ AMDSMI_STATUS_UNEXPECTED_DATA
The data read or provided to function is not what was expected.
Definition: amdsmi.h:127
AMDSMI_STATUS_API_FAILED
@ AMDSMI_STATUS_API_FAILED
API call failed.
Definition: amdsmi.h:102
AMDSMI_STATUS_TIMEOUT
@ AMDSMI_STATUS_TIMEOUT
Timeout in API call.
Definition: amdsmi.h:103
AMDSMI_STATUS_NO_HSMP_MSG_SUP
@ AMDSMI_STATUS_NO_HSMP_MSG_SUP
HSMP message/feature not supported.
Definition: amdsmi.h:134
AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS
@ AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS
The provided input is out of allowable or safe range.
Definition: amdsmi.h:112
AMDSMI_STATUS_REFCOUNT_OVERFLOW
@ AMDSMI_STATUS_REFCOUNT_OVERFLOW
An internal reference counter exceeded INT32_MAX.
Definition: amdsmi.h:114
AMDSMI_MAX_NUM_PM_POLICIES
#define AMDSMI_MAX_NUM_PM_POLICIES
Maximum number of power management policies.
Definition: amdsmi.h:153
amdsmi_guest_fw_load_status_t
amdsmi_guest_fw_load_status_t
Guest firmware load status.
Definition: amdsmi.h:1865
amdsmi_xgmi_fb_sharing_mode_t
amdsmi_xgmi_fb_sharing_mode_t
XGMI FB Sharing Mode.
Definition: amdsmi.h:1878
amdsmi_ptl_data_format_t
amdsmi_ptl_data_format_t
PTL (Peak Tops Limiter) data format types These correspond to the hardware data types used in matrix ...
Definition: amdsmi.h:653
AMDSMI_PTL_DATA_FORMAT_INVALID
@ AMDSMI_PTL_DATA_FORMAT_INVALID
Invalid format.
Definition: amdsmi.h:661
AMDSMI_PTL_DATA_FORMAT_I8
@ AMDSMI_PTL_DATA_FORMAT_I8
Integer 8-bit format.
Definition: amdsmi.h:654
AMDSMI_PTL_DATA_FORMAT_F64
@ AMDSMI_PTL_DATA_FORMAT_F64
Float 64-bit format.
Definition: amdsmi.h:658
AMDSMI_PTL_DATA_FORMAT_F8
@ AMDSMI_PTL_DATA_FORMAT_F8
Float 8-bit format.
Definition: amdsmi.h:659
AMDSMI_PTL_DATA_FORMAT_BF16
@ AMDSMI_PTL_DATA_FORMAT_BF16
Brain Float 16-bit format.
Definition: amdsmi.h:656
AMDSMI_PTL_DATA_FORMAT_F32
@ AMDSMI_PTL_DATA_FORMAT_F32
Float 32-bit format.
Definition: amdsmi.h:657
AMDSMI_PTL_DATA_FORMAT_F16
@ AMDSMI_PTL_DATA_FORMAT_F16
Float 16-bit format.
Definition: amdsmi.h:655
AMDSMI_PTL_DATA_FORMAT_VECTOR
@ AMDSMI_PTL_DATA_FORMAT_VECTOR
Vector format.
Definition: amdsmi.h:660
amdsmi_affinity_scope_t
amdsmi_affinity_scope_t
Scope for Numa affinity or Socket affinity.
Definition: amdsmi.h:618
AMDSMI_AFFINITY_SCOPE_NODE
@ AMDSMI_AFFINITY_SCOPE_NODE
Memory affinity as numa node.
Definition: amdsmi.h:619
AMDSMI_AFFINITY_SCOPE_SOCKET
@ AMDSMI_AFFINITY_SCOPE_SOCKET
socket affinity
Definition: amdsmi.h:620
amdsmi_temperature_metric_t
amdsmi_temperature_metric_t
Temperature Metrics. This enum is used to identify various temperature metrics. Corresponding values ...
Definition: amdsmi.h:402
AMDSMI_TEMP_CRITICAL_HYST
@ AMDSMI_TEMP_CRITICAL_HYST
Definition: amdsmi.h:413
AMDSMI_TEMP_CRITICAL
@ AMDSMI_TEMP_CRITICAL
Definition: amdsmi.h:411
AMDSMI_TEMP_OFFSET
@ AMDSMI_TEMP_OFFSET
Definition: amdsmi.h:425
AMDSMI_TEMP_EMERGENCY
@ AMDSMI_TEMP_EMERGENCY
Definition: amdsmi.h:415
AMDSMI_TEMP_LOWEST
@ AMDSMI_TEMP_LOWEST
Historical min temperature.
Definition: amdsmi.h:427
AMDSMI_TEMP_CRIT_MIN
@ AMDSMI_TEMP_CRIT_MIN
Definition: amdsmi.h:421
AMDSMI_TEMP_SHUTDOWN
@ AMDSMI_TEMP_SHUTDOWN
Shutdown temperature.
Definition: amdsmi.h:429
AMDSMI_TEMP_EMERGENCY_HYST
@ AMDSMI_TEMP_EMERGENCY_HYST
Definition: amdsmi.h:419
AMDSMI_TEMP_CURRENT
@ AMDSMI_TEMP_CURRENT
Current temperature.
Definition: amdsmi.h:403
AMDSMI_TEMP_MIN
@ AMDSMI_TEMP_MIN
Min temperature.
Definition: amdsmi.h:406
AMDSMI_TEMP_HIGHEST
@ AMDSMI_TEMP_HIGHEST
Historical max temperature.
Definition: amdsmi.h:428
AMDSMI_TEMP_CRIT_MIN_HYST
@ AMDSMI_TEMP_CRIT_MIN_HYST
Definition: amdsmi.h:423
AMDSMI_TEMP_MIN_HYST
@ AMDSMI_TEMP_MIN_HYST
Definition: amdsmi.h:409
AMDSMI_TEMP_MAX_HYST
@ AMDSMI_TEMP_MAX_HYST
Definition: amdsmi.h:407
AMDSMI_TEMP_MAX
@ AMDSMI_TEMP_MAX
Max temperature.
Definition: amdsmi.h:405
amdsmi_event_category_t
amdsmi_event_category_t
Event Category.
Definition: amdsmi.h:1291
amdsmi_cper_sev_t
amdsmi_cper_sev_t
Cper sev.
Definition: amdsmi.h:1102
AMDSMI_CPER_SEV_NUM
@ AMDSMI_CPER_SEV_NUM
CPER severity Number.
Definition: amdsmi.h:1106
AMDSMI_CPER_SEV_NON_FATAL_CORRECTED
@ AMDSMI_CPER_SEV_NON_FATAL_CORRECTED
CPER Non-Fatal Corrected severity.
Definition: amdsmi.h:1105
AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED
@ AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED
CPER Non-Fatal Uncorrected severity.
Definition: amdsmi.h:1103
AMDSMI_CPER_SEV_FATAL
@ AMDSMI_CPER_SEV_FATAL
CPER Fatal severity.
Definition: amdsmi.h:1104
AMDSMI_CPER_SEV_UNUSED
@ AMDSMI_CPER_SEV_UNUSED
CPER Unused severity.
Definition: amdsmi.h:1107
amdsmi_gpu_block_t
amdsmi_gpu_block_t
This enum is used to identify different GPU blocks.
Definition: amdsmi.h:476
AMDSMI_GPU_BLOCK_XGMI_WAFL
@ AMDSMI_GPU_BLOCK_XGMI_WAFL
XGMI block.
Definition: amdsmi.h:486
AMDSMI_GPU_BLOCK_GFX
@ AMDSMI_GPU_BLOCK_GFX
GFX block.
Definition: amdsmi.h:481
AMDSMI_GPU_BLOCK_IH
@ AMDSMI_GPU_BLOCK_IH
IH block.
Definition: amdsmi.h:496
AMDSMI_GPU_BLOCK_VCN
@ AMDSMI_GPU_BLOCK_VCN
VCN block.
Definition: amdsmi.h:494
AMDSMI_GPU_BLOCK_INVALID
@ AMDSMI_GPU_BLOCK_INVALID
Invalid block.
Definition: amdsmi.h:477
AMDSMI_GPU_BLOCK_MP0
@ AMDSMI_GPU_BLOCK_MP0
MP0 block.
Definition: amdsmi.h:490
AMDSMI_GPU_BLOCK_HDP
@ AMDSMI_GPU_BLOCK_HDP
HDP block.
Definition: amdsmi.h:485
AMDSMI_GPU_BLOCK_MPIO
@ AMDSMI_GPU_BLOCK_MPIO
MPIO block.
Definition: amdsmi.h:497
AMDSMI_GPU_BLOCK_ATHUB
@ AMDSMI_GPU_BLOCK_ATHUB
ATHUB block.
Definition: amdsmi.h:483
AMDSMI_GPU_BLOCK_MP1
@ AMDSMI_GPU_BLOCK_MP1
MP1 block.
Definition: amdsmi.h:491
AMDSMI_GPU_BLOCK_PCIE_BIF
@ AMDSMI_GPU_BLOCK_PCIE_BIF
PCIE_BIF block.
Definition: amdsmi.h:484
AMDSMI_GPU_BLOCK_SDMA
@ AMDSMI_GPU_BLOCK_SDMA
SDMA block.
Definition: amdsmi.h:480
AMDSMI_GPU_BLOCK_JPEG
@ AMDSMI_GPU_BLOCK_JPEG
JPEG block.
Definition: amdsmi.h:495
AMDSMI_GPU_BLOCK_UMC
@ AMDSMI_GPU_BLOCK_UMC
UMC block.
Definition: amdsmi.h:479
AMDSMI_GPU_BLOCK_FUSE
@ AMDSMI_GPU_BLOCK_FUSE
Fuse block.
Definition: amdsmi.h:492
AMDSMI_GPU_BLOCK_DF
@ AMDSMI_GPU_BLOCK_DF
DF block.
Definition: amdsmi.h:487
AMDSMI_GPU_BLOCK_MMHUB
@ AMDSMI_GPU_BLOCK_MMHUB
MMHUB block.
Definition: amdsmi.h:482
AMDSMI_GPU_BLOCK_SMN
@ AMDSMI_GPU_BLOCK_SMN
SMN block.
Definition: amdsmi.h:488
AMDSMI_GPU_BLOCK_SEM
@ AMDSMI_GPU_BLOCK_SEM
SEM block.
Definition: amdsmi.h:489
AMDSMI_GPU_BLOCK_MCA
@ AMDSMI_GPU_BLOCK_MCA
MCA block.
Definition: amdsmi.h:493
amdsmi_metric_name_t
amdsmi_metric_name_t
Metric Name.
Definition: amdsmi.h:1927
amdsmi_vf_sched_state_t
amdsmi_vf_sched_state_t
VF Schedule State.
Definition: amdsmi.h:1796
amdsmi_event_sched_t
amdsmi_event_sched_t
Event Schedule.
Definition: amdsmi.h:1576
amdsmi_driver_model_type_t
amdsmi_driver_model_type_t
The values of this enum are used to identify driver model type.
Definition: amdsmi.h:2128
amdsmi_temperature_type_t
amdsmi_temperature_type_t
This enumeration is used to indicate from which part of the processor a temperature reading should be...
Definition: amdsmi.h:326
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR
OAM X 0.4V HBM D voltage regulator temperature.
Definition: amdsmi.h:346
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3
VDDCR VDD3 voltage regulator temperature.
Definition: amdsmi.h:355
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC
OAM 0-1 HSC temperature.
Definition: amdsmi.h:376
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A
VDDCR SOC A voltage regulator temperature.
Definition: amdsmi.h:356
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC
OAM 6-7 HSC temperature.
Definition: amdsmi.h:379
AMDSMI_TEMPERATURE_TYPE_HBM_2
@ AMDSMI_TEMPERATURE_TYPE_HBM_2
High Bandwidth 2 temperature per stack.
Definition: amdsmi.h:334
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2
OAM X IBC 2 temperature.
Definition: amdsmi.h:343
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR
Retimer 4-5 0.9V voltage regulator temperature.
Definition: amdsmi.h:385
AMDSMI_TEMPERATURE_TYPE_HOTSPOT
@ AMDSMI_TEMPERATURE_TYPE_HOTSPOT
Hottest temperature reported for entire die.
Definition: amdsmi.h:329
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM
VDD 0.85V HBM voltage regulator temperature.
Definition: amdsmi.h:360
AMDSMI_TEMPERATURE_TYPE_HBM_0
@ AMDSMI_TEMPERATURE_TYPE_HBM_0
High Bandwidth 0 temperature per stack.
Definition: amdsmi.h:332
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2
VDDCR VDD2 voltage regulator temperature.
Definition: amdsmi.h:354
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC
UBB IBC temperature.
Definition: amdsmi.h:373
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D
VDDCR 1.1V HBM D voltage regulator temperature.
Definition: amdsmi.h:362
AMDSMI_TEMPERATURE_TYPE_JUNCTION
@ AMDSMI_TEMPERATURE_TYPE_JUNCTION
Synonymous with HOTSPOT.
Definition: amdsmi.h:330
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR
Retimer 4-5-6-7 1.2V voltage regulator temperature.
Definition: amdsmi.h:383
AMDSMI_TEMPERATURE_TYPE_HBM_3
@ AMDSMI_TEMPERATURE_TYPE_HBM_3
High Bandwidth 3 temperature per stack.
Definition: amdsmi.h:335
AMDSMI_TEMPERATURE_TYPE_VRAM
@ AMDSMI_TEMPERATURE_TYPE_VRAM
VRAM temperature on graphics card.
Definition: amdsmi.h:331
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC
OAM 2-3 HSC temperature.
Definition: amdsmi.h:377
AMDSMI_TEMPERATURE_TYPE_EDGE
@ AMDSMI_TEMPERATURE_TYPE_EDGE
Edge temperature.
Definition: amdsmi.h:327
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA
UBB UFPGA temperature.
Definition: amdsmi.h:374
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR
VDD USR voltage regulator temperature.
Definition: amdsmi.h:363
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR
OAM X 0.4V HBM B voltage regulator temperature.
Definition: amdsmi.h:345
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C
VDDCR SOC C voltage regulator temperature.
Definition: amdsmi.h:357
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A
VDDCR SOCIO A voltage regulator temperature.
Definition: amdsmi.h:358
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC
IBC HSC temperature.
Definition: amdsmi.h:390
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC
OAM 4-5 HSC temperature.
Definition: amdsmi.h:378
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR
Retimer 2-3 0.9V voltage regulator temperature.
Definition: amdsmi.h:386
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1
VDDCR VDD1 voltage regulator temperature.
Definition: amdsmi.h:353
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C
VDDCR SOCIO C voltage regulator temperature.
Definition: amdsmi.h:359
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR
Retimer 0-1 0.9V voltage regulator temperature.
Definition: amdsmi.h:384
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0
VDDCR VDD0 voltage regulator temperature.
Definition: amdsmi.h:351
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR
UBB FPGA 0.72V voltage regulator temperature.
Definition: amdsmi.h:380
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR
UBB FPGA 3.3V voltage regulator temperature.
Definition: amdsmi.h:381
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32
VDDIO 1.1V E32 voltage regulator temperature.
Definition: amdsmi.h:364
AMDSMI_TEMPERATURE_TYPE_PLX
@ AMDSMI_TEMPERATURE_TYPE_PLX
PCIe switch temperature.
Definition: amdsmi.h:336
AMDSMI_TEMPERATURE_TYPE_HBM_1
@ AMDSMI_TEMPERATURE_TYPE_HBM_1
High Bandwidth 1 temperature per stack.
Definition: amdsmi.h:333
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7
UBB OAM7 temperature.
Definition: amdsmi.h:372
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR
OAM 0-1-2-3 3.3V voltage regulator temperature.
Definition: amdsmi.h:388
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B
VDDCR 1.1V HBM B voltage regulator temperature.
Definition: amdsmi.h:361
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK
UBB back temperature.
Definition: amdsmi.h:371
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA
UBB FPGA temperature.
Definition: amdsmi.h:369
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X
Retimer X temperature.
Definition: amdsmi.h:340
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC
IBC temperature.
Definition: amdsmi.h:391
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR
OAM X VDD 1.8V voltage regulator temperature.
Definition: amdsmi.h:344
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC
OAM X IBC temperature.
Definition: amdsmi.h:342
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR
Retimer 0-1-2-3 1.2V voltage regulator temperature.
Definition: amdsmi.h:382
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT
UBB front temperature.
Definition: amdsmi.h:370
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR
Retimer 6-7 0.9V voltage regulator temperature.
Definition: amdsmi.h:387
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR
OAM 4-5-6-7 3.3V voltage regulator temperature.
Definition: amdsmi.h:389
AMDSMI_TEMPERATURE_TYPE__MAX
@ AMDSMI_TEMPERATURE_TYPE__MAX
Maximum per GPU temperature type.
Definition: amdsmi.h:393
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1
UBB OAM1 temperature.
Definition: amdsmi.h:375
AMDSMI_MAX_UUID_ELEMENTS
#define AMDSMI_MAX_UUID_ELEMENTS
Maximum number of UUID elements supported.
Definition: amdsmi.h:188
AMDSMI_MAX_NUM_FREQUENCIES
#define AMDSMI_MAX_NUM_FREQUENCIES
Guaranteed maximum possible number of supported frequencies.
Definition: amdsmi.h:192
AMDSMI_MAX_CACHE_TYPES
#define AMDSMI_MAX_CACHE_TYPES
Maximum number of cache types.
Definition: amdsmi.h:164
AMDSMI_DFC_FW_NUMBER_OF_ENTRIES
#define AMDSMI_DFC_FW_NUMBER_OF_ENTRIES
Number of DFC firmware entries supported.
Definition: amdsmi.h:185
AMDSMI_MAX_NUM_NUMA_NODES
#define AMDSMI_MAX_NUM_NUMA_NODES
Maximum number of NUMA nodes.
Definition: amdsmi.h:168
amdsmi_set_gpu_accelerator_partition_profile
amdsmi_status_t amdsmi_set_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, uint32_t profile_index)
Set accelerator partition setting based on profile_index from amdsmi_get_gpu_accelerator_partition_pr...
amdsmi_get_gpu_accelerator_partition_profile_config
amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile_config(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_config_t *profile_config)
Returns gpu accelerator partition caps as currently configured in the system.
amdsmi_get_gpu_accelerator_partition_profile_config_global
amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile_config_global(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_config_global_t *config)
Returns all GPU accelerator partition capabilities which can be configured on the system.
amdsmi_get_gpu_accelerator_partition_profile
amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_t *profile, uint32_t *partition_id)
Returns current gpu accelerator partition cap.
amdsmi_get_fb_layout
amdsmi_status_t amdsmi_get_fb_layout(amdsmi_processor_handle processor_handle, amdsmi_pf_fb_info_t *info)
Returns the framebuffer info for the ASIC.
amdsmi_get_power_cap_info
amdsmi_status_t amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, amdsmi_power_cap_info_t *info)
Returns the power caps as currently configured in the system.
amdsmi_get_pcie_info
amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle, amdsmi_pcie_info_t *info)
Returns the PCIe info for the GPU.
amdsmi_get_gpu_vram_info
amdsmi_status_t amdsmi_get_gpu_vram_info(amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info)
Returns vram info.
amdsmi_get_gpu_board_info
amdsmi_status_t amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info)
Returns the board part number and board information for the requested device.
amdsmi_get_gpu_asic_info
amdsmi_status_t amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info)
Returns the ASIC information for the device.
amdsmi_get_gpu_pci_bandwidth
amdsmi_status_t amdsmi_get_gpu_pci_bandwidth(amdsmi_processor_handle processor_handle, amdsmi_pcie_bandwidth_t *bandwidth)
Get the list of possible PCIe bandwidths that are available. It is not supported on virtual machine g...
amdsmi_get_xgmi_plpd
amdsmi_status_t amdsmi_get_xgmi_plpd(amdsmi_processor_handle processor_handle, amdsmi_dpm_policy_t *xgmi_plpd)
Get the xgmi per-link power down policy parameter for the processor.
amdsmi_set_xgmi_plpd
amdsmi_status_t amdsmi_set_xgmi_plpd(amdsmi_processor_handle processor_handle, uint32_t policy_id)
Set the xgmi per-link power down policy parameter for the processor.
amdsmi_get_soc_pstate
amdsmi_status_t amdsmi_get_soc_pstate(amdsmi_processor_handle processor_handle, amdsmi_dpm_policy_t *policy)
Get the soc pstate policy for the processor.
amdsmi_set_soc_pstate
amdsmi_status_t amdsmi_set_soc_pstate(amdsmi_processor_handle processor_handle, uint32_t policy_id)
Set the soc pstate policy for the processor.
amdsmi_reset_gpu
amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle)
Triggers a chain that resets all GPUs. It is not supported on virtual machine guest.
amdsmi_get_gpu_total_ecc_count
amdsmi_status_t amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec)
Returns the total number of ECC errors (correctable, uncorrectable and deferred) in the given GPU....
amdsmi_get_gpu_ecc_count
amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_gpu_block_t block, amdsmi_error_count_t *ec)
Retrieve the error counts for a GPU block. It is not supported on virtual machine guest.
amdsmi_get_gpu_ecc_enabled
amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle, uint64_t *enabled_blocks)
Retrieve the enabled ECC bit-mask. It is not supported on virtual machine guest.
amdsmi_status_code_to_string
amdsmi_status_t amdsmi_status_code_to_string(amdsmi_status_t status, const char **status_string)
Get a description of a provided AMDSMI error status.
amdsmi_event_destroy
amdsmi_status_t amdsmi_event_destroy(amdsmi_event_set set)
Destroys and frees an event set.
amdsmi_event_read
amdsmi_status_t amdsmi_event_read(amdsmi_event_set set, int64_t timeout_usec, amdsmi_event_entry_t *event)
The call blocks till timeout is expired to copy one event specified by the event set into the user pr...
amdsmi_event_create
amdsmi_status_t amdsmi_event_create(amdsmi_processor_handle *processor_list, uint32_t num_devices, uint64_t event_types, amdsmi_event_set *set)
Allocate a new event set notifier to monitor different types of issues with the GPU running virtualiz...
amdsmi_get_gpu_vbios_info
amdsmi_status_t amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info)
Returns the static information for the vBIOS on the device.
amdsmi_get_fw_info
amdsmi_status_t amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info)
Returns the firmware versions running on the device.
amdsmi_get_dfc_fw_table
amdsmi_status_t amdsmi_get_dfc_fw_table(amdsmi_processor_handle processor_handle, amdsmi_dfc_fw_t *info)
Returns the DFC fw table.
amdsmi_get_fw_error_records
amdsmi_status_t amdsmi_get_fw_error_records(amdsmi_processor_handle processor_handle, amdsmi_fw_error_record_t *records)
Gets firmware error records.
amdsmi_get_power_info
amdsmi_status_t amdsmi_get_power_info(amdsmi_processor_handle processor_handle, amdsmi_power_info_t *info)
Returns the current power and voltage of the GPU.
amdsmi_get_gpu_metrics
amdsmi_status_t amdsmi_get_gpu_metrics(amdsmi_processor_handle processor_handle, uint32_t *metrics_size, amdsmi_metric_t *metrics)
Return metrics information.
amdsmi_get_temp_metric
amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle, amdsmi_temperature_type_t sensor_type, amdsmi_temperature_metric_t metric, int64_t *temperature)
Get the temperature metric value for the specified metric, from the specified temperature sensor on t...
amdsmi_get_gpu_activity
amdsmi_status_t amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info)
Returns the current usage of the GPU engines (GFX, MM and MEM). Each usage is reported as a percentag...
amdsmi_get_clock_info
amdsmi_status_t amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info)
Returns the measurements of the clocks in the GPU for the GFX and multimedia engines and Memory....
amdsmi_is_gpu_power_management_enabled
amdsmi_status_t amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled)
Returns is power management enabled.
amdsmi_get_xgmi_fb_sharing_caps
amdsmi_status_t amdsmi_get_xgmi_fb_sharing_caps(amdsmi_processor_handle processor_handle, amdsmi_xgmi_fb_sharing_caps_t *caps)
Return XGMI capabilities.
amdsmi_set_xgmi_fb_sharing_mode_v2
amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode_v2(amdsmi_processor_handle *processor_list, uint32_t num_processors, amdsmi_xgmi_fb_sharing_mode_t mode)
Set XGMI framebuffer custom sharing mode.
amdsmi_get_xgmi_fb_sharing_mode_info
amdsmi_status_t amdsmi_get_xgmi_fb_sharing_mode_info(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_xgmi_fb_sharing_mode_t mode, uint8_t *fb_sharing)
Return XGMI framebuffer sharing information between two GPUs.
amdsmi_topo_get_numa_node_number
amdsmi_status_t amdsmi_topo_get_numa_node_number(amdsmi_processor_handle processor_handle, uint32_t *numa_node)
Retrieve the NUMA CPU node number for a device.
amdsmi_get_link_topology
amdsmi_status_t amdsmi_get_link_topology(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_link_topology_t *topology_info)
Return link topology information between two connected processors.
amdsmi_get_link_metrics
amdsmi_status_t amdsmi_get_link_metrics(amdsmi_processor_handle processor_handle, amdsmi_link_metrics_t *link_metrics)
Return link metric information.
amdsmi_topo_get_p2p_status
amdsmi_status_t amdsmi_topo_get_p2p_status(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_link_type_t *type, amdsmi_p2p_capability_t *cap)
Retrieve connection type and P2P capabilities between 2 GPUs.
amdsmi_set_xgmi_fb_sharing_mode
amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode(amdsmi_processor_handle processor_handle, amdsmi_xgmi_fb_sharing_mode_t mode)
Set XGMI framebuffer sharing mode.
amdsmi_get_link_topology_nearest
amdsmi_status_t amdsmi_get_link_topology_nearest(amdsmi_processor_handle processor_handle, amdsmi_link_type_t link_type, amdsmi_topology_nearest_t *topology_nearest_info)
Retrieve the set of GPUs that are nearest to a given device at a specific interconnectivity level.
amdsmi_get_guest_data
amdsmi_status_t amdsmi_get_guest_data(amdsmi_vf_handle_t vf_handle, amdsmi_guest_data_t *info)
Returns guest OS information of the queried VF. The fw_info field from the amdsmi_guest_data structur...
amdsmi_get_vf_fw_info
amdsmi_status_t amdsmi_get_vf_fw_info(amdsmi_vf_handle_t vf_handle, amdsmi_fw_info_t *info)
Returns the firmware versions running on a VF. In case the VM is not started on the VF,...
amdsmi_shut_down
amdsmi_status_t amdsmi_shut_down(void)
Shutdown the AMD SMI library.
amdsmi_init
amdsmi_status_t amdsmi_init(uint64_t init_flags)
Initialize the AMD SMI library.
amdsmi_get_gpu_memory_partition_config
amdsmi_status_t amdsmi_get_gpu_memory_partition_config(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_config_t *config)
Returns current gpu memory partition capabilities.
amdsmi_set_gpu_memory_partition_mode
amdsmi_status_t amdsmi_set_gpu_memory_partition_mode(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_type_t mode)
Sets memory partition mode Set memory partition setting based on memory_partition mode from amdsmi_ge...
amdsmi_topo_get_nic_link_type
amdsmi_status_t amdsmi_topo_get_nic_link_type(amdsmi_processor_handle nic_handle, amdsmi_processor_handle processor_handle, amdsmi_nic_link_type_t *type)
Retrieve the link topology type information between nic and processor.
amdsmi_get_nic_rdma_dev_info
amdsmi_status_t amdsmi_get_nic_rdma_dev_info(amdsmi_processor_handle processor_handle, amdsmi_nic_rdma_devices_info_t *info)
Retrieves RDMA devices information for the NIC.
amdsmi_get_nic_rdma_port_statistics
amdsmi_status_t amdsmi_get_nic_rdma_port_statistics(amdsmi_processor_handle processor_handle, uint32_t rdma_port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)
Retrieve RDMA port statistics for the NIC.
amdsmi_get_nic_port_info
amdsmi_status_t amdsmi_get_nic_port_info(amdsmi_processor_handle processor_handle, amdsmi_nic_port_info_t *info)
Retrieves PORT information for the NIC.
amdsmi_get_nic_vendor_statistics
amdsmi_status_t amdsmi_get_nic_vendor_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)
Retrieve vendor specific statistics for the NIC port.
amdsmi_get_nic_port_statistics
amdsmi_status_t amdsmi_get_nic_port_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)
Retrieve PORT statistics for the specified NIC port.
amdsmi_get_nic_driver_info
amdsmi_status_t amdsmi_get_nic_driver_info(amdsmi_processor_handle processor_handle, amdsmi_nic_driver_info_t *info)
Retrieves information about the NIC driver.
amdsmi_get_nic_bus_info
amdsmi_status_t amdsmi_get_nic_bus_info(amdsmi_processor_handle processor_handle, amdsmi_nic_bus_info_t *info)
Retrieves BUS information for the NIC.
amdsmi_get_nic_asic_info
amdsmi_status_t amdsmi_get_nic_asic_info(amdsmi_processor_handle processor_handle, amdsmi_nic_asic_info_t *info)
Retrieves ASIC information for the NIC.
amdsmi_get_nic_numa_info
amdsmi_status_t amdsmi_get_nic_numa_info(amdsmi_processor_handle processor_handle, amdsmi_nic_numa_info_t *info)
Retrieves NUMA information for the NIC.
amdsmi_get_npm_info
amdsmi_status_t amdsmi_get_npm_info(amdsmi_node_handle node_handle, amdsmi_npm_info_t *info)
Retrieves node power management (NPM) status and power limit for the specified node.
amdsmi_get_gpu_ptl_state
amdsmi_status_t amdsmi_get_gpu_ptl_state(amdsmi_processor_handle processor_handle, bool *enabled)
Get PTL enable/disable state.
amdsmi_set_gpu_ptl_state
amdsmi_status_t amdsmi_set_gpu_ptl_state(amdsmi_processor_handle processor_handle, bool enable)
Set PTL enable/disable state.
amdsmi_set_gpu_ptl_formats
amdsmi_status_t amdsmi_set_gpu_ptl_formats(amdsmi_processor_handle processor_handle, amdsmi_ptl_data_format_t data_format1, amdsmi_ptl_data_format_t data_format2)
Set PTL with specified preferred data formats.
amdsmi_get_gpu_ptl_formats
amdsmi_status_t amdsmi_get_gpu_ptl_formats(amdsmi_processor_handle processor_handle, amdsmi_ptl_data_format_t *data_format1, amdsmi_ptl_data_format_t *data_format2)
Get PTL (Peak Tops Limiter) formats for the processor.
amdsmi_get_gpu_cache_info
amdsmi_status_t amdsmi_get_gpu_cache_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info)
Returns gpu cache info.
amdsmi_set_power_cap
amdsmi_status_t amdsmi_set_power_cap(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, uint64_t cap)
Set the maximum gpu power cap value. It is not supported on virtual machine guest.
amdsmi_get_supported_power_cap
amdsmi_status_t amdsmi_get_supported_power_cap(amdsmi_processor_handle processor_handle, uint32_t *sensor_count, uint32_t *sensor_inds, amdsmi_power_cap_type_t *sensor_types)
Query the supported power cap sensors and their types for a device.
amdsmi_get_processor_handles
amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle, uint32_t *processor_count, amdsmi_processor_handle *processor_handles)
Get the list of the processor handles associated to a socket.
amdsmi_get_index_from_processor_handle
amdsmi_status_t amdsmi_get_index_from_processor_handle(amdsmi_processor_handle processor_handle, uint32_t *processor_index)
Returns the index of the given processor handle.
amdsmi_get_gpu_device_uuid
amdsmi_status_t amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid)
Returns the UUID of the device.
amdsmi_get_processor_type
amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle, processor_type_t *processor_type)
Get the processor type of the processor_handle.
amdsmi_get_socket_info
amdsmi_status_t amdsmi_get_socket_info(amdsmi_socket_handle socket_handle, size_t len, char *name)
Get information about the given socket.
amdsmi_get_node_handle
amdsmi_status_t amdsmi_get_node_handle(amdsmi_processor_handle processor_handle, amdsmi_node_handle *node_handle)
Get the node handle associated with processor handle.
amdsmi_get_gpu_virtualization_mode
amdsmi_status_t amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle, amdsmi_virtualization_mode_t *mode)
Returns the virtualization mode for the target device.
amdsmi_get_nic_processor_handles
amdsmi_status_t amdsmi_get_nic_processor_handles(amdsmi_socket_handle socket_handle, uint32_t *processor_count, amdsmi_processor_handle *processor_handles)
Get the list of the NIC processor handles associated to a socket.
amdsmi_get_nic_device_bdf
amdsmi_status_t amdsmi_get_nic_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given NIC device.
amdsmi_get_processor_handle_from_uuid
amdsmi_status_t amdsmi_get_processor_handle_from_uuid(const char *uuid, amdsmi_processor_handle *processor_handle)
Returns the processor handle from the given UUID.
amdsmi_get_socket_handles
amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count, amdsmi_socket_handle *socket_handles)
Get the list of socket handles in the system.
amdsmi_get_vf_bdf
amdsmi_status_t amdsmi_get_vf_bdf(amdsmi_vf_handle_t vf_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given device (VF).
amdsmi_get_vf_handle_from_bdf
amdsmi_status_t amdsmi_get_vf_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_vf_handle_t *vf_handle)
Returns VF handle from the given BDF.
amdsmi_get_processor_handle_from_bdf
amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_processor_handle *processor_handle)
Get processor handle with the matching bdf.
amdsmi_get_vf_handle_from_vf_index
amdsmi_status_t amdsmi_get_vf_handle_from_vf_index(amdsmi_processor_handle processor_handle, uint32_t fcn_idx, amdsmi_vf_handle_t *vf_handle)
Returns the handle of a virtual function given its index.
amdsmi_get_processor_handles_by_type
amdsmi_status_t amdsmi_get_processor_handles_by_type(amdsmi_socket_handle socket_handle, processor_type_t processor_type, amdsmi_processor_handle *processor_handles, uint32_t *processor_count)
Returns a list of processor handles of the specified type in the system.
amdsmi_get_vf_uuid
amdsmi_status_t amdsmi_get_vf_uuid(amdsmi_vf_handle_t processor_handle, unsigned int *uuid_length, char *uuid)
Returns the UUID of the VF.
amdsmi_get_gpu_device_bdf
amdsmi_status_t amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given GPU device.
amdsmi_get_processor_bdf
amdsmi_status_t amdsmi_get_processor_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given device.
amdsmi_get_vf_handle_from_uuid
amdsmi_status_t amdsmi_get_vf_handle_from_uuid(const char *uuid, amdsmi_vf_handle_t *vf_handle)
Returns the handle of a virtual function from the given UUID.
amdsmi_get_cpu_affinity_with_scope
amdsmi_status_t amdsmi_get_cpu_affinity_with_scope(amdsmi_processor_handle processor_handle, uint32_t cpu_set_size, uint64_t *cpu_set, amdsmi_affinity_scope_t scope)
Retrieves an array of uint64_t (sized to cpu_set_size) of bitmasks with the affinity within numa node...
amdsmi_get_processor_handle_from_index
amdsmi_status_t amdsmi_get_processor_handle_from_index(uint32_t processor_index, amdsmi_processor_handle *processor_handle)
Returns the processor handle from the given processor index.
amdsmi_get_gpu_ras_policy_info
amdsmi_status_t amdsmi_get_gpu_ras_policy_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_ras_policy_info_t *info)
Get the RAS policy info for a device.
amdsmi_get_afids_from_cper
amdsmi_status_t amdsmi_get_afids_from_cper(char *cper_buffer, uint32_t buf_size, uint64_t *afids, uint32_t *num_afids)
Get the AFIDs from CPER buffer.
amdsmi_get_bad_page_threshold
amdsmi_status_t amdsmi_get_bad_page_threshold(amdsmi_processor_handle processor_handle, uint32_t *threshold)
Get the bad page threshold for a device.
amdsmi_get_gpu_cper_entries
amdsmi_status_t amdsmi_get_gpu_cper_entries(amdsmi_processor_handle processor_handle, uint32_t severity_mask, char *cper_data, uint64_t *buf_size, amdsmi_cper_hdr_t **cper_hdrs, uint64_t *entry_count, uint64_t *cursor)
Retrieve CPER entries cached in the driver.
amdsmi_get_gpu_ras_feature_info
amdsmi_status_t amdsmi_get_gpu_ras_feature_info(amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature)
Returns RAS features info.
amdsmi_get_gpu_bad_page_info
amdsmi_status_t amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *bad_page_size, amdsmi_eeprom_table_record_t *bad_pages)
Returns the bad page info.
amdsmi_get_gpu_driver_info
amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info)
Returns the driver version information.
amdsmi_get_gpu_driver_model
amdsmi_status_t amdsmi_get_gpu_driver_model(amdsmi_processor_handle processor_handle, amdsmi_driver_model_type_t *model)
Returns the driver model information.
amdsmi_get_vf_info
amdsmi_status_t amdsmi_get_vf_info(amdsmi_vf_handle_t vf_handle, amdsmi_vf_info_t *config)
Returns the configuration structure for a VF.
amdsmi_get_vf_data
amdsmi_status_t amdsmi_get_vf_data(amdsmi_vf_handle_t vf_handle, amdsmi_vf_data_t *info)
Returns the data structure for a VF.
amdsmi_get_vf_partition_info
amdsmi_status_t amdsmi_get_vf_partition_info(amdsmi_processor_handle processor_handle, unsigned int vf_buffer_num, amdsmi_partition_info_t *info)
Returns the current framebuffer partitioning structure as currently configured by the driver.
amdsmi_get_num_vf
amdsmi_status_t amdsmi_get_num_vf(amdsmi_processor_handle processor_handle, uint32_t *num_vf_enabled, uint32_t *num_vf_supported)
Returns the number of VFs enabled by gpuv in the ASIC.
amdsmi_get_partition_profile_info
amdsmi_status_t amdsmi_get_partition_profile_info(amdsmi_processor_handle processor_handle, amdsmi_profile_info_t *profile_info)
Return the list of supported profiles on the given GPU device.
amdsmi_clear_vf_fb
amdsmi_status_t amdsmi_clear_vf_fb(amdsmi_vf_handle_t vf_handle)
Clear the framebuffer of a VF. If trying to clear the framebuffer of an active function,...
amdsmi_set_num_vf
amdsmi_status_t amdsmi_set_num_vf(amdsmi_processor_handle processor_handle, uint32_t num_vf)
Enable a given number of VF.
amdsmi_get_lib_version
amdsmi_status_t amdsmi_get_lib_version(amdsmi_version_t *version)
Get the build version information for the currently running build of AMDSMI.
amdsmi_accelerator_partition_profile_config_global_t
Definition: amdsmi.h:2498
amdsmi_accelerator_partition_profile_config_global_t::num_profiles
uint32_t num_profiles
The length of profiles array.
Definition: amdsmi.h:2499
amdsmi_accelerator_partition_profile_config_global_t::default_profile_index
uint32_t default_profile_index
The index of the default profile in the profiles array.
Definition: amdsmi.h:2502
amdsmi_accelerator_partition_profile_config_t
Accelerator Partition Profile Configurations.
Definition: amdsmi.h:974
amdsmi_accelerator_partition_profile_config_t::default_profile_index
uint32_t default_profile_index
The index of the default profile in the profiles array.
Definition: amdsmi.h:978
amdsmi_accelerator_partition_profile_config_t::num_profiles
uint32_t num_profiles
The length of profiles array.
Definition: amdsmi.h:975
amdsmi_accelerator_partition_profile_global_t
Definition: amdsmi.h:2492
amdsmi_accelerator_partition_profile_global_t::vf_mode
uint32_t vf_mode
Bitmask of VF modes (see amdsmi_vf_mode_t)
Definition: amdsmi.h:2494
amdsmi_accelerator_partition_profile_t
Accelerator Partition Resource Profile.
Definition: amdsmi.h:945
amdsmi_accelerator_partition_profile_t::profile_index
uint32_t profile_index
Index in the profiles array in amdsmi_accelerator_partition_profile_t.
Definition: amdsmi.h:949
amdsmi_accelerator_partition_profile_t::num_partitions
uint32_t num_partitions
On MI300X: SPX=>1, DPX=>2, QPX=>4, CPX=>8; length of resources.
Definition: amdsmi.h:947
amdsmi_accelerator_partition_profile_t::memory_caps
amdsmi_nps_caps_t memory_caps
Possible memory partition capabilities.
Definition: amdsmi.h:948
amdsmi_accelerator_partition_profile_t::profile_type
amdsmi_accelerator_partition_type_t profile_type
SPX, DPX, QPX, CPX and so on.
Definition: amdsmi.h:946
amdsmi_accelerator_partition_profile_t::num_resources
uint32_t num_resources
length of index_of_resources_profile
Definition: amdsmi.h:950
amdsmi_accelerator_partition_resource_profile_t
Accelerator Partition Resources. This struct is used to identify various partition resource profiles.
Definition: amdsmi.h:961
amdsmi_accelerator_partition_resource_profile_t::partition_resource
uint32_t partition_resource
Resources a partition can use, which may be shared.
Definition: amdsmi.h:964
amdsmi_accelerator_partition_resource_profile_t::num_partitions_share_resource
uint32_t num_partitions_share_resource
If it is greater than 1, then resource is shared.
Definition: amdsmi.h:965
amdsmi_asic_info_t
ASIC Information.
Definition: amdsmi.h:804
amdsmi_asic_info_t::target_graphics_version
uint64_t target_graphics_version
0xFFFFFFFFFFFFFFFF if not supported
Definition: amdsmi.h:814
amdsmi_asic_info_t::vendor_id
uint32_t vendor_id
Use 32 bit to be compatible with other platform.
Definition: amdsmi.h:806
amdsmi_asic_info_t::device_id
uint64_t device_id
The device ID of a GPU.
Definition: amdsmi.h:809
amdsmi_asic_info_t::oam_id
uint32_t oam_id
Corresponds to socket number, 0xFFFFFFFF if not supported.
Definition: amdsmi.h:812
amdsmi_asic_info_t::num_of_compute_units
uint32_t num_of_compute_units
0xFFFFFFFF if not supported
Definition: amdsmi.h:813
amdsmi_asic_info_t::subvendor_id
uint32_t subvendor_id
The subsystem vendor ID.
Definition: amdsmi.h:808
amdsmi_asic_info_t::subsystem_id
uint32_t subsystem_id
The subsystem ID.
Definition: amdsmi.h:815
amdsmi_asic_info_t::flags
uint64_t flags
Chip flags.
Definition: amdsmi.h:816
amdsmi_asic_info_t::rev_id
uint32_t rev_id
The revision ID of a GPU.
Definition: amdsmi.h:810
amdsmi_bdf_t::bdf_
Definition: amdsmi.h:670
amdsmi_board_info_t
Board Information.
Definition: amdsmi.h:988
amdsmi_clk_info_t
Clock Information.
Definition: amdsmi.h:885
amdsmi_clk_info_t::clk
uint32_t clk
In MHz.
Definition: amdsmi.h:886
amdsmi_clk_info_t::clk_locked
uint8_t clk_locked
True/False.
Definition: amdsmi.h:889
amdsmi_clk_info_t::clk_deep_sleep
uint8_t clk_deep_sleep
True/False.
Definition: amdsmi.h:890
amdsmi_clk_info_t::min_clk
uint32_t min_clk
In MHz.
Definition: amdsmi.h:887
amdsmi_clk_info_t::max_clk
uint32_t max_clk
In MHz.
Definition: amdsmi.h:888
amdsmi_cper_guid_t
Cper.
Definition: amdsmi.h:1162
amdsmi_cper_hdr_t
Definition: amdsmi.h:1187
amdsmi_cper_hdr_t::notify_type
amdsmi_cper_guid_t notify_type
CMC, MCE, can use amdsmi_cper_notifiy_type_t to decode.
Definition: amdsmi.h:1199
amdsmi_cper_hdr_t::persistence_info
uint64_t persistence_info
Reserved.
Definition: amdsmi.h:1202
amdsmi_cper_hdr_t::signature_end
uint32_t signature_end
0xFFFFFFFF
Definition: amdsmi.h:1190
amdsmi_cper_hdr_t::flags
uint32_t flags
Reserved.
Definition: amdsmi.h:1201
amdsmi_cper_hdr_t::partition_id
amdsmi_cper_guid_t partition_id
Reserved.
Definition: amdsmi.h:1197
amdsmi_cper_hdr_t::record_length
uint32_t record_length
Total size of CPER Entry.
Definition: amdsmi.h:1194
amdsmi_cper_timestamp_t
Definition: amdsmi.h:1166
amdsmi_cper_valid_bits_t::valid_bits_
Definition: amdsmi.h:1178
amdsmi_dfc_fw_data_t
DFC Firmware Data.
Definition: amdsmi.h:2353
amdsmi_dfc_fw_data_t::customer_ordinal
uint32_t customer_ordinal
only used in driver version on NV32+
Definition: amdsmi.h:2356
amdsmi_dfc_fw_header_t
DFC Firmware Header.
Definition: amdsmi.h:2321
amdsmi_dfc_fw_t
DFC Firmware.
Definition: amdsmi.h:2370
amdsmi_dfc_fw_ta_uuid_t
DFC Firmware TA UUID.
Definition: amdsmi.h:2344
amdsmi_dfc_fw_white_list_t
DFC Firmware White List.
Definition: amdsmi.h:2334
amdsmi_dpm_policy_entry_t
The dpm policy.
Definition: amdsmi.h:1059
amdsmi_dpm_policy_t
DPM Policy.
Definition: amdsmi.h:1071
amdsmi_dpm_policy_t::num_supported
uint32_t num_supported
The number of supported policies.
Definition: amdsmi.h:1072
amdsmi_dpm_policy_t::current
uint32_t current
The current policy index.
Definition: amdsmi.h:1073
amdsmi_driver_info_t
Driver Information.
Definition: amdsmi.h:843
amdsmi_eeprom_table_record_t
Structure representing an EEPROM table record for tracking memory errors.
Definition: amdsmi.h:2384
amdsmi_eeprom_table_record_t::retired_page
uint64_t retired_page
Bad page frame address.
Definition: amdsmi.h:2385
amdsmi_engine_usage_t
Engine Usage amdsmi_engine_usage_t: This structure holds common GPU activity values seen in both BM o...
Definition: amdsmi.h:873
amdsmi_engine_usage_t::gfx_activity
uint32_t gfx_activity
In %.
Definition: amdsmi.h:874
amdsmi_engine_usage_t::umc_activity
uint32_t umc_activity
In %.
Definition: amdsmi.h:875
amdsmi_engine_usage_t::mm_activity
uint32_t mm_activity
In %.
Definition: amdsmi.h:876
amdsmi_error_count_t
This structure holds error counts.
Definition: amdsmi.h:899
amdsmi_error_count_t::uncorrectable_count
uint64_t uncorrectable_count
Accumulated uncorrectable errors.
Definition: amdsmi.h:901
amdsmi_error_count_t::correctable_count
uint64_t correctable_count
Accumulated correctable errors.
Definition: amdsmi.h:900
amdsmi_error_count_t::deferred_count
uint64_t deferred_count
Accumulated deferred errors.
Definition: amdsmi.h:902
amdsmi_event_entry_t
Event Entry.
Definition: amdsmi.h:2149
amdsmi_event_entry_t::timestamp
uint64_t timestamp
UTC microseconds.
Definition: amdsmi.h:2152
amdsmi_frequencies_t
This structure holds information about clock frequencies.
Definition: amdsmi.h:719
amdsmi_frequencies_t::current
uint32_t current
The current frequency index in MHz.
Definition: amdsmi.h:722
amdsmi_frequencies_t::num_supported
uint32_t num_supported
The number of supported frequencies.
Definition: amdsmi.h:721
amdsmi_frequencies_t::has_deep_sleep
bool has_deep_sleep
Deep Sleep frequency is only supported by some GPUs.
Definition: amdsmi.h:720
amdsmi_fw_error_record_t
Firmware Error Record.
Definition: amdsmi.h:2415
amdsmi_fw_info_t::fw_info_list_
Definition: amdsmi.h:1046
amdsmi_fw_info_t
Firmware Information.
Definition: amdsmi.h:1044
amdsmi_fw_load_error_record_t
Firmware Load Error Record.
Definition: amdsmi.h:2402
amdsmi_fw_load_error_record_t::timestamp
uint64_t timestamp
UTC microseconds.
Definition: amdsmi.h:2403
amdsmi_fw_load_error_record_t::status
uint16_t status
amdsmi_guest_fw_load_status
Definition: amdsmi.h:2406
amdsmi_gpu_cache_info_t::cache_
Definition: amdsmi.h:1028
amdsmi_gpu_cache_info_t::cache_::num_cache_instance
uint32_t num_cache_instance
total number of instance of this cache type
Definition: amdsmi.h:1033
amdsmi_gpu_cache_info_t::cache_::cache_size
uint32_t cache_size
In KB.
Definition: amdsmi.h:1030
amdsmi_gpu_cache_info_t::cache_::max_num_cu_shared
uint32_t max_num_cu_shared
Indicates how many Compute Units share this cache instance.
Definition: amdsmi.h:1032
amdsmi_gpu_cache_info_t::cache_::cache_properties
uint32_t cache_properties
amdsmi_cache_property_type_t which is a bitmask
Definition: amdsmi.h:1029
amdsmi_gpu_cache_info_t
GPU Cache Information.
Definition: amdsmi.h:1026
amdsmi_gpu_ras_policy_info_t
Ras policy info structure for storing version and different ras policy version structures.
Definition: amdsmi.h:1146
amdsmi_gpu_ras_policy_v4_0_t
Ras policy v4.0.
Definition: amdsmi.h:1135
amdsmi_gpu_ras_policy_v4_0_t::dram_critical_region_threshold
uint16_t dram_critical_region_threshold
Critical region UCE threshold.
Definition: amdsmi.h:1137
amdsmi_gpu_ras_policy_v4_0_t::dram_non_critical_region_threshold
uint16_t dram_non_critical_region_threshold
Non-critical region UCE threshold.
Definition: amdsmi.h:1136
amdsmi_guard_info_t
Guard Information.
Definition: amdsmi.h:2214
amdsmi_guest_data_t
Guest Data.
Definition: amdsmi.h:2310
amdsmi_guest_data_t::fb_usage
uint32_t fb_usage
guest framebuffer usage in MB
Definition: amdsmi.h:2312
amdsmi_handshake_t
Handshake.
Definition: amdsmi.h:2168
amdsmi_link_metrics_t::_links
Definition: amdsmi.h:748
amdsmi_link_metrics_t::_links::write
uint64_t write
total data transfered for each link in KB
Definition: amdsmi.h:754
amdsmi_link_metrics_t::_links::link_status
amdsmi_link_status_t link_status
HW status of the link.
Definition: amdsmi.h:755
amdsmi_link_metrics_t::_links::read
uint64_t read
total data received for each link in KB
Definition: amdsmi.h:753
amdsmi_link_metrics_t::_links::bit_rate
uint32_t bit_rate
current link speed in Gb/s
Definition: amdsmi.h:750
amdsmi_link_metrics_t::_links::link_type
amdsmi_link_type_t link_type
type of the link
Definition: amdsmi.h:752
amdsmi_link_metrics_t::_links::bdf
amdsmi_bdf_t bdf
bdf of the destination gpu
Definition: amdsmi.h:749
amdsmi_link_metrics_t::_links::max_bandwidth
uint32_t max_bandwidth
max bandwidth of the link in Gb/s
Definition: amdsmi.h:751
amdsmi_link_metrics_t
Link Metrics.
Definition: amdsmi.h:746
amdsmi_link_metrics_t::num_links
uint32_t num_links
number of links
Definition: amdsmi.h:747
amdsmi_link_topology_t
Link Topology.
Definition: amdsmi.h:2426
amdsmi_link_topology_t::weight
uint64_t weight
link weight
Definition: amdsmi.h:2427
amdsmi_link_topology_t::link_type
amdsmi_link_type_t link_type
type of the link
Definition: amdsmi.h:2429
amdsmi_link_topology_t::num_hops
uint8_t num_hops
number of hops
Definition: amdsmi.h:2430
amdsmi_link_topology_t::link_status
amdsmi_link_status_t link_status
HW status of the link.
Definition: amdsmi.h:2428
amdsmi_link_topology_t::fb_sharing
uint8_t fb_sharing
framebuffer sharing flag
Definition: amdsmi.h:2431
amdsmi_memory_partition_config_t::numa_range_
Definition: amdsmi.h:932
amdsmi_memory_partition_config_t
Memory Partition Configuration. This structure is used to identify various memory partition configura...
Definition: amdsmi.h:928
amdsmi_metric_t
Metric.
Definition: amdsmi.h:2468
amdsmi_metric_t::res_group
amdsmi_metric_res_group_t res_group
Resource group this metric belongs to.
Definition: amdsmi.h:2475
amdsmi_metric_t::res_subgroup
amdsmi_metric_res_subgroup_t res_subgroup
Resource subgroup this metric belongs to.
Definition: amdsmi.h:2476
amdsmi_metric_t::flags
uint32_t flags
used to determine type of the metric (amdsmi_metric_type_t)
Definition: amdsmi.h:2472
amdsmi_metric_t::res_instance
uint32_t res_instance
Resource instance this metric belongs to.
Definition: amdsmi.h:2477
amdsmi_metric_t::vf_mask
uint32_t vf_mask
Mask of all active VFs + PF that this metric applies to.
Definition: amdsmi.h:2473
amdsmi_nic_asic_info_t
NIC asic information.
Definition: amdsmi.h:2546
amdsmi_nic_bus_info_t
NIC bus information.
Definition: amdsmi.h:2564
amdsmi_nic_bus_info_t::max_pcie_speed
uint32_t max_pcie_speed
maximum PCIe speed in GT/s
Definition: amdsmi.h:2567
amdsmi_nic_driver_info_t
NIC driver information.
Definition: amdsmi.h:2658
amdsmi_nic_fw_info_t
NIC firmware information collection.
Definition: amdsmi.h:2597
amdsmi_nic_fw_t
NIC firmware information.
Definition: amdsmi.h:2587
amdsmi_nic_numa_info_t
NIC NUMA information.
Definition: amdsmi.h:2577
amdsmi_nic_port_info_t
NIC port information collection.
Definition: amdsmi.h:2648
amdsmi_nic_port_t
NIC port information.
Definition: amdsmi.h:2624
amdsmi_nic_port_t::active_fec
uint32_t active_fec
Active FEC modes bitmask (see about FEC modes in the description)
Definition: amdsmi.h:2636
amdsmi_nic_rdma_dev_info_t
NIC RDMA device information.
Definition: amdsmi.h:2681
amdsmi_nic_rdma_devices_info_t
NIC RDMA devices information collection.
Definition: amdsmi.h:2696
amdsmi_nic_rdma_port_info_t
NIC RDMA port information.
Definition: amdsmi.h:2668
amdsmi_nic_stat_t
Structure for NIC statistic name-value pairs.
Definition: amdsmi.h:2536
amdsmi_npm_info_t
NPM info.
Definition: amdsmi.h:1015
amdsmi_npm_info_t::status
amdsmi_npm_status_t status
NPM status (enabled/disabled).
Definition: amdsmi.h:1016
amdsmi_npm_info_t::limit
uint64_t limit
Node-level power limit in Watts.
Definition: amdsmi.h:1017
amdsmi_nps_caps_t::nps_flags_
Definition: amdsmi.h:912
amdsmi_nps_caps_t::nps_flags_::nps8_cap
uint32_t nps8_cap
bool 1 = true; 0 = false
Definition: amdsmi.h:916
amdsmi_nps_caps_t::nps_flags_::nps4_cap
uint32_t nps4_cap
bool 1 = true; 0 = false
Definition: amdsmi.h:915
amdsmi_nps_caps_t::nps_flags_::nps2_cap
uint32_t nps2_cap
bool 1 = true; 0 = false
Definition: amdsmi.h:914
amdsmi_nps_caps_t::nps_flags_::nps1_cap
uint32_t nps1_cap
bool 1 = true; 0 = false
Definition: amdsmi.h:913
amdsmi_p2p_capability_t
IO Link P2P Capability.
Definition: amdsmi.h:1002
amdsmi_p2p_capability_t::is_iolink_atomics_64bit
uint8_t is_iolink_atomics_64bit
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:1005
amdsmi_p2p_capability_t::is_iolink_atomics_32bit
uint8_t is_iolink_atomics_32bit
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:1004
amdsmi_p2p_capability_t::is_iolink_bi_directional
uint8_t is_iolink_bi_directional
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:1007
amdsmi_p2p_capability_t::is_iolink_coherent
uint8_t is_iolink_coherent
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:1003
amdsmi_p2p_capability_t::is_iolink_dma
uint8_t is_iolink_dma
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:1006
amdsmi_partition_info_t
Partition Information.
Definition: amdsmi.h:2203
amdsmi_pcie_bandwidth_t
This structure holds information about the possible PCIe bandwidths. Specifically,...
Definition: amdsmi.h:736
amdsmi_pcie_bandwidth_t::transfer_rate
amdsmi_frequencies_t transfer_rate
Transfer rates (T/s) that are possible.
Definition: amdsmi.h:737
amdsmi_pcie_info_t::pcie_metric_
Definition: amdsmi.h:699
amdsmi_pcie_info_t::pcie_metric_::pcie_nak_received_count
uint64_t pcie_nak_received_count
total number of NAKs issued on the PCIe link by the receiver
Definition: amdsmi.h:707
amdsmi_pcie_info_t::pcie_metric_::pcie_replay_count
uint64_t pcie_replay_count
total number of the replays issued on the PCIe link
Definition: amdsmi.h:703
amdsmi_pcie_info_t::pcie_metric_::pcie_width
uint16_t pcie_width
current PCIe width
Definition: amdsmi.h:700
amdsmi_pcie_info_t::pcie_metric_::pcie_speed
uint32_t pcie_speed
current PCIe speed in MT/s
Definition: amdsmi.h:701
amdsmi_pcie_info_t::pcie_metric_::pcie_bandwidth
uint32_t pcie_bandwidth
current PCIe bandwidth in Mb/s
Definition: amdsmi.h:702
amdsmi_pcie_info_t::pcie_metric_::pcie_l0_to_recovery_count
uint64_t pcie_l0_to_recovery_count
total number of times the PCIe link transitioned from L0 to the recovery state
Definition: amdsmi.h:704
amdsmi_pcie_info_t::pcie_metric_::pcie_nak_sent_count
uint64_t pcie_nak_sent_count
total number of NAKs issued on the PCIe link by the device
Definition: amdsmi.h:706
amdsmi_pcie_info_t::pcie_metric_::pcie_replay_roll_over_count
uint64_t pcie_replay_roll_over_count
total number of replay rollovers issued on the PCIe link
Definition: amdsmi.h:705
amdsmi_pcie_info_t::pcie_metric_::pcie_lc_perf_other_end_recovery_count
uint32_t pcie_lc_perf_other_end_recovery_count
PCIe other end recovery counter.
Definition: amdsmi.h:708
amdsmi_pcie_info_t::pcie_static_
Definition: amdsmi.h:691
amdsmi_pcie_info_t::pcie_static_::max_pcie_width
uint16_t max_pcie_width
maximum number of PCIe lanes
Definition: amdsmi.h:692
amdsmi_pcie_info_t::pcie_static_::max_pcie_interface_version
uint32_t max_pcie_interface_version
maximum PCIe link generation
Definition: amdsmi.h:696
amdsmi_pcie_info_t::pcie_static_::slot_type
amdsmi_card_form_factor_t slot_type
card form factor
Definition: amdsmi.h:695
amdsmi_pcie_info_t::pcie_static_::max_pcie_speed
uint32_t max_pcie_speed
maximum PCIe speed in GT/s
Definition: amdsmi.h:693
amdsmi_pcie_info_t::pcie_static_::pcie_interface_version
uint32_t pcie_interface_version
PCIe interface version.
Definition: amdsmi.h:694
amdsmi_pcie_info_t
pcie information
Definition: amdsmi.h:690
amdsmi_pf_fb_info_t
PF FB Information.
Definition: amdsmi.h:2177
amdsmi_pf_fb_info_t::pf_fb_reserved
uint32_t pf_fb_reserved
Total fb consumed by PF.
Definition: amdsmi.h:2179
amdsmi_pf_fb_info_t::min_vf_fb_usable
uint32_t min_vf_fb_usable
Minimum usable fb size in MB.
Definition: amdsmi.h:2183
amdsmi_pf_fb_info_t::fb_alignment
uint32_t fb_alignment
FB alignment.
Definition: amdsmi.h:2181
amdsmi_pf_fb_info_t::total_fb_size
uint32_t total_fb_size
Total GPU fb size in MB.
Definition: amdsmi.h:2178
amdsmi_pf_fb_info_t::max_vf_fb_usable
uint32_t max_vf_fb_usable
Maximum usable fb size in MB.
Definition: amdsmi.h:2182
amdsmi_pf_fb_info_t::pf_fb_offset
uint32_t pf_fb_offset
PF FB offset.
Definition: amdsmi.h:2180
amdsmi_power_cap_info_t
Power Cap Information.
Definition: amdsmi.h:766
amdsmi_power_cap_info_t::power_cap
uint64_t power_cap
current power cap Units uW {@linux_bm} or W {@host}
Definition: amdsmi.h:767
amdsmi_power_cap_info_t::dpm_cap
uint64_t dpm_cap
dpm power cap Units MHz {@linux_bm} or Hz {@host}
Definition: amdsmi.h:769
amdsmi_power_cap_info_t::max_power_cap
uint64_t max_power_cap
maximum power cap Units uW {@linux_bm} or W {@host}
Definition: amdsmi.h:771
amdsmi_power_cap_info_t::default_power_cap
uint64_t default_power_cap
default power cap Units uW {@linux_bm} or W {@host}
Definition: amdsmi.h:768
amdsmi_power_cap_info_t::min_power_cap
uint64_t min_power_cap
minimum power cap Units uW {@linux_bm} or W {@host}
Definition: amdsmi.h:770
amdsmi_power_info_t
Power Information.
Definition: amdsmi.h:827
amdsmi_power_info_t::soc_voltage
uint64_t soc_voltage
SOC voltage measurement in mV {@linux_bm} or V {@host}.
Definition: amdsmi.h:832
amdsmi_power_info_t::socket_power
uint64_t socket_power
Current power usage in W {@linux_bm}, uW {@host}.
Definition: amdsmi.h:828
amdsmi_power_info_t::power_limit
uint32_t power_limit
The power limit in W {@linux_bm}, Linux only.
Definition: amdsmi.h:834
amdsmi_power_info_t::mem_voltage
uint64_t mem_voltage
MEM voltage measurement in mV {@linux_bm} or V {@host}.
Definition: amdsmi.h:833
amdsmi_power_info_t::current_socket_power
uint32_t current_socket_power
Current socket power in W {@linux_bm}, Linux only, Mi 300+ Series cards.
Definition: amdsmi.h:829
amdsmi_power_info_t::average_socket_power
uint32_t average_socket_power
Average socket power in W {@linux_bm}, Linux only, Navi + Mi 200 and earlier Series cards.
Definition: amdsmi.h:830
amdsmi_power_info_t::gfx_voltage
uint64_t gfx_voltage
GFX voltage measurement in mV {@linux_bm} or V {@host}.
Definition: amdsmi.h:831
amdsmi_profile_caps_info_t
Profile Caps Information.
Definition: amdsmi.h:2281
amdsmi_profile_info_t
Profile Information.
Definition: amdsmi.h:2295
amdsmi_ras_feature_t::ras_info_
Definition: amdsmi.h:1088
amdsmi_ras_feature_t
This structure holds ras feature information.
Definition: amdsmi.h:1082
amdsmi_ras_feature_t::ras_eeprom_version
uint32_t ras_eeprom_version
Definition: amdsmi.h:1083
amdsmi_ras_feature_t::ecc_correction_schema_flag
uint32_t ecc_correction_schema_flag
Definition: amdsmi.h:1085
amdsmi_sched_info_t
Schedule Information.
Definition: amdsmi.h:2246
amdsmi_sched_info_t::boot_up_time
uint64_t boot_up_time
in microseconds
Definition: amdsmi.h:2248
amdsmi_topology_nearest_t
Topology Nearest.
Definition: amdsmi.h:2440
amdsmi_vbios_info_t
VBios Information.
Definition: amdsmi.h:790
amdsmi_version_t
This structure holds version information.
Definition: amdsmi.h:2486
amdsmi_version_t::minor
uint32_t minor
Minor version.
Definition: amdsmi.h:2488
amdsmi_version_t::major
uint32_t major
Major version.
Definition: amdsmi.h:2487
amdsmi_version_t::release
uint32_t release
Patch, build or stepping version.
Definition: amdsmi.h:2489
amdsmi_vf_data_t
VF Data.
Definition: amdsmi.h:2270
amdsmi_vf_fb_info_t
VF FB Information.
Definition: amdsmi.h:2192
amdsmi_vf_fb_info_t::fb_size
uint32_t fb_size
Size in MB Must be divisible by 16 and not less than 256.
Definition: amdsmi.h:2194
amdsmi_vf_fb_info_t::fb_offset
uint32_t fb_offset
Offset in MB from start of the framebuffer.
Definition: amdsmi.h:2193
amdsmi_vf_handle_t
VF Handle.
Definition: amdsmi.h:2140
amdsmi_vf_info_t
VF Information.
Definition: amdsmi.h:2235
amdsmi_vf_info_t::gfx_timeslice
uint32_t gfx_timeslice
Graphics timeslice in us, maximum value is 1000 ms.
Definition: amdsmi.h:2237
amdsmi_vram_info_t
VRam Information.
Definition: amdsmi.h:855
amdsmi_vram_info_t::vram_bit_width
uint32_t vram_bit_width
In bits.
Definition: amdsmi.h:859
amdsmi_vram_info_t::vram_size
uint64_t vram_size
vram size in MB
Definition: amdsmi.h:858
amdsmi_vram_info_t::vram_max_bandwidth
uint64_t vram_max_bandwidth
The VRAM max bandwidth at current memory clock (GB/s)
Definition: amdsmi.h:860
amdsmi_xgmi_fb_sharing_caps_t::cap_
Definition: amdsmi.h:2452
amdsmi_bdf_t
bdf types
Definition: amdsmi.h:669
amdsmi_cper_valid_bits_t
Definition: amdsmi.h:1177
amdsmi_gpu_ras_policy_info_t::policy_data_
Definition: amdsmi.h:1149
amdsmi_nps_caps_t
This union holds memory partition bitmask.
Definition: amdsmi.h:911
amdsmi_xgmi_fb_sharing_caps_t
XGMI FB Sharing Caps.
Definition: amdsmi.h:2451