amdsmi.h Source File

amdsmi.h Source File#

AMD SMI: amdsmi.h Source File
amdsmi.h
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1 /*
2  * Copyright (c) Advanced Micro Devices, Inc. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy
5  * of this software and associated documentation files (the "Software"), to deal
6  * in the Software without restriction, including without limitation the rights
7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8  * copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20  * THE SOFTWARE.
21  */
22 
23 #ifndef __AMDSMI_H__
24 #define __AMDSMI_H__
25 
31 #ifndef __KERNEL__
32 #include <stdint.h>
33 #include <stdbool.h>
34 #include <stddef.h>
35 #endif
36 
44 typedef enum {
45  AMDSMI_INIT_ALL_PROCESSORS = 0xFFFFFFFF,
46  AMDSMI_INIT_AMD_CPUS = (1 << 0),
47  AMDSMI_INIT_AMD_GPUS = (1 << 1),
48  AMDSMI_INIT_NON_AMD_CPUS = (1 << 2),
49  AMDSMI_INIT_NON_AMD_GPUS = (1 << 3),
50  AMDSMI_INIT_AMD_APUS = (AMDSMI_INIT_AMD_CPUS | AMDSMI_INIT_AMD_GPUS)
52 } amdsmi_init_flags_t;
53 
59 typedef void *amdsmi_processor_handle;
60 typedef void *amdsmi_socket_handle;
61 
70 typedef enum {
71  AMDSMI_STATUS_SUCCESS = 0,
72  // Library usage errors
73  AMDSMI_STATUS_INVAL = 1,
74  AMDSMI_STATUS_NOT_SUPPORTED = 2,
75  AMDSMI_STATUS_NOT_YET_IMPLEMENTED = 3,
76  AMDSMI_STATUS_FAIL_LOAD_MODULE = 4,
77  AMDSMI_STATUS_FAIL_LOAD_SYMBOL = 5,
78  AMDSMI_STATUS_DRM_ERROR = 6,
79  AMDSMI_STATUS_API_FAILED = 7,
80  AMDSMI_STATUS_TIMEOUT = 8,
81  AMDSMI_STATUS_RETRY = 9,
82  AMDSMI_STATUS_NO_PERM = 10,
83  AMDSMI_STATUS_INTERRUPT = 11,
84  AMDSMI_STATUS_IO = 12,
85  AMDSMI_STATUS_ADDRESS_FAULT = 13,
86  AMDSMI_STATUS_FILE_ERROR = 14,
87  AMDSMI_STATUS_OUT_OF_RESOURCES = 15,
88  AMDSMI_STATUS_INTERNAL_EXCEPTION = 16,
89  AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS = 17,
90  AMDSMI_STATUS_INIT_ERROR = 18,
91  AMDSMI_STATUS_REFCOUNT_OVERFLOW = 19,
92  AMDSMI_STATUS_DIRECTORY_NOT_FOUND = 20,
93  // Processor related errors
94  AMDSMI_STATUS_BUSY = 30,
95  AMDSMI_STATUS_NOT_FOUND = 31,
96  AMDSMI_STATUS_NOT_INIT = 32,
97  AMDSMI_STATUS_NO_SLOT = 33,
98  AMDSMI_STATUS_DRIVER_NOT_LOADED = 34,
99  // Data and size errors
100  AMDSMI_STATUS_MORE_DATA = 39,
101  AMDSMI_STATUS_NO_DATA = 40,
102  AMDSMI_STATUS_INSUFFICIENT_SIZE = 41,
103  AMDSMI_STATUS_UNEXPECTED_SIZE = 42,
104  AMDSMI_STATUS_UNEXPECTED_DATA = 43,
105  //esmi errors
106  AMDSMI_STATUS_NON_AMD_CPU = 44,
107  AMDSMI_STATUS_NO_ENERGY_DRV = 45,
108  AMDSMI_STATUS_NO_MSR_DRV = 46,
109  AMDSMI_STATUS_NO_HSMP_DRV = 47,
110  AMDSMI_STATUS_NO_HSMP_SUP = 48,
111  AMDSMI_STATUS_NO_HSMP_MSG_SUP = 49,
112  AMDSMI_STATUS_HSMP_TIMEOUT = 50,
113  AMDSMI_STATUS_NO_DRV = 51,
114  AMDSMI_STATUS_FILE_NOT_FOUND = 52,
115  AMDSMI_STATUS_ARG_PTR_NULL = 53,
116  AMDSMI_STATUS_AMDGPU_RESTART_ERR = 54,
117  AMDSMI_STATUS_SETTING_UNAVAILABLE = 55,
118  AMDSMI_STATUS_CORRUPTED_EEPROM = 56,
119  // General errors
120  AMDSMI_STATUS_MAP_ERROR = 0xFFFFFFFE,
121  AMDSMI_STATUS_UNKNOWN_ERROR = 0xFFFFFFFF,
122 } amdsmi_status_t;
123 
133 typedef enum {
134  AMDSMI_PROCESSOR_TYPE_UNKNOWN = 0,
135  AMDSMI_PROCESSOR_TYPE_AMD_GPU,
136  AMDSMI_PROCESSOR_TYPE_AMD_CPU,
137  AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU,
138  AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU,
139  AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE,
140  AMDSMI_PROCESSOR_TYPE_AMD_APU,
141  AMDSMI_PROCESSOR_TYPE_AMD_NIC
142 } amdsmi_processor_type_t;
143 
149 #define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK 64
150 #define AMDSMI_MAX_NUM_PM_POLICIES 32
151 #define AMDSMI_MAX_CONTAINER_TYPE 2
152 
158 #define AMDSMI_MAX_MM_IP_COUNT 8
159 #define AMDSMI_MAX_DEVICES 32
160 #define AMDSMI_MAX_STRING_LENGTH 256
161 #define AMDSMI_MAX_CACHE_TYPES 10
162 #define AMDSMI_MAX_CP_PROFILE_RESOURCES 32
163 #define AMDSMI_MAX_ACCELERATOR_PARTITIONS 8
164 #define AMDSMI_MAX_ACCELERATOR_PROFILE 32
165 #define AMDSMI_MAX_NUM_NUMA_NODES 32
166 #define AMDSMI_GPU_UUID_SIZE 38
167 
173 #define MAX_NUMBER_OF_AFIDS_PER_RECORD 12
174 
180 #define AMDSMI_MAX_VF_COUNT 32
181 #define AMDSMI_MAX_DRIVER_NUM 2
182 #define AMDSMI_DFC_FW_NUMBER_OF_ENTRIES 9
183 #define AMDSMI_MAX_WHITE_LIST_ELEMENTS 16
184 #define AMDSMI_MAX_BLACK_LIST_ELEMENTS 64
185 #define AMDSMI_MAX_UUID_ELEMENTS 16
186 #define AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS 8
187 #define AMDSMI_MAX_ERR_RECORDS 10
188 #define AMDSMI_MAX_PROFILE_COUNT 16
189 
195 #define AMDSMI_TIME_FORMAT "%02d:%02d:%02d.%03d"
196 #define AMDSMI_DATE_FORMAT "%04d-%02d-%02d:%02d:%02d:%02d.%03d"
197 
203 typedef enum {
204  AMDSMI_MEMORY_PARTITION_UNKNOWN = 0,
205  AMDSMI_MEMORY_PARTITION_NPS1 = 1,
207  AMDSMI_MEMORY_PARTITION_NPS2 = 2,
210  AMDSMI_MEMORY_PARTITION_NPS4 = 4,
213  AMDSMI_MEMORY_PARTITION_NPS8 = 8,
218 } amdsmi_memory_partition_type_t;
219 
225 typedef enum {
226  AMDSMI_ACCELERATOR_PARTITION_INVALID = 0,
227  AMDSMI_ACCELERATOR_PARTITION_SPX,
229  AMDSMI_ACCELERATOR_PARTITION_DPX,
231  AMDSMI_ACCELERATOR_PARTITION_TPX,
233  AMDSMI_ACCELERATOR_PARTITION_QPX,
235  AMDSMI_ACCELERATOR_PARTITION_CPX,
237  AMDSMI_ACCELERATOR_PARTITION_MAX
238 } amdsmi_accelerator_partition_type_t;
239 
245 typedef enum {
246  AMDSMI_VRAM_TYPE_UNKNOWN = 0,
247  // HBM
248  AMDSMI_VRAM_TYPE_HBM = 1,
249  AMDSMI_VRAM_TYPE_HBM2 = 2,
250  AMDSMI_VRAM_TYPE_HBM2E = 3,
251  AMDSMI_VRAM_TYPE_HBM3 = 4,
252  AMDSMI_VRAM_TYPE_HBM3E = 5,
253  // DDR
254  AMDSMI_VRAM_TYPE_DDR2 = 10,
255  AMDSMI_VRAM_TYPE_DDR3 = 11,
256  AMDSMI_VRAM_TYPE_DDR4 = 12,
257  // GDDR
258  AMDSMI_VRAM_TYPE_GDDR1 = 17,
259  AMDSMI_VRAM_TYPE_GDDR2 = 18,
260  AMDSMI_VRAM_TYPE_GDDR3 = 19,
261  AMDSMI_VRAM_TYPE_GDDR4 = 20,
262  AMDSMI_VRAM_TYPE_GDDR5 = 21,
263  AMDSMI_VRAM_TYPE_GDDR6 = 22,
264  AMDSMI_VRAM_TYPE_GDDR7 = 23,
265  AMDSMI_VRAM_TYPE__MAX = AMDSMI_VRAM_TYPE_GDDR7
266 } amdsmi_vram_type_t;
267 
273 typedef enum {
274  AMDSMI_ACCELERATOR_XCC,
275  AMDSMI_ACCELERATOR_ENCODER,
276  AMDSMI_ACCELERATOR_DECODER,
277  AMDSMI_ACCELERATOR_DMA,
278  AMDSMI_ACCELERATOR_JPEG,
279  AMDSMI_ACCELERATOR_MAX
280 } amdsmi_accelerator_partition_resource_type_t;
281 
287 typedef enum {
288  AMDSMI_CLK_TYPE_SYS = 0x0,
289  AMDSMI_CLK_TYPE_FIRST = AMDSMI_CLK_TYPE_SYS,
290  AMDSMI_CLK_TYPE_GFX = AMDSMI_CLK_TYPE_SYS,
291  AMDSMI_CLK_TYPE_DF,
293  AMDSMI_CLK_TYPE_DCEF,
295  AMDSMI_CLK_TYPE_SOC,
296  AMDSMI_CLK_TYPE_MEM,
297  AMDSMI_CLK_TYPE_PCIE,
298  AMDSMI_CLK_TYPE_VCLK0,
299  AMDSMI_CLK_TYPE_VCLK1,
300  AMDSMI_CLK_TYPE_DCLK0,
301  AMDSMI_CLK_TYPE_DCLK1,
302  AMDSMI_CLK_TYPE__MAX = AMDSMI_CLK_TYPE_DCLK1
303 } amdsmi_clk_type_t;
304 
311 typedef enum {
312  AMDSMI_TEMPERATURE_TYPE_EDGE,
313  AMDSMI_TEMPERATURE_TYPE_FIRST = AMDSMI_TEMPERATURE_TYPE_EDGE,
314  AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
315  AMDSMI_TEMPERATURE_TYPE_JUNCTION = AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
316  AMDSMI_TEMPERATURE_TYPE_VRAM,
317  AMDSMI_TEMPERATURE_TYPE_HBM_0,
318  AMDSMI_TEMPERATURE_TYPE_HBM_1,
319  AMDSMI_TEMPERATURE_TYPE_HBM_2,
320  AMDSMI_TEMPERATURE_TYPE_HBM_3,
321  AMDSMI_TEMPERATURE_TYPE_PLX,
322 
323  // GPU Board Node temperature
324  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_FIRST = 100,
325  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X
326  = AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_FIRST,
327  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC,
328  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2,
329  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR,
330  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR,
331  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR,
332  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_LAST = 149,
333 
334  // GPU Board VR (Voltage Regulator) temperature
335  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_FIRST = 150,
336  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0
337  = AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_FIRST,
338  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1,
339  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2,
340  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3,
341  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A,
342  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C,
343  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A,
344  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C,
345  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM,
346  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B,
347  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D,
348  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR,
349  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32,
350  AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VR_LAST = 199,
351 
352  // Baseboard System temperature
353  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_FIRST = 200,
354  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA = AMDSMI_TEMPERATURE_TYPE_BASEBOARD_FIRST,
355  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT,
356  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK,
357  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7,
358  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC,
359  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA,
360  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1,
361  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC,
362  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC,
363  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC,
364  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC,
365  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR,
366  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR,
367  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR,
368  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR,
369  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR,
370  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR,
371  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR,
372  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR,
373  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR,
374  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR,
375  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC,
376  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC,
377  AMDSMI_TEMPERATURE_TYPE_BASEBOARD_LAST = 249,
378  AMDSMI_TEMPERATURE_TYPE__MAX = AMDSMI_TEMPERATURE_TYPE_BASEBOARD_LAST
379 } amdsmi_temperature_type_t;
380 
387 typedef enum {
388  AMDSMI_TEMP_CURRENT = 0x0,
389  AMDSMI_TEMP_FIRST = AMDSMI_TEMP_CURRENT,
390  AMDSMI_TEMP_MAX,
391  AMDSMI_TEMP_MIN,
392  AMDSMI_TEMP_MAX_HYST,
394  AMDSMI_TEMP_MIN_HYST,
396  AMDSMI_TEMP_CRITICAL,
398  AMDSMI_TEMP_CRITICAL_HYST,
400  AMDSMI_TEMP_EMERGENCY,
404  AMDSMI_TEMP_EMERGENCY_HYST,
406  AMDSMI_TEMP_CRIT_MIN,
408  AMDSMI_TEMP_CRIT_MIN_HYST,
410  AMDSMI_TEMP_OFFSET,
412  AMDSMI_TEMP_LOWEST,
413  AMDSMI_TEMP_HIGHEST,
414  AMDSMI_TEMP_SHUTDOWN,
415  AMDSMI_TEMP_LAST = AMDSMI_TEMP_SHUTDOWN
416 } amdsmi_temperature_metric_t;
417 
423 typedef enum {
424  AMDSMI_CARD_FORM_FACTOR_PCIE,
425  AMDSMI_CARD_FORM_FACTOR_OAM,
426  AMDSMI_CARD_FORM_FACTOR_CEM,
427  AMDSMI_CARD_FORM_FACTOR_UNKNOWN
428 } amdsmi_card_form_factor_t;
429 
435 typedef enum {
436  AMDSMI_LINK_TYPE_INTERNAL = 0,
437  AMDSMI_LINK_TYPE_PCIE = 1,
438  AMDSMI_LINK_TYPE_XGMI = 2,
439  AMDSMI_LINK_TYPE_NOT_APPLICABLE = 3,
440  AMDSMI_LINK_TYPE_UNKNOWN = 4
441 } amdsmi_link_type_t;
442 
448 typedef enum {
449  AMDSMI_CACHE_PROPERTY_ENABLED = 0x00000001,
450  AMDSMI_CACHE_PROPERTY_DATA_CACHE = 0x00000002,
451  AMDSMI_CACHE_PROPERTY_INST_CACHE = 0x00000004,
452  AMDSMI_CACHE_PROPERTY_CPU_CACHE = 0x00000008,
453  AMDSMI_CACHE_PROPERTY_SIMD_CACHE = 0x00000010
454 } amdsmi_cache_property_type_t;
455 
461 typedef enum {
462  AMDSMI_GPU_BLOCK_INVALID = 0,
463  AMDSMI_GPU_BLOCK_FIRST = (1ULL << 0),
464  AMDSMI_GPU_BLOCK_UMC = AMDSMI_GPU_BLOCK_FIRST,
465  AMDSMI_GPU_BLOCK_SDMA = (1ULL << 1),
466  AMDSMI_GPU_BLOCK_GFX = (1ULL << 2),
467  AMDSMI_GPU_BLOCK_MMHUB = (1ULL << 3),
468  AMDSMI_GPU_BLOCK_ATHUB = (1ULL << 4),
469  AMDSMI_GPU_BLOCK_PCIE_BIF = (1ULL << 5),
470  AMDSMI_GPU_BLOCK_HDP = (1ULL << 6),
471  AMDSMI_GPU_BLOCK_XGMI_WAFL = (1ULL << 7),
472  AMDSMI_GPU_BLOCK_DF = (1ULL << 8),
473  AMDSMI_GPU_BLOCK_SMN = (1ULL << 9),
474  AMDSMI_GPU_BLOCK_SEM = (1ULL << 10),
475  AMDSMI_GPU_BLOCK_MP0 = (1ULL << 11),
476  AMDSMI_GPU_BLOCK_MP1 = (1ULL << 12),
477  AMDSMI_GPU_BLOCK_FUSE = (1ULL << 13),
478  AMDSMI_GPU_BLOCK_MCA = (1ULL << 14),
479  AMDSMI_GPU_BLOCK_VCN = (1ULL << 15),
480  AMDSMI_GPU_BLOCK_JPEG = (1ULL << 16),
481  AMDSMI_GPU_BLOCK_IH = (1ULL << 17),
482  AMDSMI_GPU_BLOCK_MPIO = (1ULL << 18),
483  AMDSMI_GPU_BLOCK_LAST = AMDSMI_GPU_BLOCK_MPIO,
484  AMDSMI_GPU_BLOCK_RESERVED = (1ULL << 63)
485 } amdsmi_gpu_block_t;
486 
493 typedef enum {
494  AMDSMI_FW_ID_SMU = 1,
496  AMDSMI_FW_ID_FIRST = AMDSMI_FW_ID_SMU,
497  AMDSMI_FW_ID_CP_CE,
498  AMDSMI_FW_ID_CP_PFP,
499  AMDSMI_FW_ID_CP_ME,
500  AMDSMI_FW_ID_CP_MEC_JT1,
501  AMDSMI_FW_ID_CP_MEC_JT2,
502  AMDSMI_FW_ID_CP_MEC1,
503  AMDSMI_FW_ID_CP_MEC2,
504  AMDSMI_FW_ID_RLC,
505  AMDSMI_FW_ID_SDMA0,
506  AMDSMI_FW_ID_SDMA1,
507  AMDSMI_FW_ID_SDMA2,
508  AMDSMI_FW_ID_SDMA3,
509  AMDSMI_FW_ID_SDMA4,
510  AMDSMI_FW_ID_SDMA5,
511  AMDSMI_FW_ID_SDMA6,
512  AMDSMI_FW_ID_SDMA7,
513  AMDSMI_FW_ID_VCN,
514  AMDSMI_FW_ID_UVD,
515  AMDSMI_FW_ID_VCE,
516  AMDSMI_FW_ID_ISP,
517  AMDSMI_FW_ID_DMCU_ERAM,
518  AMDSMI_FW_ID_DMCU_ISR,
519  AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM,
520  AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM,
521  AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL,
522  AMDSMI_FW_ID_RLC_V,
523  AMDSMI_FW_ID_MMSCH,
524  AMDSMI_FW_ID_PSP_SYSDRV,
525  AMDSMI_FW_ID_PSP_SOSDRV,
526  AMDSMI_FW_ID_PSP_TOC,
527  AMDSMI_FW_ID_PSP_KEYDB,
528  AMDSMI_FW_ID_DFC,
529  AMDSMI_FW_ID_PSP_SPL,
530  AMDSMI_FW_ID_DRV_CAP,
531  AMDSMI_FW_ID_MC,
532  AMDSMI_FW_ID_PSP_BL,
533  AMDSMI_FW_ID_CP_PM4,
534  AMDSMI_FW_ID_RLC_P,
535  AMDSMI_FW_ID_SEC_POLICY_STAGE2,
536  AMDSMI_FW_ID_REG_ACCESS_WHITELIST,
537  AMDSMI_FW_ID_IMU_DRAM,
538  AMDSMI_FW_ID_IMU_IRAM,
539  AMDSMI_FW_ID_SDMA_TH0,
540  AMDSMI_FW_ID_SDMA_TH1,
541  AMDSMI_FW_ID_CP_MES,
542  AMDSMI_FW_ID_MES_KIQ,
543  AMDSMI_FW_ID_MES_STACK,
544  AMDSMI_FW_ID_MES_THREAD1,
545  AMDSMI_FW_ID_MES_THREAD1_STACK,
546  AMDSMI_FW_ID_RLX6,
547  AMDSMI_FW_ID_RLX6_DRAM_BOOT,
548  AMDSMI_FW_ID_RS64_ME,
549  AMDSMI_FW_ID_RS64_ME_P0_DATA,
550  AMDSMI_FW_ID_RS64_ME_P1_DATA,
551  AMDSMI_FW_ID_RS64_PFP,
552  AMDSMI_FW_ID_RS64_PFP_P0_DATA,
553  AMDSMI_FW_ID_RS64_PFP_P1_DATA,
554  AMDSMI_FW_ID_RS64_MEC,
555  AMDSMI_FW_ID_RS64_MEC_P0_DATA,
556  AMDSMI_FW_ID_RS64_MEC_P1_DATA,
557  AMDSMI_FW_ID_RS64_MEC_P2_DATA,
558  AMDSMI_FW_ID_RS64_MEC_P3_DATA,
559  AMDSMI_FW_ID_PPTABLE,
560  AMDSMI_FW_ID_PSP_SOC,
561  AMDSMI_FW_ID_PSP_DBG,
562  AMDSMI_FW_ID_PSP_INTF,
563  AMDSMI_FW_ID_RLX6_CORE1,
564  AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1,
565  AMDSMI_FW_ID_RLCV_LX7,
566  AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST,
567  AMDSMI_FW_ID_ASD,
568  AMDSMI_FW_ID_TA_RAS,
569  AMDSMI_FW_ID_TA_XGMI,
570  AMDSMI_FW_ID_XGMI,
571  AMDSMI_FW_ID_RLC_SRLG,
572  AMDSMI_FW_ID_RLC_SRLS,
573  AMDSMI_FW_ID_PM,
574  AMDSMI_FW_ID_SMC,
575  AMDSMI_FW_ID_DMCU,
576  AMDSMI_FW_ID_PSP_RAS,
577  AMDSMI_FW_ID_P2S_TABLE,
578  AMDSMI_FW_ID_PLDM_BUNDLE,
579  AMDSMI_FW_ID__MAX
580 } amdsmi_fw_block_t;
581 
590 typedef enum {
591  AMDSMI_VIRTUALIZATION_MODE_UNKNOWN = 0,
592  AMDSMI_VIRTUALIZATION_MODE_BAREMETAL,
593  AMDSMI_VIRTUALIZATION_MODE_HOST,
594  AMDSMI_VIRTUALIZATION_MODE_GUEST,
595  AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH
596 } amdsmi_virtualization_mode_t;
597 
603 typedef enum {
604  AMDSMI_AFFINITY_SCOPE_NODE,
605  AMDSMI_AFFINITY_SCOPE_SOCKET
606 } amdsmi_affinity_scope_t;
607 
613 typedef enum {
614  AMDSMI_LINK_STATUS_ENABLED = 0,
615  AMDSMI_LINK_STATUS_DISABLED = 1,
616  AMDSMI_LINK_STATUS_INACTIVE = 2,
617  AMDSMI_LINK_STATUS_ERROR = 3
618 } amdsmi_link_status_t;
619 
625 typedef union {
626  struct bdf_ {
627  uint64_t function_number : 3;
628  uint64_t device_number : 5;
629  uint64_t bus_number : 8;
630  uint64_t domain_number : 48;
631  } bdf;
632  struct {
633  uint64_t function_number : 3;
634  uint64_t device_number : 5;
635  uint64_t bus_number : 8;
636  uint64_t domain_number : 48;
637  };
638  uint64_t as_uint;
639 } amdsmi_bdf_t;
640 
646 typedef struct {
647  struct pcie_static_ {
648  uint16_t max_pcie_width;
649  uint32_t max_pcie_speed;
650  uint32_t pcie_interface_version;
651  amdsmi_card_form_factor_t slot_type;
652  uint32_t max_pcie_interface_version;
653  uint64_t reserved[9];
654  } pcie_static;
655  struct pcie_metric_ {
656  uint16_t pcie_width;
657  uint32_t pcie_speed;
658  uint32_t pcie_bandwidth;
659  uint64_t pcie_replay_count;
660  uint64_t pcie_l0_to_recovery_count;
661  uint64_t pcie_replay_roll_over_count;
662  uint64_t pcie_nak_sent_count;
663  uint64_t pcie_nak_received_count;
664  uint32_t pcie_lc_perf_other_end_recovery_count;
665  uint64_t reserved[12];
666  } pcie_metric;
667  uint64_t reserved[32];
668 } amdsmi_pcie_info_t;
669 
675 typedef struct {
676  uint32_t num_links;
677  struct _links {
678  amdsmi_bdf_t bdf;
679  uint32_t bit_rate;
680  uint32_t max_bandwidth;
681  amdsmi_link_type_t link_type;
682  uint64_t read;
683  uint64_t write;
684  amdsmi_link_status_t link_status;
685  uint64_t reserved[1];
686  } links[AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK];
687  uint64_t reserved[7];
688 } amdsmi_link_metrics_t;
689 
695 typedef struct {
696  uint64_t power_cap;
697  uint64_t default_power_cap;
698  uint64_t dpm_cap;
699  uint64_t min_power_cap;
700  uint64_t max_power_cap;
701  uint64_t reserved[3];
702 } amdsmi_power_cap_info_t;
703 
709 typedef struct {
710  char name[AMDSMI_MAX_STRING_LENGTH];
711  char build_date[AMDSMI_MAX_STRING_LENGTH];
712  char part_number[AMDSMI_MAX_STRING_LENGTH];
713  char version[AMDSMI_MAX_STRING_LENGTH];
714  char boot_firmware[AMDSMI_MAX_STRING_LENGTH];
715  uint64_t reserved[36];
716 } amdsmi_vbios_info_t;
717 
723 typedef struct {
724  char market_name[AMDSMI_MAX_STRING_LENGTH];
725  uint32_t vendor_id;
726  char vendor_name[AMDSMI_MAX_STRING_LENGTH];
727  uint32_t subvendor_id;
728  uint64_t device_id;
729  uint32_t rev_id;
730  char asic_serial[AMDSMI_MAX_STRING_LENGTH];
731  uint32_t oam_id;
732  uint32_t num_of_compute_units;
733  uint64_t target_graphics_version;
734  uint32_t subsystem_id;
735  uint32_t reserved[21];
736 } amdsmi_asic_info_t;
737 
743 typedef struct {
744  uint64_t socket_power;
745  uint32_t current_socket_power;
746  uint32_t average_socket_power;
747  uint64_t gfx_voltage;
748  uint64_t soc_voltage;
749  uint64_t mem_voltage;
750  uint32_t power_limit;
751  uint64_t reserved[18];
752 } amdsmi_power_info_t;
753 
759 typedef struct {
760  char driver_version[AMDSMI_MAX_STRING_LENGTH];
761  char driver_date[AMDSMI_MAX_STRING_LENGTH];
762  char driver_name[AMDSMI_MAX_STRING_LENGTH];
763  uint64_t reserved[64];
764 } amdsmi_driver_info_t;
765 
771 typedef struct {
772  amdsmi_vram_type_t vram_type;
773  char vram_vendor[AMDSMI_MAX_STRING_LENGTH];
774  uint64_t vram_size;
775  uint32_t vram_bit_width;
776  uint64_t vram_max_bandwidth;
777  uint64_t reserved[37];
778 } amdsmi_vram_info_t;
779 
789 typedef struct {
790  uint32_t gfx_activity;
791  uint32_t umc_activity;
792  uint32_t mm_activity;
793  uint32_t reserved[13];
794 } amdsmi_engine_usage_t;
795 
801 typedef struct {
802  uint32_t clk;
803  uint32_t min_clk;
804  uint32_t max_clk;
805  uint8_t clk_locked;
806  uint8_t clk_deep_sleep;
807  uint32_t reserved[4];
808 } amdsmi_clk_info_t;
809 
815 typedef struct {
816  uint64_t correctable_count;
817  uint64_t uncorrectable_count;
818  uint64_t deferred_count;
819  uint64_t reserved[5];
820 } amdsmi_error_count_t;
821 
827 typedef union {
828  struct nps_flags_{
829  uint32_t nps1_cap :1;
830  uint32_t nps2_cap :1;
831  uint32_t nps4_cap :1;
832  uint32_t nps8_cap :1;
833  uint32_t reserved :28;
834  } nps_flags;
835  uint32_t nps_cap_mask;
836 } amdsmi_nps_caps_t;
837 
844 typedef struct {
845  amdsmi_nps_caps_t partition_caps;
846  amdsmi_memory_partition_type_t mp_mode;
847  uint32_t num_numa_ranges;
848  struct numa_range_{
849  amdsmi_vram_type_t memory_type;
850  uint64_t start;
851  uint64_t end;
852  } numa_range[AMDSMI_MAX_NUM_NUMA_NODES];
853  uint64_t reserved[11];
854 } amdsmi_memory_partition_config_t;
855 
861 typedef struct {
862  amdsmi_accelerator_partition_type_t profile_type;
863  uint32_t num_partitions;
864  amdsmi_nps_caps_t memory_caps;
865  uint32_t profile_index;
866  uint32_t num_resources;
867  uint32_t resources[AMDSMI_MAX_ACCELERATOR_PARTITIONS][AMDSMI_MAX_CP_PROFILE_RESOURCES];
868  uint64_t reserved[13];
869 } amdsmi_accelerator_partition_profile_t;
870 
877 typedef struct {
878  uint32_t profile_index;
879  amdsmi_accelerator_partition_resource_type_t resource_type;
880  uint32_t partition_resource;
881  uint32_t num_partitions_share_resource;
882  uint64_t reserved[6];
883 } amdsmi_accelerator_partition_resource_profile_t;
884 
890 typedef struct {
891  uint32_t num_profiles;
892  uint32_t num_resource_profiles;
893  amdsmi_accelerator_partition_resource_profile_t resource_profiles[AMDSMI_MAX_CP_PROFILE_RESOURCES];
894  uint32_t default_profile_index;
895  amdsmi_accelerator_partition_profile_t profiles[AMDSMI_MAX_ACCELERATOR_PROFILE];
896  uint64_t reserved[30];
897 } amdsmi_accelerator_partition_profile_config_t;
898 
904 typedef struct {
905  char model_number[AMDSMI_MAX_STRING_LENGTH];
906  char product_serial[AMDSMI_MAX_STRING_LENGTH];
907  char fru_id[AMDSMI_MAX_STRING_LENGTH];
908  char product_name[AMDSMI_MAX_STRING_LENGTH];
909  char manufacturer_name[AMDSMI_MAX_STRING_LENGTH];
910  uint64_t reserved[64];
911 } amdsmi_board_info_t;
912 
918 typedef struct {
919  uint8_t is_iolink_coherent;
920  uint8_t is_iolink_atomics_32bit;
921  uint8_t is_iolink_atomics_64bit;
922  uint8_t is_iolink_dma;
923  uint8_t is_iolink_bi_directional;
924 } amdsmi_p2p_capability_t;
925 
931 typedef struct {
932  uint32_t num_cache_types;
933  struct cache_ {
934  uint32_t cache_properties;
935  uint32_t cache_size;
936  uint32_t cache_level;
937  uint32_t max_num_cu_shared;
938  uint32_t num_cache_instance;
939  uint32_t reserved[3];
940  } cache[AMDSMI_MAX_CACHE_TYPES];
941  uint32_t reserved[15];
942 } amdsmi_gpu_cache_info_t;
943 
949 typedef struct {
950  uint8_t num_fw_info;
951  struct {
952  amdsmi_fw_block_t fw_id;
953  uint64_t fw_version;
954  uint64_t reserved[2];
955  } fw_info_list[AMDSMI_FW_ID__MAX];
956  uint32_t reserved[7];
957 } amdsmi_fw_info_t;
958 
964 typedef struct {
965  uint32_t policy_id;
966  char policy_description[AMDSMI_MAX_STRING_LENGTH];
967 } amdsmi_dpm_policy_entry_t;
968 
976 typedef struct {
977  uint32_t num_supported;
978  uint32_t current;
979  amdsmi_dpm_policy_entry_t policies[AMDSMI_MAX_NUM_PM_POLICIES];
980 } amdsmi_dpm_policy_t;
981 
987 typedef struct {
988  struct {
989  uint32_t dram_ecc : 1;
990  uint32_t sram_ecc : 1;
991  uint32_t poisoning : 1;
992  uint32_t rsvd : 29;
993  } ras_info;
994  bool needs_reboot;
995  uint32_t ras_eeprom_version;
997  uint32_t ecc_correction_schema_flag;
1000  uint32_t reserved[4];
1001 } amdsmi_ras_feature_t;
1002 
1008 typedef enum {
1009  AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED = 0,
1010  AMDSMI_CPER_SEV_FATAL = 1,
1011  AMDSMI_CPER_SEV_NON_FATAL_CORRECTED = 2,
1012  AMDSMI_CPER_SEV_NUM = 3,
1013  AMDSMI_CPER_SEV_UNUSED = 10
1014 } amdsmi_cper_sev_t;
1015 
1021 typedef enum {
1022  AMDSMI_CPER_NOTIFY_TYPE_CMC = 0x450eBDD72DCE8BB1,
1023  AMDSMI_CPER_NOTIFY_TYPE_CPE = 0x4a55D8434E292F96,
1024  AMDSMI_CPER_NOTIFY_TYPE_MCE = 0x4cc5919CE8F56FFE,
1025  AMDSMI_CPER_NOTIFY_TYPE_PCIE = 0x4dfc1A16CF93C01F,
1026  AMDSMI_CPER_NOTIFY_TYPE_INIT = 0x454a9308CC5263E8,
1027  AMDSMI_CPER_NOTIFY_TYPE_NMI = 0x42c9B7E65BAD89FF,
1028  AMDSMI_CPER_NOTIFY_TYPE_BOOT = 0x409aAB403D61A466,
1029  AMDSMI_CPER_NOTIFY_TYPE_DMAR = 0x4c27C6B3667DD791,
1030  AMDSMI_CPER_NOTIFY_TYPE_SEA = 0x11E4BBE89A78788A,
1031  AMDSMI_CPER_NOTIFY_TYPE_SEI = 0x4E87B0AE5C284C81,
1032  AMDSMI_CPER_NOTIFY_TYPE_PEI = 0x4214520409A9D5AC,
1033  AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT = 0x49A341DF69293BC9
1034 } amdsmi_cper_notify_type_t;
1035 
1036 #pragma pack(push, 1)
1037 
1043 typedef struct {
1044  unsigned char b[16];
1045 } amdsmi_cper_guid_t;
1046 
1047 typedef struct {
1048  uint8_t seconds;
1049  uint8_t minutes;
1050  uint8_t hours;
1051  uint8_t flag;
1052  uint8_t day;
1053  uint8_t month;
1054  uint8_t year;
1055  uint8_t century;
1056 } amdsmi_cper_timestamp_t;
1057 
1058 typedef union {
1059  struct valid_bits_ {
1060  uint32_t platform_id : 1;
1061  uint32_t timestamp : 1;
1062  uint32_t partition_id : 1;
1063  uint32_t reserved : 29;
1064  } valid_bits;
1065  uint32_t valid_mask;
1066 } amdsmi_cper_valid_bits_t;
1067 
1068 typedef struct {
1069  char signature[4];
1070  uint16_t revision;
1071  uint32_t signature_end;
1072  uint16_t sec_cnt;
1073  amdsmi_cper_sev_t error_severity;
1074  amdsmi_cper_valid_bits_t cper_valid_bits;
1075  uint32_t record_length;
1076  amdsmi_cper_timestamp_t timestamp;
1077  char platform_id[16];
1078  amdsmi_cper_guid_t partition_id;
1079  char creator_id[16];
1080  amdsmi_cper_guid_t notify_type;
1081  char record_id[8];
1082  uint32_t flags;
1083  uint64_t persistence_info;
1084  uint8_t reserved[12];
1085 } amdsmi_cper_hdr_t;
1086 
1087 #pragma pack(pop)
1088 
1094 #define SMI_VERSION_ALPHA_0 0x00000002
1095 #define SMI_VERSION_BETA_0 0x00000003
1096 #define SMI_VERSION_BETA_1 0x00000004
1097 #define SMI_VERSION_BETA_2 0x00000005
1098 #define SMI_VERSION_BETA_3 0x00000006
1099 #define SMI_VERSION_BETA_4 0x00000007
1100 
1108 #define AMDSMI_MASK_ALL (~0ULL)
1109 
1111 #define AMDSMI_MASK_DEFAULT ((1ULL << 62) - 1)
1112 
1114 #define AMDSMI_MASK_INIT (0ULL)
1115 
1117 #define AMDSMI_MASK_HIGH_AND_MED_SEVERITY (~((1ULL << 61) - 1))
1118 
1124 #define AMDSMI_MASK_HIGH_ERROR_SEVERITY_ONLY(mask) (mask & ((1ULL << 60) - 1))
1125 #define AMDSMI_MASK_INCLUDE_MED_ERROR_SEVERITY(mask) (mask | (1ULL << 60))
1126 #define AMDSMI_MASK_INCLUDE_LOW_ERROR_SEVERITY(mask) (mask | (1ULL << 61))
1127 #define AMDSMI_MASK_INCLUDE_WARN_SEVERITY(mask) (mask | (1ULL << 62))
1128 #define AMDSMI_MASK_INCLUDE_INFO_SEVERITY(mask) (mask | (1ULL << 63))
1129 
1135 #define AMDSMI_MASK_HIGH_SEVERITY_ONLY(mask) (mask & ((1ULL << 62) - 1))
1136 #define AMDSMI_MASK_INCLUDE_MED_SEVERITY(mask) AMDSMI_MASK_INCLUDE_WARN_SEVERITY(mask)
1137 #define AMDSMI_MASK_INCLUDE_LOW_SEVERITY(mask) AMDSMI_MASK_INCLUDE_INFO_SEVERITY(mask)
1138 
1139 #define AMDSMI_MASK_INCLUDE_CATEGORY(mask, cate) (mask | (1ULL << cate))
1140 #define AMDSMI_MASK_EXCLUDE_CATEGORY(mask, cate) (mask & (~(1ULL << cate)))
1141 
1142 #define AMDSMI_MAX_FB_SHARING_GROUPS 64
1143 #define AMDSMI_MAX_NUM_CONNECTED_NODES 64
1144 
1145 #define AMDSMI_MAX_NUM_METRICS_V1 255
1146 #define AMDSMI_MAX_NUM_METRICS_V2 512
1147 #define AMDSMI_MAX_NUM_METRICS AMDSMI_MAX_NUM_METRICS_V2
1148 
1149 #define AMDSMI_MAX_BAD_PAGE_RECORD_V1 512
1150 #define AMDSMI_MAX_BAD_PAGE_RECORD_V2 16384
1151 #define AMDSMI_MAX_BAD_PAGE_RECORD AMDSMI_MAX_BAD_PAGE_RECORD_V2
1152 
1158 #define AMDSMI_MAX_DATE_STRING_LENGTH 32
1159 
1165 typedef void *amdsmi_event_set;
1166 
1172 typedef enum {
1173  AMDSMI_EVENT_CATEGORY_NON_USED = 0,
1174  AMDSMI_EVENT_CATEGORY_DRIVER = 1,
1175  AMDSMI_EVENT_CATEGORY_RESET = 2,
1176  AMDSMI_EVENT_CATEGORY_SCHED = 3,
1177  AMDSMI_EVENT_CATEGORY_VBIOS = 4,
1178  AMDSMI_EVENT_CATEGORY_ECC = 5,
1179  AMDSMI_EVENT_CATEGORY_PP = 6,
1180  AMDSMI_EVENT_CATEGORY_IOV = 7,
1181  AMDSMI_EVENT_CATEGORY_VF = 8,
1182  AMDSMI_EVENT_CATEGORY_FW = 9,
1183  AMDSMI_EVENT_CATEGORY_GPU = 10,
1184  AMDSMI_EVENT_CATEGORY_GUARD = 11,
1185  AMDSMI_EVENT_CATEGORY_GPUMON = 12,
1186  AMDSMI_EVENT_CATEGORY_MMSCH = 13,
1187  AMDSMI_EVENT_CATEGORY_XGMI = 14,
1188  AMDSMI_EVENT_CATEGORY__MAX
1189 } amdsmi_event_category_t;
1190 
1196 typedef enum {
1197  AMDSMI_EVENT_GPU_DEVICE_LOST = 0,
1198  AMDSMI_EVENT_GPU_NOT_SUPPORTED,
1199  AMDSMI_EVENT_GPU_RMA,
1200  AMDSMI_EVENT_GPU_NOT_INITIALIZED,
1201  AMDSMI_EVENT_GPU_MMSCH_ABNORMAL_STATE,
1202  AMDSMI_EVENT_GPU_RLCV_ABNORMAL_STATE,
1203  AMDSMI_EVENT_GPU_SDMA_ENGINE_BUSY,
1204  AMDSMI_EVENT_GPU_RLC_ENGINE_BUSY,
1205  AMDSMI_EVENT_GPU_GC_ENGINE_BUSY,
1206  AMDSMI_EVENT_GPU__MAX
1207 } amdsmi_event_gpu_t;
1208 
1214 typedef enum {
1215  AMDSMI_EVENT_DRIVER_SPIN_LOCK_BUSY = 0,
1216  AMDSMI_EVENT_DRIVER_ALLOC_SYSTEM_MEM_FAIL,
1217  AMDSMI_EVENT_DRIVER_CREATE_GFX_WORKQUEUE_FAIL,
1218  AMDSMI_EVENT_DRIVER_CREATE_MM_WORKQUEUE_FAIL,
1219  AMDSMI_EVENT_DRIVER_BUFFER_OVERFLOW,
1220 
1221  AMDSMI_EVENT_DRIVER_DEV_INIT_FAIL,
1222  AMDSMI_EVENT_DRIVER_CREATE_THREAD_FAIL,
1223  AMDSMI_EVENT_DRIVER_NO_ACCESS_PCI_REGION,
1224  AMDSMI_EVENT_DRIVER_MMIO_FAIL,
1225  AMDSMI_EVENT_DRIVER_INTERRUPT_INIT_FAIL,
1226 
1227  AMDSMI_EVENT_DRIVER_INVALID_VALUE,
1228  AMDSMI_EVENT_DRIVER_CREATE_MUTEX_FAIL,
1229  AMDSMI_EVENT_DRIVER_CREATE_TIMER_FAIL,
1230  AMDSMI_EVENT_DRIVER_CREATE_EVENT_FAIL,
1231  AMDSMI_EVENT_DRIVER_CREATE_SPIN_LOCK_FAIL,
1232 
1233  AMDSMI_EVENT_DRIVER_ALLOC_FB_MEM_FAIL,
1234  AMDSMI_EVENT_DRIVER_ALLOC_DMA_MEM_FAIL,
1235  AMDSMI_EVENT_DRIVER_NO_FB_MANAGER,
1236  AMDSMI_EVENT_DRIVER_HW_INIT_FAIL,
1237  AMDSMI_EVENT_DRIVER_SW_INIT_FAIL,
1238 
1239  AMDSMI_EVENT_DRIVER_INIT_CONFIG_ERROR,
1240  AMDSMI_EVENT_DRIVER_ERROR_LOGGING_FAILED,
1241  AMDSMI_EVENT_DRIVER_CREATE_RWLOCK_FAIL,
1242  AMDSMI_EVENT_DRIVER_CREATE_RWSEMA_FAIL,
1243  AMDSMI_EVENT_DRIVER_GET_READ_LOCK_FAIL,
1244 
1245  AMDSMI_EVENT_DRIVER_GET_WRITE_LOCK_FAIL,
1246  AMDSMI_EVENT_DRIVER_GET_READ_SEMA_FAIL,
1247  AMDSMI_EVENT_DRIVER_GET_WRITE_SEMA_FAIL,
1248 
1249  AMDSMI_EVENT_DRIVER_DIAG_DATA_INIT_FAIL,
1250  AMDSMI_EVENT_DRIVER_DIAG_DATA_MEM_REQ_FAIL,
1251  AMDSMI_EVENT_DRIVER_DIAG_DATA_VADDR_REQ_FAIL,
1252  AMDSMI_EVENT_DRIVER_DIAG_DATA_BUS_ADDR_REQ_FAIL,
1253 
1254  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_INIT_FAIL,
1255  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_MEM_REQ_FAIL,
1256  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_VADDR_REQ_FAIL,
1257  AMDSMI_EVENT_DRIVER_REMOTE_DEBUG_BUS_ADDR_REQ_FAIL,
1258 
1259  AMDSMI_EVENT_DRIVER_HRTIMER_START_FAIL,
1260  AMDSMI_EVENT_DRIVER_CREATE_DRIVER_FILE_FAIL,
1261  AMDSMI_EVENT_DRIVER_CREATE_DEVICE_FILE_FAIL,
1262  AMDSMI_EVENT_DRIVER_CREATE_DEBUGFS_FILE_FAIL,
1263  AMDSMI_EVENT_DRIVER_CREATE_DEBUGFS_DIR_FAIL,
1264 
1265  AMDSMI_EVENT_DRIVER_PCI_ENABLE_DEVICE_FAIL,
1266  AMDSMI_EVENT_DRIVER_FB_MAP_FAIL,
1267  AMDSMI_EVENT_DRIVER_DOORBELL_MAP_FAIL,
1268  AMDSMI_EVENT_DRIVER_PCI_REGISTER_DRIVER_FAIL,
1269 
1270  AMDSMI_EVENT_DRIVER_ALLOC_IOVA_ALIGN_FAIL,
1271 
1272  AMDSMI_EVENT_DRIVER_ROM_MAP_FAIL,
1273  AMDSMI_EVENT_DRIVER_FULL_ACCESS_TIMEOUT,
1274 
1275  AMDSMI_EVENT_DRIVER__MAX
1276 } amdsmi_event_driver_t;
1277 
1283 typedef enum {
1284  AMDSMI_EVENT_FW_CMD_ALLOC_BUF_FAIL = 0,
1285  AMDSMI_EVENT_FW_CMD_BUF_PREP_FAIL,
1286  AMDSMI_EVENT_FW_RING_INIT_FAIL,
1287  AMDSMI_EVENT_FW_FW_APPLY_SECURITY_POLICY_FAIL,
1288  AMDSMI_EVENT_FW_START_RING_FAIL,
1289 
1290  AMDSMI_EVENT_FW_FW_LOAD_FAIL,
1291  AMDSMI_EVENT_FW_EXIT_FAIL,
1292  AMDSMI_EVENT_FW_INIT_FAIL,
1293  AMDSMI_EVENT_FW_CMD_SUBMIT_FAIL,
1294  AMDSMI_EVENT_FW_CMD_FENCE_WAIT_FAIL,
1295 
1296  AMDSMI_EVENT_FW_TMR_LOAD_FAIL,
1297  AMDSMI_EVENT_FW_TOC_LOAD_FAIL,
1298  AMDSMI_EVENT_FW_RAS_LOAD_FAIL,
1299  AMDSMI_EVENT_FW_RAS_UNLOAD_FAIL,
1300  AMDSMI_EVENT_FW_RAS_TA_INVOKE_FAIL,
1301  AMDSMI_EVENT_FW_RAS_TA_ERR_INJECT_FAIL,
1302 
1303  AMDSMI_EVENT_FW_ASD_LOAD_FAIL,
1304  AMDSMI_EVENT_FW_ASD_UNLOAD_FAIL,
1305  AMDSMI_EVENT_FW_AUTOLOAD_FAIL,
1306  AMDSMI_EVENT_FW_VFGATE_FAIL,
1307 
1308  AMDSMI_EVENT_FW_XGMI_LOAD_FAIL,
1309  AMDSMI_EVENT_FW_XGMI_UNLOAD_FAIL,
1310  AMDSMI_EVENT_FW_XGMI_TA_INVOKE_FAIL,
1311 
1312  AMDSMI_EVENT_FW_TMR_INIT_FAIL,
1313  AMDSMI_EVENT_FW_NOT_SUPPORTED_FEATURE,
1314  AMDSMI_EVENT_FW_GET_PSP_TRACELOG_FAIL,
1315 
1316  AMDSMI_EVENT_FW_SET_SNAPSHOT_ADDR_FAIL,
1317  AMDSMI_EVENT_FW_SNAPSHOT_TRIGGER_FAIL,
1318 
1319  AMDSMI_EVENT_FW_MIGRATION_GET_PSP_INFO_FAIL,
1320  AMDSMI_EVENT_FW_MIGRATION_EXPORT_FAIL,
1321  AMDSMI_EVENT_FW_MIGRATION_IMPORT_FAIL,
1322 
1323  AMDSMI_EVENT_FW_BL_FAIL,
1324  AMDSMI_EVENT_FW_RAS_BOOT_FAIL,
1325  AMDSMI_EVENT_FW_MAILBOX_ERROR,
1326 
1327  AMDSMI_EVENT_FW__MAX
1328 } amdsmi_event_fw_t;
1329 
1330 #define AMDSMI_EVENT_FW_FW_INIT_FAIL AMDSMI_EVENT_FW_RING_INIT_FAIL
1331 
1337 typedef enum {
1338  AMDSMI_EVENT_RESET_GPU = 0,
1339  AMDSMI_EVENT_RESET_GPU_FAILED,
1340  AMDSMI_EVENT_RESET_FLR,
1341  AMDSMI_EVENT_RESET_FLR_FAILED,
1342  AMDSMI_EVENT_RESET__MAX
1343 } amdsmi_event_reset_t;
1344 
1350 typedef enum {
1351  AMDSMI_EVENT_IOV_NO_GPU_IOV_CAP = 0,
1352  AMDSMI_EVENT_IOV_ASIC_NO_SRIOV_SUPPORT,
1353  AMDSMI_EVENT_IOV_ENABLE_SRIOV_FAIL,
1354  AMDSMI_EVENT_IOV_CMD_TIMEOUT,
1355  AMDSMI_EVENT_IOV_CMD_ERROR,
1356 
1357  AMDSMI_EVENT_IOV_INIT_IV_RING_FAIL,
1358  AMDSMI_EVENT_IOV_SRIOV_STRIDE_ERROR,
1359  AMDSMI_EVENT_IOV_WS_SAVE_TIMEOUT,
1360  AMDSMI_EVENT_IOV_WS_IDLE_TIMEOUT,
1361  AMDSMI_EVENT_IOV_WS_RUN_TIMEOUT,
1362  AMDSMI_EVENT_IOV_WS_LOAD_TIMEOUT,
1363  AMDSMI_EVENT_IOV_WS_SHUTDOWN_TIMEOUT,
1364  AMDSMI_EVENT_IOV_WS_ALREADY_SHUTDOWN,
1365  AMDSMI_EVENT_IOV_WS_INFINITE_LOOP,
1366  AMDSMI_EVENT_IOV_WS_REENTRANT_ERROR,
1367  AMDSMI_EVENT_IOV__MAX
1368 } amdsmi_event_iov_t;
1369 
1375 typedef enum {
1376  AMDSMI_EVENT_ECC_UCE = 0,
1377  AMDSMI_EVENT_ECC_CE,
1378  AMDSMI_EVENT_ECC_IN_PF_FB,
1379  AMDSMI_EVENT_ECC_IN_CRI_REG,
1380  AMDSMI_EVENT_ECC_IN_VF_CRI,
1381  AMDSMI_EVENT_ECC_REACH_THD,
1382  AMDSMI_EVENT_ECC_VF_CE,
1383  AMDSMI_EVENT_ECC_VF_UE,
1384  AMDSMI_EVENT_ECC_IN_SAME_ROW,
1385  AMDSMI_EVENT_ECC_UMC_UE,
1386  AMDSMI_EVENT_ECC_GFX_CE,
1387  AMDSMI_EVENT_ECC_GFX_UE,
1388  AMDSMI_EVENT_ECC_SDMA_CE,
1389  AMDSMI_EVENT_ECC_SDMA_UE,
1390  AMDSMI_EVENT_ECC_GFX_CE_TOTAL,
1391  AMDSMI_EVENT_ECC_GFX_UE_TOTAL,
1392  AMDSMI_EVENT_ECC_SDMA_CE_TOTAL,
1393  AMDSMI_EVENT_ECC_SDMA_UE_TOTAL,
1394  AMDSMI_EVENT_ECC_UMC_CE_TOTAL,
1395  AMDSMI_EVENT_ECC_UMC_UE_TOTAL,
1396  AMDSMI_EVENT_ECC_MMHUB_CE,
1397  AMDSMI_EVENT_ECC_MMHUB_UE,
1398  AMDSMI_EVENT_ECC_MMHUB_CE_TOTAL,
1399  AMDSMI_EVENT_ECC_MMHUB_UE_TOTAL,
1400  AMDSMI_EVENT_ECC_XGMI_WAFL_CE,
1401  AMDSMI_EVENT_ECC_XGMI_WAFL_UE,
1402  AMDSMI_EVENT_ECC_XGMI_WAFL_CE_TOTAL,
1403  AMDSMI_EVENT_ECC_XGMI_WAFL_UE_TOTAL,
1404  AMDSMI_EVENT_ECC_FATAL_ERROR,
1405  AMDSMI_EVENT_ECC_POISON_CONSUMPTION,
1406  AMDSMI_EVENT_ECC_ACA_DUMP,
1407  AMDSMI_EVENT_ECC_WRONG_SOCKET_ID,
1408  AMDSMI_EVENT_ECC_ACA_UNKNOWN_BLOCK_INSTANCE,
1409  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_CE,
1410  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_UE,
1411  AMDSMI_EVENT_ECC_UMC_CHIPLET_CE,
1412  AMDSMI_EVENT_ECC_UMC_CHIPLET_UE,
1413  AMDSMI_EVENT_ECC_GFX_CHIPLET_CE,
1414  AMDSMI_EVENT_ECC_GFX_CHIPLET_UE,
1415  AMDSMI_EVENT_ECC_SDMA_CHIPLET_CE,
1416  AMDSMI_EVENT_ECC_SDMA_CHIPLET_UE,
1417  AMDSMI_EVENT_ECC_MMHUB_CHIPLET_CE,
1418  AMDSMI_EVENT_ECC_MMHUB_CHIPLET_UE,
1419  AMDSMI_EVENT_ECC_XGMI_WAFL_CHIPLET_CE,
1420  AMDSMI_EVENT_ECC_XGMI_WAFL_CHIPLET_UE,
1421  AMDSMI_EVENT_ECC_EEPROM_ENTRIES_FOUND,
1422  AMDSMI_EVENT_ECC_UMC_DE,
1423  AMDSMI_EVENT_ECC_UMC_DE_TOTAL,
1424  AMDSMI_EVENT_ECC_UNKNOWN,
1425  AMDSMI_EVENT_ECC_EEPROM_REACH_THD,
1426  AMDSMI_EVENT_ECC_UMC_CHIPLET_DE,
1427  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_DE,
1428  AMDSMI_EVENT_ECC_EEPROM_CHK_MISMATCH,
1429  AMDSMI_EVENT_ECC_EEPROM_RESET,
1430  AMDSMI_EVENT_ECC_EEPROM_RESET_FAILED,
1431  AMDSMI_EVENT_ECC_EEPROM_APPEND,
1432  AMDSMI_EVENT_ECC_THD_CHANGED,
1433  AMDSMI_EVENT_ECC_DUP_ENTRIES,
1434  AMDSMI_EVENT_ECC_EEPROM_WRONG_HDR,
1435  AMDSMI_EVENT_ECC_EEPROM_WRONG_VER,
1436  AMDSMI_EVENT_ECC__MAX
1437 } amdsmi_event_ecc_t;
1438 
1444 typedef enum {
1445  AMDSMI_EVENT_PP_SET_DPM_POLICY_FAIL = 0,
1446  AMDSMI_EVENT_PP_ACTIVATE_DPM_POLICY_FAIL,
1447  AMDSMI_EVENT_PP_I2C_SLAVE_NOT_PRESENT,
1448  AMDSMI_EVENT_PP_THROTTLER_EVENT,
1449  AMDSMI_EVENT_PP__MAX
1450 } amdsmi_event_pp_t;
1451 
1457 typedef enum {
1458  AMDSMI_EVENT_SCHED_WORLD_SWITCH_FAIL = 0,
1459  AMDSMI_EVENT_SCHED_DISABLE_AUTO_HW_SWITCH_FAIL,
1460  AMDSMI_EVENT_SCHED_ENABLE_AUTO_HW_SWITCH_FAIL,
1461  AMDSMI_EVENT_SCHED_GFX_SAVE_REG_FAIL,
1462  AMDSMI_EVENT_SCHED_GFX_IDLE_REG_FAIL,
1463 
1464  AMDSMI_EVENT_SCHED_GFX_RUN_REG_FAIL,
1465  AMDSMI_EVENT_SCHED_GFX_LOAD_REG_FAIL,
1466  AMDSMI_EVENT_SCHED_GFX_INIT_REG_FAIL,
1467  AMDSMI_EVENT_SCHED_MM_SAVE_REG_FAIL,
1468  AMDSMI_EVENT_SCHED_MM_IDLE_REG_FAIL,
1469 
1470  AMDSMI_EVENT_SCHED_MM_RUN_REG_FAIL,
1471  AMDSMI_EVENT_SCHED_MM_LOAD_REG_FAIL,
1472  AMDSMI_EVENT_SCHED_MM_INIT_REG_FAIL,
1473  AMDSMI_EVENT_SCHED_INIT_GPU_FAIL,
1474  AMDSMI_EVENT_SCHED_RUN_GPU_FAIL,
1475 
1476  AMDSMI_EVENT_SCHED_SAVE_GPU_STATE_FAIL,
1477  AMDSMI_EVENT_SCHED_LOAD_GPU_STATE_FAIL,
1478  AMDSMI_EVENT_SCHED_IDLE_GPU_FAIL,
1479  AMDSMI_EVENT_SCHED_FINI_GPU_FAIL,
1480  AMDSMI_EVENT_SCHED_DEAD_VF,
1481 
1482  AMDSMI_EVENT_SCHED_EVENT_QUEUE_FULL,
1483  AMDSMI_EVENT_SCHED_SHUTDOWN_VF_FAIL,
1484  AMDSMI_EVENT_SCHED_RESET_VF_NUM_FAIL,
1485  AMDSMI_EVENT_SCHED_IGNORE_EVENT,
1486  AMDSMI_EVENT_SCHED_PF_SWITCH_FAIL,
1487  AMDSMI_EVENT_SCHED__MAX
1488 } amdsmi_event_sched_t;
1489 
1495 typedef enum {
1496  AMDSMI_EVENT_VF_ATOMBIOS_INIT_FAIL = 0,
1497  AMDSMI_EVENT_VF_NO_VBIOS,
1498  AMDSMI_EVENT_VF_GPU_POST_ERROR,
1499  AMDSMI_EVENT_VF_ATOMBIOS_GET_CLOCK_FAIL,
1500  AMDSMI_EVENT_VF_FENCE_INIT_FAIL,
1501  AMDSMI_EVENT_VF_AMDGPU_INIT_FAIL,
1502  AMDSMI_EVENT_VF_IB_INIT_FAIL,
1503  AMDSMI_EVENT_VF_AMDGPU_LATE_INIT_FAIL,
1504  AMDSMI_EVENT_VF_ASIC_RESUME_FAIL,
1505  AMDSMI_EVENT_VF_GPU_RESET_FAIL,
1506  AMDSMI_EVENT_VF__MAX
1507 } amdsmi_event_vf_max_t;
1508 
1514 typedef enum {
1515  AMDSMI_EVENT_VBIOS_INVALID = 0,
1516  AMDSMI_EVENT_VBIOS_IMAGE_MISSING,
1517  AMDSMI_EVENT_VBIOS_CHECKSUM_ERR,
1518  AMDSMI_EVENT_VBIOS_POST_FAIL,
1519  AMDSMI_EVENT_VBIOS_READ_FAIL,
1520 
1521  AMDSMI_EVENT_VBIOS_READ_IMG_HEADER_FAIL,
1522  AMDSMI_EVENT_VBIOS_READ_IMG_SIZE_FAIL,
1523  AMDSMI_EVENT_VBIOS_GET_FW_INFO_FAIL,
1524  AMDSMI_EVENT_VBIOS_GET_TBL_REVISION_FAIL,
1525  AMDSMI_EVENT_VBIOS_PARSER_TBL_FAIL,
1526 
1527  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_FAIL,
1528  AMDSMI_EVENT_VBIOS_TIMEOUT,
1529  AMDSMI_EVENT_VBIOS_HASH_INVALID,
1530  AMDSMI_EVENT_VBIOS_HASH_UPDATED,
1531  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_BINARY_CHECKSUM_FAIL,
1532  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_TABLE_CHECKSUM_FAIL,
1533  AMDSMI_EVENT_VBIOS__MAX
1534 } amdsmi_event_vbios_t;
1535 
1541 typedef enum {
1542  AMDSMI_EVENT_GUARD_RESET_FAIL = 0,
1543  AMDSMI_EVENT_GUARD_EVENT_OVERFLOW,
1544  AMDSMI_EVENT_GUARD__MAX
1545 } amdsmi_event_guard_t;
1546 
1552 typedef enum {
1553  AMDSMI_EVENT_GPUMON_INVALID_OPTION = 0,
1554  AMDSMI_EVENT_GPUMON_INVALID_VF_INDEX,
1555  AMDSMI_EVENT_GPUMON_INVALID_FB_SIZE,
1556  AMDSMI_EVENT_GPUMON_NO_SUITABLE_SPACE,
1557  AMDSMI_EVENT_GPUMON_NO_AVAILABLE_SLOT,
1558 
1559  AMDSMI_EVENT_GPUMON_OVERSIZE_ALLOCATION,
1560  AMDSMI_EVENT_GPUMON_OVERLAPPING_FB,
1561  AMDSMI_EVENT_GPUMON_INVALID_GFX_TIMESLICE,
1562  AMDSMI_EVENT_GPUMON_INVALID_MM_TIMESLICE,
1563  AMDSMI_EVENT_GPUMON_INVALID_GFX_PART,
1564 
1565  AMDSMI_EVENT_GPUMON_VF_BUSY,
1566  AMDSMI_EVENT_GPUMON_INVALID_VF_NUM,
1567  AMDSMI_EVENT_GPUMON_NOT_SUPPORTED,
1568  AMDSMI_EVENT_GPUMON__MAX
1569 } amdsmi_event_gpumon_t;
1570 
1576 typedef enum {
1577  AMDSMI_EVENT_MMSCH_IGNORED_JOB = 0,
1578  AMDSMI_EVENT_MMSCH_UNSUPPORTED_VCN_FW,
1579  AMDSMI_EVENT_MMSCH__MAX
1580 } amdsmi_event_mmsch_t;
1581 
1587 typedef enum {
1588  AMDSMI_EVENT_XGMI_TOPOLOGY_UPDATE_FAILED = 0,
1589  AMDSMI_EVENT_XGMI_TOPOLOGY_HW_INIT_UPDATE,
1590  AMDSMI_EVENT_XGMI_TOPOLOGY_UPDATE_DONE,
1591  AMDSMI_EVENT_XGMI_FB_SHARING_SETTING_ERROR,
1592  AMDSMI_EVENT_XGMI_FB_SHARING_SETTING_RESET,
1593  AMDSMI_EVENT_XGMI__MAX
1594 } amdsmi_event_xgmi_t;
1595 
1608 typedef enum {
1609  AMDSMI_EVENT_THROTTLER_PROCHOT = (1 << 0),
1610  AMDSMI_EVENT_THROTTLER_SOCKET = (1 << 2),
1611  AMDSMI_EVENT_THROTTLER_VR = (1 << 3),
1612  AMDSMI_EVENT_THROTTLER_HBM = (1 << 4)
1613 } amdsmi_pp_throttler_type_t;
1614 
1620 typedef enum {
1621  AMDSMI_RAS_ECC_SUPPORT_PARITY = (1 << 0),
1622  AMDSMI_RAS_ECC_SUPPORT_CORRECTABLE = (1 << 1),
1623  AMDSMI_RAS_ECC_SUPPORT_UNCORRECTABLE = (1 << 2),
1624  AMDSMI_RAS_ECC_SUPPORT_POISON = (1 << 3)
1625 } amdsmi_ecc_correction_schema_support_t;
1626 
1632 typedef enum {
1633  AMDSMI_GUEST_FW_ID_VCE = 0,
1634  AMDSMI_GUEST_FW_ID_UVD,
1635  AMDSMI_GUEST_FW_ID_MC,
1636  AMDSMI_GUEST_FW_ID_ME,
1637  AMDSMI_GUEST_FW_ID_PFP,
1638  AMDSMI_GUEST_FW_ID_CE,
1639  AMDSMI_GUEST_FW_ID_RLC,
1640  AMDSMI_GUEST_FW_ID_RLC_SRLC,
1641  AMDSMI_GUEST_FW_ID_RLC_SRLG,
1642  AMDSMI_GUEST_FW_ID_RLC_SRLS,
1643  AMDSMI_GUEST_FW_ID_MEC,
1644  AMDSMI_GUEST_FW_ID_MEC2,
1645  AMDSMI_GUEST_FW_ID_SOS,
1646  AMDSMI_GUEST_FW_ID_ASD,
1647  AMDSMI_GUEST_FW_ID_TA_RAS,
1648  AMDSMI_GUEST_FW_ID_TA_XGMI,
1649  AMDSMI_GUEST_FW_ID_SMC,
1650  AMDSMI_GUEST_FW_ID_SDMA,
1651  AMDSMI_GUEST_FW_ID_SDMA2,
1652  AMDSMI_GUEST_FW_ID_VCN,
1653  AMDSMI_GUEST_FW_ID_DMCU,
1654  AMDSMI_GUEST_FW_ID__MAX
1655 } amdsmi_guest_fw_engine_id_t;
1656 
1662 typedef enum {
1663  AMDSMI_VF_CONFIG_FB_SIZE_SET = 0,
1664  AMDSMI_VF_CONFIG_FB_OFFSET_SET,
1665  AMDSMI_VF_CONFIG_GFX_TIMESLICE_US_SET,
1666  AMDSMI_VF_CONFIG_ENG_COMPUTE_BW_SET,
1667  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_FLR_SET,
1668  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_EXCL_MOD_SET,
1669  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_EXCL_TIMEOUT_SET,
1670  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_ALL_INT_SET,
1671  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_UVD_SET,
1672  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCE_SET,
1673  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_UVD1_SET,
1674  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCN_SET,
1675  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCN1_SET,
1676  AMDSMI_VF_CONFIG__MAX
1677 } amdsmi_vf_config_flags_t;
1678 
1684 typedef enum {
1685  AMDSMI_VF_STATE_UNAVAILABLE,
1686  AMDSMI_VF_STATE_AVAILABLE,
1687  AMDSMI_VF_STATE_ACTIVE,
1688  AMDSMI_VF_STATE_SUSPENDED,
1689  AMDSMI_VF_STATE_FULLACCESS,
1690  AMDSMI_VF_STATE_DEFAULT_AVAILABLE,
1691 } amdsmi_vf_sched_state_t;
1692 
1698 typedef enum {
1699  AMDSMI_GUARD_EVENT_FLR,
1700  AMDSMI_GUARD_EVENT_EXCLUSIVE_MOD,
1701  AMDSMI_GUARD_EVENT_EXCLUSIVE_TIMEOUT,
1702  AMDSMI_GUARD_EVENT_ALL_INT,
1703  AMDSMI_GUARD_EVENT_RAS_ERR_COUNT,
1704  AMDSMI_GUARD_EVENT_RAS_CPER_DUMP,
1705  AMDSMI_GUARD_EVENT_RAS_BAD_PAGES,
1706  AMDSMI_GUARD_EVENT__MAX
1707 } amdsmi_guard_type_t;
1708 
1714 typedef enum {
1715  AMDSMI_DRIVER_LIBGV,
1716  AMDSMI_DRIVER_KMD,
1717  AMDSMI_DRIVER_AMDGPUV,
1718  AMDSMI_DRIVER_AMDGPU,
1719  AMDSMI_DRIVER_VMWGPUV,
1720  AMDSMI_DRIVER__MAX,
1721 } amdsmi_driver_t;
1722 
1728 typedef enum {
1729  AMDSMI_GUARD_STATE_NORMAL = 0,
1730  AMDSMI_GUARD_STATE_FULL = 1,
1731  AMDSMI_GUARD_STATE_OVERFLOW = 2,
1732 } amdsmi_guard_state_t;
1733 
1739 typedef enum {
1740  AMDSMI_SCHED_BLOCK_GFX = 0x0,
1741  AMDSMI_SCHED_BLOCK_UVD = 0x1,
1742  AMDSMI_SCHED_BLOCK_VCE = 0x2,
1743  AMDSMI_SCHED_BLOCK_UVD1 = 0x3,
1744  AMDSMI_SCHED_BLOCK_VCN = 0x4,
1745  AMDSMI_SCHED_BLOCK_VCN1 = 0x5,
1746 } amdsmi_sched_block_t;
1747 
1753 typedef enum {
1754  AMDSMI_GUEST_FW_LOAD_STATUS_OK = 0,
1755  AMDSMI_GUEST_FW_LOAD_STATUS_OBSOLETE_FW = 1,
1756  AMDSMI_GUEST_FW_LOAD_STATUS_BAD_SIG = 2,
1757  AMDSMI_GUEST_FW_LOAD_STATUS_FW_LOAD_FAIL = 3,
1758  AMDSMI_GUEST_FW_LOAD_STATUS_ERR_GENERIC = 4
1759 } amdsmi_guest_fw_load_status_t;
1760 
1766 typedef enum {
1767  AMDSMI_XGMI_FB_SHARING_MODE_CUSTOM = 0,
1768  AMDSMI_XGMI_FB_SHARING_MODE_1 = 1,
1769  AMDSMI_XGMI_FB_SHARING_MODE_2 = 2,
1770  AMDSMI_XGMI_FB_SHARING_MODE_4 = 4,
1771  AMDSMI_XGMI_FB_SHARING_MODE_8 = 8,
1772  AMDSMI_XGMI_FB_SHARING_MODE_UNKNOWN = 0xFFFFFFFF
1773 } amdsmi_xgmi_fb_sharing_mode_t;
1774 
1780 typedef enum {
1781  AMDSMI_PROFILE_CAPABILITY_MEMORY = 0,
1782  AMDSMI_PROFILE_CAPABILITY_ENCODE = 1,
1783  AMDSMI_PROFILE_CAPABILITY_DECODE = 2,
1784  AMDSMI_PROFILE_CAPABILITY_COMPUTE = 3,
1785  AMDSMI_PROFILE_CAPABILITY__MAX,
1786 } amdsmi_profile_capability_type_t;
1787 
1793 typedef enum {
1794  AMDSMI_METRIC_CATEGORY_ACC_COUNTER,
1795  AMDSMI_METRIC_CATEGORY_FREQUENCY,
1796  AMDSMI_METRIC_CATEGORY_ACTIVITY,
1797  AMDSMI_METRIC_CATEGORY_TEMPERATURE,
1798  AMDSMI_METRIC_CATEGORY_POWER,
1799  AMDSMI_METRIC_CATEGORY_ENERGY,
1800  AMDSMI_METRIC_CATEGORY_THROTTLE,
1801  AMDSMI_METRIC_CATEGORY_PCIE,
1802  AMDSMI_METRIC_CATEGORY_STATIC,
1803  AMDSMI_METRIC_CATEGORY_SYS_ACC_COUNTER,
1804  AMDSMI_METRIC_CATEGORY_SYS_BASEBOARD_TEMP,
1805  AMDSMI_METRIC_CATEGORY_SYS_GPUBOARD_TEMP,
1806  AMDSMI_METRIC_CATEGORY_UNKNOWN
1807 } amdsmi_metric_category_t;
1808 
1814 typedef enum {
1815  AMDSMI_METRIC_NAME_METRIC_ACC_COUNTER,
1816  AMDSMI_METRIC_NAME_FW_TIMESTAMP,
1817  AMDSMI_METRIC_NAME_CLK_GFX,
1818  AMDSMI_METRIC_NAME_CLK_SOC,
1819  AMDSMI_METRIC_NAME_CLK_MEM,
1820  AMDSMI_METRIC_NAME_CLK_VCLK,
1821  AMDSMI_METRIC_NAME_CLK_DCLK,
1822 
1823  AMDSMI_METRIC_NAME_USAGE_GFX,
1824  AMDSMI_METRIC_NAME_USAGE_MEM,
1825  AMDSMI_METRIC_NAME_USAGE_MM,
1826  AMDSMI_METRIC_NAME_USAGE_VCN,
1827  AMDSMI_METRIC_NAME_USAGE_JPEG,
1828 
1829  AMDSMI_METRIC_NAME_VOLT_GFX,
1830  AMDSMI_METRIC_NAME_VOLT_SOC,
1831  AMDSMI_METRIC_NAME_VOLT_MEM,
1832 
1833  AMDSMI_METRIC_NAME_TEMP_HOTSPOT_CURR,
1834  AMDSMI_METRIC_NAME_TEMP_HOTSPOT_LIMIT,
1835  AMDSMI_METRIC_NAME_TEMP_MEM_CURR,
1836  AMDSMI_METRIC_NAME_TEMP_MEM_LIMIT,
1837  AMDSMI_METRIC_NAME_TEMP_VR_CURR,
1838  AMDSMI_METRIC_NAME_TEMP_SHUTDOWN,
1839 
1840  AMDSMI_METRIC_NAME_POWER_CURR,
1841  AMDSMI_METRIC_NAME_POWER_LIMIT,
1842 
1843  AMDSMI_METRIC_NAME_ENERGY_SOCKET,
1844  AMDSMI_METRIC_NAME_ENERGY_CCD,
1845  AMDSMI_METRIC_NAME_ENERGY_XCD,
1846  AMDSMI_METRIC_NAME_ENERGY_AID,
1847  AMDSMI_METRIC_NAME_ENERGY_MEM,
1848 
1849  AMDSMI_METRIC_NAME_THROTTLE_SOCKET_ACTIVE,
1850  AMDSMI_METRIC_NAME_THROTTLE_VR_ACTIVE,
1851  AMDSMI_METRIC_NAME_THROTTLE_MEM_ACTIVE,
1852 
1853  AMDSMI_METRIC_NAME_PCIE_BANDWIDTH,
1854  AMDSMI_METRIC_NAME_PCIE_L0_TO_RECOVERY_COUNT,
1855  AMDSMI_METRIC_NAME_PCIE_REPLAY_COUNT,
1856  AMDSMI_METRIC_NAME_PCIE_REPLAY_ROLLOVER_COUNT,
1857  AMDSMI_METRIC_NAME_PCIE_NAK_SENT_COUNT,
1858  AMDSMI_METRIC_NAME_PCIE_NAK_RECEIVED_COUNT,
1859 
1860  AMDSMI_METRIC_NAME_CLK_GFX_MAX_LIMIT,
1861  AMDSMI_METRIC_NAME_CLK_SOC_MAX_LIMIT,
1862  AMDSMI_METRIC_NAME_CLK_MEM_MAX_LIMIT,
1863  AMDSMI_METRIC_NAME_CLK_VCLK_MAX_LIMIT,
1864  AMDSMI_METRIC_NAME_CLK_DCLK_MAX_LIMIT,
1865 
1866  AMDSMI_METRIC_NAME_CLK_GFX_MIN_LIMIT,
1867  AMDSMI_METRIC_NAME_CLK_SOC_MIN_LIMIT,
1868  AMDSMI_METRIC_NAME_CLK_MEM_MIN_LIMIT,
1869  AMDSMI_METRIC_NAME_CLK_VCLK_MIN_LIMIT,
1870  AMDSMI_METRIC_NAME_CLK_DCLK_MIN_LIMIT,
1871 
1872  AMDSMI_METRIC_NAME_CLK_GFX_LOCKED,
1873 
1874  AMDSMI_METRIC_NAME_CLK_GFX_DS_DISABLED,
1875  AMDSMI_METRIC_NAME_CLK_MEM_DS_DISABLED,
1876  AMDSMI_METRIC_NAME_CLK_SOC_DS_DISABLED,
1877  AMDSMI_METRIC_NAME_CLK_VCLK_DS_DISABLED,
1878  AMDSMI_METRIC_NAME_CLK_DCLK_DS_DISABLED,
1879 
1880  AMDSMI_METRIC_NAME_PCIE_LINK_SPEED,
1881  AMDSMI_METRIC_NAME_PCIE_LINK_WIDTH,
1882 
1883  AMDSMI_METRIC_NAME_DRAM_BANDWIDTH,
1884  AMDSMI_METRIC_NAME_MAX_DRAM_BANDWIDTH,
1885 
1886  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_PPT,
1887  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_THM,
1888  AMDSMI_METRIC_NAME_GFX_CLK_BELOW_HOST_LIMIT_TOTAL,
1889  AMDSMI_METRIC_NAME_GFX_CLK_LOW_UTILIZATION,
1890  AMDSMI_METRIC_NAME_INPUT_TELEMETRY_VOLTAGE,
1891  AMDSMI_METRIC_NAME_PLDM_VERSION,
1892  AMDSMI_METRIC_NAME_TEMP_XCD,
1893  AMDSMI_METRIC_NAME_TEMP_AID,
1894  AMDSMI_METRIC_NAME_TEMP_HBM,
1895 
1896  AMDSMI_METRIC_NAME_SYS_METRIC_ACC_COUNTER,
1897  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA,
1898  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FRONT,
1899  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_BACK,
1900  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_OAM7,
1901  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_IBC,
1902  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_UFPGA,
1903  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_OAM1,
1904  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_0_1_HSC,
1905  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_2_3_HSC,
1906  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_4_5_HSC,
1907  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_6_7_HSC,
1908  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA_0V72_VR,
1909  AMDSMI_METRIC_NAME_SYSTEM_TEMP_UBB_FPGA_3V3_VR,
1910  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR,
1911  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR,
1912  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_0_1_0V9_VR,
1913  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_4_5_0V9_VR,
1914  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_2_3_0V9_VR,
1915  AMDSMI_METRIC_NAME_SYSTEM_TEMP_RETIMER_6_7_0V9_VR,
1916  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR,
1917  AMDSMI_METRIC_NAME_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR,
1918  AMDSMI_METRIC_NAME_SYSTEM_TEMP_IBC_HSC,
1919  AMDSMI_METRIC_NAME_SYSTEM_TEMP_IBC,
1920  AMDSMI_METRIC_NAME_NODE_TEMP_RETIMER,
1921  AMDSMI_METRIC_NAME_NODE_TEMP_IBC_TEMP,
1922  AMDSMI_METRIC_NAME_NODE_TEMP_IBC_2_TEMP,
1923  AMDSMI_METRIC_NAME_NODE_TEMP_VDD18_VR_TEMP,
1924  AMDSMI_METRIC_NAME_NODE_TEMP_04_HBM_B_VR_TEMP,
1925  AMDSMI_METRIC_NAME_NODE_TEMP_04_HBM_D_VR_TEMP,
1926  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD0,
1927  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD1,
1928  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD2,
1929  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_VDD3,
1930  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOC_A,
1931  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOC_C,
1932  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOCIO_A,
1933  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_SOCIO_C,
1934  AMDSMI_METRIC_NAME_VR_TEMP_VDD_085_HBM,
1935  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_11_HBM_B,
1936  AMDSMI_METRIC_NAME_VR_TEMP_VDDCR_11_HBM_D,
1937  AMDSMI_METRIC_NAME_VR_TEMP_VDD_USR,
1938  AMDSMI_METRIC_NAME_VR_TEMP_VDDIO_11_E32,
1939 
1940  AMDSMI_METRIC_NAME_UNKNOWN
1941 } amdsmi_metric_name_t;
1942 
1948 typedef enum {
1949  AMDSMI_METRIC_UNIT_COUNTER,
1950  AMDSMI_METRIC_UNIT_UINT,
1951  AMDSMI_METRIC_UNIT_BOOL,
1952  AMDSMI_METRIC_UNIT_MHZ,
1953  AMDSMI_METRIC_UNIT_PERCENT,
1954  AMDSMI_METRIC_UNIT_MILLIVOLT,
1955  AMDSMI_METRIC_UNIT_CELSIUS,
1956  AMDSMI_METRIC_UNIT_WATT,
1957  AMDSMI_METRIC_UNIT_JOULE,
1958  AMDSMI_METRIC_UNIT_GBPS,
1959  AMDSMI_METRIC_UNIT_MBITPS,
1960  AMDSMI_METRIC_UNIT_PCIE_GEN,
1961  AMDSMI_METRIC_UNIT_PCIE_LANES,
1962  AMDSMI_METRIC_UNIT_15_625_MILLIJOULE,
1963  AMDSMI_METRIC_UNIT_UNKNOWN
1964 } amdsmi_metric_unit_t;
1965 
1971 typedef enum {
1972  AMDSMI_METRIC_TYPE_COUNTER = (1 << 0),
1973  AMDSMI_METRIC_TYPE_CHIPLET = (1 << 1),
1974  AMDSMI_METRIC_TYPE_INST = (1 << 2),
1975  AMDSMI_METRIC_TYPE_ACC = (1 << 3)
1976 } amdsmi_metric_type_t;
1977 
1978 typedef enum {
1979  AMDSMI_METRIC_RES_GROUP_UNKNOWN,
1980  AMDSMI_METRIC_RES_GROUP_NA,
1981  AMDSMI_METRIC_RES_GROUP_GPU,
1982  AMDSMI_METRIC_RES_GROUP_XCP,
1983  AMDSMI_METRIC_RES_GROUP_AID,
1984  AMDSMI_METRIC_RES_GROUP_MID,
1985  AMDSMI_METRIC_RES_GROUP_SYSTEM
1986 } amdsmi_metric_res_group_t;
1987 
1988 typedef enum {
1989  AMDSMI_METRIC_RES_SUBGROUP_UNKNOWN,
1990  AMDSMI_METRIC_RES_SUBGROUP_NA,
1991  AMDSMI_METRIC_RES_SUBGROUP_XCC,
1992  AMDSMI_METRIC_RES_SUBGROUP_ENGINE,
1993  AMDSMI_METRIC_RES_SUBGROUP_HBM,
1994  AMDSMI_METRIC_RES_SUBGROUP_BASEBOARD,
1995  AMDSMI_METRIC_RES_SUBGROUP_GPUBOARD
1996 } amdsmi_metric_res_subgroup_t;
1997 
1998 typedef enum {
1999  AMDSMI_VF_MODE_1 = (1U << 1),
2000  AMDSMI_VF_MODE_2 = (1U << 2),
2001  AMDSMI_VF_MODE_4 = (1U << 4),
2002  AMDSMI_VF_MODE_8 = (1U << 8),
2003  AMDSMI_VF_MODE_ALL = (AMDSMI_VF_MODE_1 | AMDSMI_VF_MODE_2 | AMDSMI_VF_MODE_4 | AMDSMI_VF_MODE_8)
2004 } amdsmi_vf_mode_t;
2005 
2011 typedef enum {
2012  AMDSMI_DRIVER_MODEL_TYPE_WDDM = 0,
2013  AMDSMI_DRIVER_MODEL_TYPE_WDM = 1,
2014  AMDSMI_DRIVER_MODEL_TYPE_MCDM = 2,
2015  AMDSMI_DRIVER_MODEL_TYPE__MAX = 3,
2016 } amdsmi_driver_model_type_t;
2017 
2023 typedef struct {
2024  uint64_t handle;
2025 } amdsmi_vf_handle_t;
2026 
2032 typedef struct {
2033  amdsmi_vf_handle_t fcn_id;
2034  uint64_t dev_id;
2035  uint64_t timestamp;
2036  uint64_t data;
2037  uint32_t category;
2038  uint32_t subcode;
2039  uint32_t level;
2040  char date[AMDSMI_MAX_DATE_STRING_LENGTH];
2041  char message[AMDSMI_MAX_STRING_LENGTH];
2042  amdsmi_processor_handle processor_handle;
2043  uint64_t reserved[37];
2044 } amdsmi_event_entry_t;
2045 
2051 typedef struct {
2052  uint32_t version;
2053 } amdsmi_handshake_t;
2054 
2060 typedef struct {
2061  uint32_t total_fb_size;
2062  uint32_t pf_fb_reserved;
2063  uint32_t pf_fb_offset;
2064  uint32_t fb_alignment;
2065  uint32_t max_vf_fb_usable;
2066  uint32_t min_vf_fb_usable;
2067  uint64_t reserved[5];
2068 } amdsmi_pf_fb_info_t;
2069 
2075 typedef struct {
2076  uint32_t fb_offset;
2077  uint32_t fb_size;
2078  uint64_t reserved[3];
2079 } amdsmi_vf_fb_info_t;
2080 
2086 typedef struct {
2087  amdsmi_vf_handle_t id;
2088  amdsmi_vf_fb_info_t fb;
2089  uint64_t reserved[3];
2090 } amdsmi_partition_info_t;
2091 
2097 typedef struct {
2098  uint8_t enabled;
2099  struct {
2100  amdsmi_guard_state_t state;
2101  /* amount of monitor event after enabled */
2102  uint32_t amount;
2103  /* threshold of events in the interval(seconds) */
2104  uint64_t interval;
2105  uint32_t threshold;
2106  /* current number of events in the interval*/
2107  uint32_t active;
2108  uint32_t reserved[4];
2109  } guard[AMDSMI_GUARD_EVENT__MAX];
2110  uint32_t reserved[6];
2111 } amdsmi_guard_info_t;
2112 
2118 typedef struct {
2119  amdsmi_vf_fb_info_t fb;
2120  uint32_t gfx_timeslice;
2121  uint64_t reserved[27];
2122 } amdsmi_vf_info_t;
2123 
2129 typedef struct {
2130  uint64_t flr_count;
2131  uint64_t boot_up_time;
2132  uint64_t shutdown_time;
2133  uint64_t reset_time;
2134  amdsmi_vf_sched_state_t state;
2135  char last_boot_start[AMDSMI_MAX_STRING_LENGTH];
2136  char last_boot_end[AMDSMI_MAX_STRING_LENGTH];
2137  char last_shutdown_start[AMDSMI_MAX_STRING_LENGTH];
2138  char last_shutdown_end[AMDSMI_MAX_STRING_LENGTH];
2139  char last_reset_start[AMDSMI_MAX_STRING_LENGTH];
2140  char last_reset_end[AMDSMI_MAX_STRING_LENGTH];
2141  char current_active_time[AMDSMI_MAX_STRING_LENGTH];
2142  char current_running_time[AMDSMI_MAX_STRING_LENGTH];
2143  char total_active_time[AMDSMI_MAX_STRING_LENGTH];
2144  char total_running_time[AMDSMI_MAX_STRING_LENGTH];
2145  uint64_t reserved[11];
2146 } amdsmi_sched_info_t;
2147 
2153 typedef struct {
2154  amdsmi_sched_info_t sched;
2155  amdsmi_guard_info_t guard;
2156  uint64_t reserved[8];
2157 } amdsmi_vf_data_t;
2158 
2164 typedef struct {
2165  uint64_t total;
2166  uint64_t available;
2167  uint64_t optimal;
2168  uint64_t min_value;
2169  uint64_t max_value;
2170  uint64_t reserved[2];
2171 } amdsmi_profile_caps_info_t;
2172 
2178 typedef struct {
2179  uint8_t profile_count;
2180  uint8_t current_profile_index;
2181  struct {
2182  uint32_t vf_count;
2183  amdsmi_profile_caps_info_t profile_caps[AMDSMI_PROFILE_CAPABILITY__MAX];
2184  } profiles[AMDSMI_MAX_PROFILE_COUNT];
2185  uint32_t reserved[6];
2186 } amdsmi_profile_info_t;
2187 
2193 typedef struct {
2194  char driver_version[AMDSMI_MAX_STRING_LENGTH];
2195  uint32_t fb_usage;
2196  uint64_t reserved[23];
2197 } amdsmi_guest_data_t;
2198 
2204 typedef struct {
2205  uint32_t dfc_fw_version;
2206  uint32_t dfc_fw_total_entries;
2207  uint32_t dfc_gart_wr_guest_min;
2208  uint32_t dfc_gart_wr_guest_max;
2209  uint32_t reserved[12];
2210 } amdsmi_dfc_fw_header_t;
2211 
2217 typedef struct {
2218  uint32_t oldest;
2219  uint32_t latest;
2220 } amdsmi_dfc_fw_white_list_t;
2221 
2227 typedef struct {
2228  uint8_t ta_uuid[AMDSMI_MAX_UUID_ELEMENTS];
2229 } amdsmi_dfc_fw_ta_uuid_t;
2230 
2236 typedef struct {
2237  uint32_t dfc_fw_type;
2238  uint32_t verification_enabled;
2239  uint32_t customer_ordinal;
2240  uint32_t reserved[13];
2241  union {
2242  amdsmi_dfc_fw_white_list_t white_list[AMDSMI_MAX_WHITE_LIST_ELEMENTS];
2243  amdsmi_dfc_fw_ta_uuid_t ta_white_list[AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS];
2244  };
2245  uint32_t black_list[AMDSMI_MAX_BLACK_LIST_ELEMENTS];
2246 } amdsmi_dfc_fw_data_t;
2247 
2253 typedef struct {
2254  amdsmi_dfc_fw_header_t header;
2255  amdsmi_dfc_fw_data_t data[AMDSMI_DFC_FW_NUMBER_OF_ENTRIES];
2256 } amdsmi_dfc_fw_t;
2257 
2267 typedef struct {
2268  uint64_t retired_page;
2269  uint64_t ts;
2270  unsigned char err_type;
2271  union {
2272  unsigned char bank;
2273  unsigned char cu;
2274  };
2275  unsigned char mem_channel;
2276  unsigned char mcumc_id;
2277  uint32_t reserved[3];
2278 } amdsmi_eeprom_table_record_t;
2279 
2285 typedef struct {
2286  uint64_t timestamp;
2287  uint32_t vf_idx;
2288  uint32_t fw_id;
2289  uint16_t status;
2290  uint32_t reserved[3];
2291 } amdsmi_fw_load_error_record_t;
2292 
2298 typedef struct {
2299  uint8_t num_err_records;
2300  amdsmi_fw_load_error_record_t err_records[AMDSMI_MAX_ERR_RECORDS];
2301  uint64_t reserved[7];
2302 } amdsmi_fw_error_record_t;
2303 
2309 typedef struct {
2310  uint64_t weight;
2311  amdsmi_link_status_t link_status;
2312  amdsmi_link_type_t link_type;
2313  uint8_t num_hops;
2314  uint8_t fb_sharing;
2315  uint32_t reserved[10];
2316 } amdsmi_link_topology_t;
2317 
2323 typedef struct {
2324  uint32_t count;
2325  amdsmi_processor_handle processor_list[AMDSMI_MAX_DEVICES];
2326  uint64_t reserved[15];
2327 } amdsmi_topology_nearest_t;
2328 
2334 typedef union {
2335  struct cap_ {
2336  uint32_t mode_custom_cap :1;
2337  uint32_t mode_1_cap :1;
2338  uint32_t mode_2_cap :1;
2339  uint32_t mode_4_cap :1;
2340  uint32_t mode_8_cap :1;
2341  uint32_t reserved :27;
2342  } cap;
2343  uint32_t xgmi_fb_sharing_cap_mask;
2344 } amdsmi_xgmi_fb_sharing_caps_t;
2345 
2351 typedef struct {
2352  amdsmi_metric_unit_t unit;
2353  amdsmi_metric_name_t name;
2354  amdsmi_metric_category_t category;
2355  uint32_t flags;
2356  uint32_t vf_mask;
2357  uint64_t val;
2358  amdsmi_metric_res_group_t res_group;
2359  amdsmi_metric_res_subgroup_t res_subgroup;
2360  uint32_t res_instance;
2361  uint32_t reserved[5];
2362 } amdsmi_metric_t;
2363 
2369 typedef struct {
2370  uint32_t major;
2371  uint32_t minor;
2372  uint32_t release;
2373 } amdsmi_version_t;
2374 
2375 typedef struct {
2376  amdsmi_accelerator_partition_profile_t profile;
2377  uint32_t vf_mode;
2378  uint64_t reserved[6];
2379 } amdsmi_accelerator_partition_profile_global_t;
2380 
2381 typedef struct {
2382  uint32_t num_profiles;
2383  uint32_t num_resource_profiles;
2384  amdsmi_accelerator_partition_resource_profile_t resource_profiles[AMDSMI_MAX_CP_PROFILE_RESOURCES];
2385  uint32_t default_profile_index;
2386  amdsmi_accelerator_partition_profile_global_t profiles[AMDSMI_MAX_ACCELERATOR_PROFILE];
2387  uint64_t reserved[30];
2388 } amdsmi_accelerator_partition_profile_config_global_t;
2389 
2395 #define AMDSMI_MAX_NIC_PORTS 32
2396 #define AMDSMI_MAX_NIC_RDMA_DEV 32
2397 #define AMDSMI_MAX_NIC_FW 16
2398 
2406 typedef struct {
2407  char name[AMDSMI_MAX_STRING_LENGTH];
2408  uint64_t value;
2409 } amdsmi_nic_stat_t;
2410 
2416 typedef struct {
2417  uint16_t vendor_id;
2418  uint16_t subvendor_id;
2419  uint16_t device_id;
2420  uint16_t subsystem_id;
2421  uint8_t revision;
2422  char permanent_address[AMDSMI_MAX_STRING_LENGTH];
2423  char product_name[AMDSMI_MAX_STRING_LENGTH];
2424  char part_number[AMDSMI_MAX_STRING_LENGTH];
2425  char serial_number[AMDSMI_MAX_STRING_LENGTH];
2426  char vendor_name[AMDSMI_MAX_STRING_LENGTH];
2427 } amdsmi_nic_asic_info_t;
2428 
2434 typedef struct {
2435  amdsmi_bdf_t bdf;
2436  uint8_t max_pcie_width;
2437  uint32_t max_pcie_speed;
2438  char pcie_interface_version[AMDSMI_MAX_STRING_LENGTH];
2439  char slot_type[AMDSMI_MAX_STRING_LENGTH];
2440 } amdsmi_nic_bus_info_t;
2441 
2447 typedef struct {
2448  uint8_t node;
2449  char affinity[AMDSMI_MAX_STRING_LENGTH];
2450 } amdsmi_nic_numa_info_t;
2451 
2457 typedef struct {
2458  char name[AMDSMI_MAX_STRING_LENGTH];
2459  char version[AMDSMI_MAX_STRING_LENGTH];
2460 } amdsmi_nic_fw_t;
2461 
2467 typedef struct {
2468  uint32_t num_fw;
2469  amdsmi_nic_fw_t fw[AMDSMI_MAX_NIC_FW];
2470 } amdsmi_nic_fw_info_t;
2471 
2477 typedef struct {
2478  amdsmi_bdf_t bdf;
2479  uint32_t port_num;
2480  char type[AMDSMI_MAX_STRING_LENGTH];
2481  char flavour[AMDSMI_MAX_STRING_LENGTH];
2482  char netdev[AMDSMI_MAX_STRING_LENGTH];
2483  uint8_t ifindex;
2484  char mac_address[AMDSMI_MAX_STRING_LENGTH];
2485  uint8_t carrier;
2486  uint16_t mtu;
2487  char link_state[AMDSMI_MAX_STRING_LENGTH];
2488  uint32_t link_speed;
2489  uint32_t active_fec;
2490  char autoneg[AMDSMI_MAX_STRING_LENGTH];
2491  char pause_autoneg[AMDSMI_MAX_STRING_LENGTH];
2492  char pause_rx[AMDSMI_MAX_STRING_LENGTH];
2493  char pause_tx[AMDSMI_MAX_STRING_LENGTH];
2494 } amdsmi_nic_port_t;
2495 
2501 typedef struct {
2502  uint32_t num_ports;
2503  amdsmi_nic_port_t ports[AMDSMI_MAX_NIC_PORTS];
2504 } amdsmi_nic_port_info_t;
2505 
2511 typedef struct {
2512  char name[AMDSMI_MAX_STRING_LENGTH];
2513  char version[AMDSMI_MAX_STRING_LENGTH];
2514 } amdsmi_nic_driver_info_t;
2515 
2521 typedef struct {
2522  char netdev[AMDSMI_MAX_STRING_LENGTH];
2523  char state[AMDSMI_MAX_STRING_LENGTH];
2524  uint8_t rdma_port;
2525  uint16_t max_mtu;
2526  uint16_t active_mtu;
2527 } amdsmi_nic_rdma_port_info_t;
2528 
2534 typedef struct {
2535  char rdma_dev[AMDSMI_MAX_STRING_LENGTH];
2536  char node_guid[AMDSMI_MAX_STRING_LENGTH];
2537  char node_type[AMDSMI_MAX_STRING_LENGTH];
2538  char sys_image_guid[AMDSMI_MAX_STRING_LENGTH];
2539  char fw_ver[AMDSMI_MAX_STRING_LENGTH];
2540  uint8_t num_rdma_ports;
2541  amdsmi_nic_rdma_port_info_t rdma_port_info[AMDSMI_MAX_NIC_PORTS];
2542 } amdsmi_nic_rdma_dev_info_t;
2543 
2549 typedef struct {
2550  uint8_t num_rdma_dev;
2551  amdsmi_nic_rdma_dev_info_t rdma_dev_info[AMDSMI_MAX_NIC_RDMA_DEV];
2552 } amdsmi_nic_rdma_devices_info_t;
2553 /*****************************************************************************/
2582 amdsmi_status_t amdsmi_init(uint64_t init_flags);
2583 
2598 amdsmi_status_t amdsmi_shut_down(void);
2599 
2602 /*****************************************************************************/
2626 amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle,
2627  amdsmi_processor_type_t *processor_type);
2628 
2646 amdsmi_status_t amdsmi_get_processor_handle_from_index(uint32_t processor_index, amdsmi_processor_handle *processor_handle);
2647 
2679 amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count, amdsmi_socket_handle *socket_handles);
2680 
2696 amdsmi_status_t amdsmi_get_index_from_processor_handle(amdsmi_processor_handle processor_handle, uint32_t *processor_index);
2697 
2739 amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle,
2740  uint32_t *processor_count,
2741  amdsmi_processor_handle *processor_handles);
2742 
2762 amdsmi_status_t amdsmi_get_socket_info(amdsmi_socket_handle socket_handle, size_t len, char *name);
2763 
2781 amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_processor_handle *processor_handle);
2782 
2797 amdsmi_status_t amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);
2798 
2813 amdsmi_status_t amdsmi_get_processor_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);
2814 
2829 amdsmi_status_t amdsmi_get_processor_handle_from_uuid(const char *uuid, amdsmi_processor_handle *processor_handle);
2830 
2850 amdsmi_status_t amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid);
2851 
2869  amdsmi_status_t amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle, amdsmi_virtualization_mode_t *mode);
2870 
2896 amdsmi_status_t amdsmi_get_cpu_affinity_with_scope(amdsmi_processor_handle processor_handle,
2897  uint32_t cpu_set_size, uint64_t *cpu_set, amdsmi_affinity_scope_t scope);
2898 
2913 amdsmi_status_t amdsmi_get_vf_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_vf_handle_t *vf_handle);
2914 
2929 amdsmi_status_t amdsmi_get_vf_handle_from_uuid(const char *uuid, amdsmi_vf_handle_t *vf_handle);
2930 
2946 amdsmi_status_t amdsmi_get_vf_handle_from_vf_index(amdsmi_processor_handle processor_handle, uint32_t fcn_idx, amdsmi_vf_handle_t *vf_handle);
2947 
2961 amdsmi_status_t amdsmi_get_vf_bdf(amdsmi_vf_handle_t vf_handle, amdsmi_bdf_t *bdf);
2962 
2981 amdsmi_status_t amdsmi_get_vf_uuid(amdsmi_vf_handle_t processor_handle, unsigned int *uuid_length, char *uuid);
2982 
2997 amdsmi_status_t amdsmi_get_nic_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);
3020 amdsmi_status_t amdsmi_get_processor_handles_by_type(amdsmi_socket_handle socket_handle,
3021  amdsmi_processor_type_t processor_type,
3022  amdsmi_processor_handle* processor_handles,
3023  uint32_t* processor_count);
3024 
3027 /*****************************************************************************/
3048 amdsmi_status_t amdsmi_get_lib_version(amdsmi_version_t *version);
3049 
3052 /*****************************************************************************/
3077 amdsmi_status_t amdsmi_status_code_to_string(amdsmi_status_t status, const char **status_string);
3078 
3081 /*****************************************************************************/
3101 amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info);
3102 
3116 amdsmi_status_t amdsmi_get_gpu_driver_model(amdsmi_processor_handle processor_handle, amdsmi_driver_model_type_t *model);
3117 
3120 /*****************************************************************************/
3144 amdsmi_status_t amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info);
3145 
3164 amdsmi_status_t
3165 amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind,
3166  amdsmi_power_cap_info_t *info);
3167 
3182 amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle, amdsmi_pcie_info_t *info);
3183 
3198 amdsmi_status_t amdsmi_get_gpu_vram_info(amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info);
3199 
3214 amdsmi_status_t amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info);
3215 
3230 amdsmi_status_t amdsmi_get_fb_layout(amdsmi_processor_handle processor_handle, amdsmi_pf_fb_info_t *info);
3231 
3234 /*****************************************************************************/
3253 amdsmi_status_t
3254 amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info);
3255 
3271 amdsmi_status_t
3272 amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info);
3273 
3288 amdsmi_status_t amdsmi_get_fw_error_records(amdsmi_processor_handle processor_handle, amdsmi_fw_error_record_t *records);
3289 
3303 amdsmi_status_t amdsmi_get_dfc_fw_table(amdsmi_processor_handle processor_handle, amdsmi_dfc_fw_t *info);
3304 
3307 /*****************************************************************************/
3326 amdsmi_status_t amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info);
3327 
3344 amdsmi_status_t amdsmi_get_power_info(amdsmi_processor_handle processor_handle, amdsmi_power_info_t *info);
3345 
3359 amdsmi_status_t
3360 amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled);
3361 
3381 amdsmi_status_t amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info);
3382 
3412 amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle, amdsmi_temperature_type_t sensor_type,
3413  amdsmi_temperature_metric_t metric, int64_t *temperature);
3414 
3433 amdsmi_status_t amdsmi_get_gpu_metrics(amdsmi_processor_handle processor_handle, uint32_t *metrics_size,
3434  amdsmi_metric_t *metrics);
3435 
3438 /*****************************************************************************/
3457  amdsmi_status_t
3458  amdsmi_get_gpu_memory_partition_config(amdsmi_processor_handle processor_handle,
3459  amdsmi_memory_partition_config_t *config);
3460 
3484 amdsmi_status_t
3485 amdsmi_set_gpu_memory_partition_mode(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_type_t mode);
3486 
3489 /*****************************************************************************/
3511 amdsmi_status_t
3512 amdsmi_get_gpu_accelerator_partition_profile_config(amdsmi_processor_handle processor_handle,
3513  amdsmi_accelerator_partition_profile_config_t *profile_config);
3514 
3535 amdsmi_status_t
3536 amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle,
3537  amdsmi_accelerator_partition_profile_t *profile,
3538  uint32_t *partition_id);
3539 
3557 amdsmi_status_t
3558 amdsmi_set_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle,
3559  uint32_t profile_index);
3560 
3583 amdsmi_status_t
3584 amdsmi_get_gpu_accelerator_partition_profile_config_global(amdsmi_processor_handle processor_handle,
3585  amdsmi_accelerator_partition_profile_config_global_t *config);
3586 
3589 /*****************************************************************************/
3608 amdsmi_status_t amdsmi_get_link_metrics(amdsmi_processor_handle processor_handle, amdsmi_link_metrics_t *link_metrics);
3609 
3634 amdsmi_status_t
3635 amdsmi_get_link_topology_nearest(amdsmi_processor_handle processor_handle,
3636  amdsmi_link_type_t link_type,
3637  amdsmi_topology_nearest_t* topology_nearest_info);
3638 
3665 amdsmi_status_t amdsmi_topo_get_p2p_status(amdsmi_processor_handle processor_handle_src,
3666  amdsmi_processor_handle processor_handle_dst,
3667  amdsmi_link_type_t *type, amdsmi_p2p_capability_t *cap);
3668 
3688 amdsmi_status_t amdsmi_topo_get_numa_node_number(amdsmi_processor_handle processor_handle, uint32_t *numa_node);
3689 
3706 amdsmi_status_t amdsmi_get_link_topology(amdsmi_processor_handle processor_handle_src,
3707  amdsmi_processor_handle processor_handle_dst,
3708  amdsmi_link_topology_t *topology_info);
3709 
3724 amdsmi_status_t amdsmi_get_xgmi_fb_sharing_caps(amdsmi_processor_handle processor_handle,
3725  amdsmi_xgmi_fb_sharing_caps_t *caps);
3726 
3745 amdsmi_status_t amdsmi_get_xgmi_fb_sharing_mode_info(amdsmi_processor_handle processor_handle_src,
3746  amdsmi_processor_handle processor_handle_dst,
3747  amdsmi_xgmi_fb_sharing_mode_t mode,
3748  uint8_t *fb_sharing);
3749 
3763 amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode(amdsmi_processor_handle processor_handle,
3764  amdsmi_xgmi_fb_sharing_mode_t mode);
3765 
3783 amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode_v2(amdsmi_processor_handle *processor_list,
3784  uint32_t num_processors,
3785  amdsmi_xgmi_fb_sharing_mode_t mode);
3786 
3789 /*****************************************************************************/
3815 amdsmi_status_t amdsmi_get_soc_pstate(amdsmi_processor_handle processor_handle,
3816  amdsmi_dpm_policy_t* policy);
3817 
3839 amdsmi_status_t amdsmi_set_soc_pstate(amdsmi_processor_handle processor_handle,
3840  uint32_t policy_id);
3841 
3861 amdsmi_status_t amdsmi_get_xgmi_plpd(amdsmi_processor_handle processor_handle,
3862  amdsmi_dpm_policy_t *xgmi_plpd);
3863 
3885 amdsmi_status_t amdsmi_set_xgmi_plpd(amdsmi_processor_handle processor_handle,
3886  uint32_t policy_id);
3887 
3890 /*****************************************************************************/
3917 amdsmi_status_t amdsmi_set_power_cap(amdsmi_processor_handle processor_handle,
3918  uint32_t sensor_ind, uint64_t cap);
3919 
3922 /*****************************************************************************/
3943 amdsmi_status_t amdsmi_get_gpu_cache_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info);
3944 
3947 /*****************************************************************************/
3977 amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle,
3978  amdsmi_gpu_block_t block, amdsmi_error_count_t *ec);
3979 
4007 amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle,
4008  uint64_t *enabled_blocks);
4009 
4026 amdsmi_status_t
4027 amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec);
4028 
4031 /*****************************************************************************/
4061 amdsmi_status_t amdsmi_get_bad_page_threshold(amdsmi_processor_handle processor_handle, uint32_t *threshold);
4062 
4099 amdsmi_status_t
4100 amdsmi_get_gpu_cper_entries(amdsmi_processor_handle processor_handle, uint32_t severity_mask, char *cper_data,
4101  uint64_t *buf_size, amdsmi_cper_hdr_t** cper_hdrs, uint64_t *entry_count, uint64_t *cursor);
4102 
4129 amdsmi_status_t amdsmi_get_afids_from_cper(char *cper_buffer, uint32_t buf_size, uint64_t *afids, uint32_t *num_afids);
4130 
4145 amdsmi_status_t amdsmi_get_gpu_ras_feature_info(amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature);
4146 
4166 amdsmi_status_t amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *bad_page_size,
4167  amdsmi_eeprom_table_record_t *bad_pages);
4168 
4171 /*****************************************************************************/
4192 amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle);
4193 
4196 /*****************************************************************************/
4218 amdsmi_status_t
4219 amdsmi_get_num_vf(amdsmi_processor_handle processor_handle, uint32_t *num_vf_enabled,
4220  uint32_t *num_vf_supported);
4221 
4240 amdsmi_status_t
4241 amdsmi_get_vf_partition_info(amdsmi_processor_handle processor_handle, unsigned int vf_buffer_num,
4242  amdsmi_partition_info_t *info);
4243 
4258 amdsmi_status_t
4259 amdsmi_get_partition_profile_info(amdsmi_processor_handle processor_handle,
4260  amdsmi_profile_info_t *profile_info);
4261 
4264 /*****************************************************************************/
4283 amdsmi_status_t
4284 amdsmi_get_vf_info(amdsmi_vf_handle_t vf_handle, amdsmi_vf_info_t *config);
4285 
4300 amdsmi_status_t
4301 amdsmi_get_vf_data(amdsmi_vf_handle_t vf_handle, amdsmi_vf_data_t *info);
4302 
4305 /*****************************************************************************/
4345 amdsmi_status_t
4346 amdsmi_event_create(amdsmi_processor_handle *processor_list, uint32_t num_devices,
4347  uint64_t event_types, amdsmi_event_set *set);
4348 
4380 amdsmi_status_t
4381 amdsmi_event_read(amdsmi_event_set set, int64_t timeout_usec, amdsmi_event_entry_t *event);
4382 
4394 amdsmi_status_t
4395 amdsmi_event_destroy(amdsmi_event_set set);
4396 
4399 /*****************************************************************************/
4421 amdsmi_status_t
4422 amdsmi_get_guest_data(amdsmi_vf_handle_t vf_handle, amdsmi_guest_data_t *info);
4423 
4439 amdsmi_status_t
4440 amdsmi_get_vf_fw_info(amdsmi_vf_handle_t vf_handle, amdsmi_fw_info_t *info);
4441 
4444 /*****************************************************************************/
4461 amdsmi_status_t amdsmi_clear_vf_fb(amdsmi_vf_handle_t vf_handle);
4462 
4476 amdsmi_status_t amdsmi_set_num_vf(amdsmi_processor_handle processor_handle, uint32_t num_vf);
4477 
4480 /*****************************************************************************/
4499 amdsmi_status_t amdsmi_get_nic_driver_info(amdsmi_processor_handle processor_handle, amdsmi_nic_driver_info_t *info);
4500 
4515 amdsmi_status_t amdsmi_get_nic_asic_info(amdsmi_processor_handle processor_handle, amdsmi_nic_asic_info_t *info);
4516 
4531 amdsmi_status_t amdsmi_get_nic_bus_info(amdsmi_processor_handle processor_handle, amdsmi_nic_bus_info_t *info);
4532 
4547 amdsmi_status_t amdsmi_get_nic_numa_info(amdsmi_processor_handle processor_handle, amdsmi_nic_numa_info_t *info);
4548 
4563 amdsmi_status_t amdsmi_get_nic_port_info(amdsmi_processor_handle processor_handle, amdsmi_nic_port_info_t *info);
4564 
4579 amdsmi_status_t amdsmi_get_nic_rdma_dev_info(amdsmi_processor_handle processor_handle, amdsmi_nic_rdma_devices_info_t *info);
4580 
4603 amdsmi_status_t amdsmi_get_nic_port_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index,
4604  uint32_t *num_stats, amdsmi_nic_stat_t *stats);
4605 
4632 amdsmi_status_t amdsmi_get_nic_vendor_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index,
4633  uint32_t *num_stats, amdsmi_nic_stat_t *stats);
4634 
4657 amdsmi_status_t amdsmi_get_nic_rdma_port_statistics(amdsmi_processor_handle processor_handle, uint32_t rdma_port_index,
4658  uint32_t *num_stats, amdsmi_nic_stat_t *stats);
4659 
4662 #endif // __AMDSMI_H__
4663 
amdsmi_event_reset_t
amdsmi_event_reset_t
Event Reset.
Definition: amdsmi.h:1337
amdsmi_vf_mode_t
amdsmi_vf_mode_t
Definition: amdsmi.h:1998
AMDSMI_VF_MODE_ALL
@ AMDSMI_VF_MODE_ALL
All VF counts supported.
Definition: amdsmi.h:2003
AMDSMI_MAX_ACCELERATOR_PROFILE
#define AMDSMI_MAX_ACCELERATOR_PROFILE
Maximum number of accelerator profiles.
Definition: amdsmi.h:164
AMDSMI_MAX_WHITE_LIST_ELEMENTS
#define AMDSMI_MAX_WHITE_LIST_ELEMENTS
Maximum number of white list elements for device access control.
Definition: amdsmi.h:183
amdsmi_event_fw_t
amdsmi_event_fw_t
Event Firmware.
Definition: amdsmi.h:1283
amdsmi_metric_category_t
amdsmi_metric_category_t
Metric Category.
Definition: amdsmi.h:1793
amdsmi_link_type_t
amdsmi_link_type_t
Link type.
Definition: amdsmi.h:435
AMDSMI_LINK_TYPE_NOT_APPLICABLE
@ AMDSMI_LINK_TYPE_NOT_APPLICABLE
Not Applicable Link Type.
Definition: amdsmi.h:439
AMDSMI_LINK_TYPE_INTERNAL
@ AMDSMI_LINK_TYPE_INTERNAL
Internal Link Type, within chip.
Definition: amdsmi.h:436
AMDSMI_LINK_TYPE_UNKNOWN
@ AMDSMI_LINK_TYPE_UNKNOWN
Unknown Link Type.
Definition: amdsmi.h:440
AMDSMI_LINK_TYPE_PCIE
@ AMDSMI_LINK_TYPE_PCIE
Peripheral Component Interconnect Express Link Type.
Definition: amdsmi.h:437
AMDSMI_LINK_TYPE_XGMI
@ AMDSMI_LINK_TYPE_XGMI
GPU Memory Interconnect (multi GPU communication)
Definition: amdsmi.h:438
amdsmi_event_xgmi_t
amdsmi_event_xgmi_t
Event XGMI.
Definition: amdsmi.h:1587
AMDSMI_MAX_PROFILE_COUNT
#define AMDSMI_MAX_PROFILE_COUNT
Maximum number of profiles supported.
Definition: amdsmi.h:188
amdsmi_event_ecc_t
amdsmi_event_ecc_t
Event ECC.
Definition: amdsmi.h:1375
amdsmi_event_gpumon_t
amdsmi_event_gpumon_t
Event GPU Monitor.
Definition: amdsmi.h:1552
amdsmi_accelerator_partition_type_t
amdsmi_accelerator_partition_type_t
Accelerator Partition.
Definition: amdsmi.h:225
AMDSMI_ACCELERATOR_PARTITION_DPX
@ AMDSMI_ACCELERATOR_PARTITION_DPX
Definition: amdsmi.h:229
AMDSMI_ACCELERATOR_PARTITION_QPX
@ AMDSMI_ACCELERATOR_PARTITION_QPX
Definition: amdsmi.h:233
AMDSMI_ACCELERATOR_PARTITION_INVALID
@ AMDSMI_ACCELERATOR_PARTITION_INVALID
Invalid accelerator partition type.
Definition: amdsmi.h:226
AMDSMI_ACCELERATOR_PARTITION_SPX
@ AMDSMI_ACCELERATOR_PARTITION_SPX
Definition: amdsmi.h:227
AMDSMI_ACCELERATOR_PARTITION_TPX
@ AMDSMI_ACCELERATOR_PARTITION_TPX
Definition: amdsmi.h:231
AMDSMI_ACCELERATOR_PARTITION_CPX
@ AMDSMI_ACCELERATOR_PARTITION_CPX
Definition: amdsmi.h:235
amdsmi_event_guard_t
amdsmi_event_guard_t
Event Guard.
Definition: amdsmi.h:1541
amdsmi_vf_config_flags_t
amdsmi_vf_config_flags_t
VF Config Flags.
Definition: amdsmi.h:1662
amdsmi_clk_type_t
amdsmi_clk_type_t
Clock types.
Definition: amdsmi.h:287
AMDSMI_CLK_TYPE_DCLK1
@ AMDSMI_CLK_TYPE_DCLK1
Display 2 clock, timing signals for display output.
Definition: amdsmi.h:301
AMDSMI_CLK_TYPE_MEM
@ AMDSMI_CLK_TYPE_MEM
Memory clock speed, system operating frequency.
Definition: amdsmi.h:296
AMDSMI_CLK_TYPE_SYS
@ AMDSMI_CLK_TYPE_SYS
System clock.
Definition: amdsmi.h:288
AMDSMI_CLK_TYPE_SOC
@ AMDSMI_CLK_TYPE_SOC
System On Chip clock, integrated circuit frequency.
Definition: amdsmi.h:295
AMDSMI_CLK_TYPE_GFX
@ AMDSMI_CLK_TYPE_GFX
Graphics clock.
Definition: amdsmi.h:290
AMDSMI_CLK_TYPE_DCLK0
@ AMDSMI_CLK_TYPE_DCLK0
Display 1 clock, timing signals for display output.
Definition: amdsmi.h:300
AMDSMI_CLK_TYPE_DCEF
@ AMDSMI_CLK_TYPE_DCEF
Definition: amdsmi.h:293
AMDSMI_CLK_TYPE_VCLK1
@ AMDSMI_CLK_TYPE_VCLK1
Video 1 clock, video processing units.
Definition: amdsmi.h:299
AMDSMI_CLK_TYPE_DF
@ AMDSMI_CLK_TYPE_DF
Definition: amdsmi.h:291
AMDSMI_CLK_TYPE_VCLK0
@ AMDSMI_CLK_TYPE_VCLK0
Video 0 clock, video processing units.
Definition: amdsmi.h:298
AMDSMI_CLK_TYPE_PCIE
@ AMDSMI_CLK_TYPE_PCIE
PCI Express clock, high bandwidth peripherals.
Definition: amdsmi.h:297
amdsmi_accelerator_partition_resource_type_t
amdsmi_accelerator_partition_resource_type_t
Accelerator Partition Resource Types.
Definition: amdsmi.h:273
AMDSMI_ACCELERATOR_DMA
@ AMDSMI_ACCELERATOR_DMA
Direct Memory Access, high speed data transfers.
Definition: amdsmi.h:277
AMDSMI_ACCELERATOR_XCC
@ AMDSMI_ACCELERATOR_XCC
Compute complex or stream processors.
Definition: amdsmi.h:274
AMDSMI_ACCELERATOR_DECODER
@ AMDSMI_ACCELERATOR_DECODER
Video decoding.
Definition: amdsmi.h:276
AMDSMI_ACCELERATOR_JPEG
@ AMDSMI_ACCELERATOR_JPEG
Encoding and Decoding jpeg engines.
Definition: amdsmi.h:278
AMDSMI_ACCELERATOR_ENCODER
@ AMDSMI_ACCELERATOR_ENCODER
Video encoding.
Definition: amdsmi.h:275
AMDSMI_MAX_ERR_RECORDS
#define AMDSMI_MAX_ERR_RECORDS
Maximum number of error records that can be stored.
Definition: amdsmi.h:187
amdsmi_card_form_factor_t
amdsmi_card_form_factor_t
Card Form Factor.
Definition: amdsmi.h:423
AMDSMI_CARD_FORM_FACTOR_OAM
@ AMDSMI_CARD_FORM_FACTOR_OAM
OAM form factor.
Definition: amdsmi.h:425
AMDSMI_CARD_FORM_FACTOR_UNKNOWN
@ AMDSMI_CARD_FORM_FACTOR_UNKNOWN
Unknown Form factor.
Definition: amdsmi.h:427
AMDSMI_CARD_FORM_FACTOR_PCIE
@ AMDSMI_CARD_FORM_FACTOR_PCIE
PCIE card form factor.
Definition: amdsmi.h:424
AMDSMI_CARD_FORM_FACTOR_CEM
@ AMDSMI_CARD_FORM_FACTOR_CEM
CEM form factor.
Definition: amdsmi.h:426
AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK
#define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK
Common defines.
Definition: amdsmi.h:149
amdsmi_guard_type_t
amdsmi_guard_type_t
Guard Event.
Definition: amdsmi.h:1698
amdsmi_pp_throttler_type_t
amdsmi_pp_throttler_type_t
This enum represents bit mask positions for PP Throttler events.
Definition: amdsmi.h:1608
amdsmi_profile_capability_type_t
amdsmi_profile_capability_type_t
Profile Capability.
Definition: amdsmi.h:1780
AMDSMI_PROFILE_CAPABILITY_DECODE
@ AMDSMI_PROFILE_CAPABILITY_DECODE
decode engine
Definition: amdsmi.h:1783
AMDSMI_PROFILE_CAPABILITY_MEMORY
@ AMDSMI_PROFILE_CAPABILITY_MEMORY
memory
Definition: amdsmi.h:1781
AMDSMI_PROFILE_CAPABILITY_ENCODE
@ AMDSMI_PROFILE_CAPABILITY_ENCODE
encode engine
Definition: amdsmi.h:1782
AMDSMI_PROFILE_CAPABILITY_COMPUTE
@ AMDSMI_PROFILE_CAPABILITY_COMPUTE
compute engine
Definition: amdsmi.h:1784
amdsmi_init_flags_t
amdsmi_init_flags_t
Initialization flags.
Definition: amdsmi.h:44
AMDSMI_INIT_AMD_GPUS
@ AMDSMI_INIT_AMD_GPUS
Initialize AMD GPUS.
Definition: amdsmi.h:47
AMDSMI_INIT_ALL_PROCESSORS
@ AMDSMI_INIT_ALL_PROCESSORS
Initialize all processors.
Definition: amdsmi.h:45
AMDSMI_INIT_AMD_CPUS
@ AMDSMI_INIT_AMD_CPUS
Initialize AMD CPUS.
Definition: amdsmi.h:46
AMDSMI_INIT_NON_AMD_GPUS
@ AMDSMI_INIT_NON_AMD_GPUS
Initialize Non-AMD GPUS.
Definition: amdsmi.h:49
AMDSMI_INIT_NON_AMD_CPUS
@ AMDSMI_INIT_NON_AMD_CPUS
Initialize Non-AMD CPUS.
Definition: amdsmi.h:48
AMDSMI_INIT_AMD_APUS
@ AMDSMI_INIT_AMD_APUS
Definition: amdsmi.h:50
amdsmi_event_pp_t
amdsmi_event_pp_t
Event PP.
Definition: amdsmi.h:1444
amdsmi_event_vbios_t
amdsmi_event_vbios_t
Event VBios.
Definition: amdsmi.h:1514
amdsmi_event_set
void * amdsmi_event_set
Opague Handler point to underlying implementation.
Definition: amdsmi.h:1165
AMDSMI_MAX_NIC_FW
#define AMDSMI_MAX_NIC_FW
Maximum number of NIC firmwares.
Definition: amdsmi.h:2397
amdsmi_vram_type_t
amdsmi_vram_type_t
vRam Types. This enum is used to identify various VRam types.
Definition: amdsmi.h:245
AMDSMI_VRAM_TYPE_GDDR2
@ AMDSMI_VRAM_TYPE_GDDR2
Graphics Double Data Rate, Generation 2.
Definition: amdsmi.h:259
AMDSMI_VRAM_TYPE_HBM2E
@ AMDSMI_VRAM_TYPE_HBM2E
High Bandwidth Memory, Generation 2 Enhanced.
Definition: amdsmi.h:250
AMDSMI_VRAM_TYPE_GDDR6
@ AMDSMI_VRAM_TYPE_GDDR6
Graphics Double Data Rate, Generation 6.
Definition: amdsmi.h:263
AMDSMI_VRAM_TYPE_HBM
@ AMDSMI_VRAM_TYPE_HBM
High Bandwidth Memory.
Definition: amdsmi.h:248
AMDSMI_VRAM_TYPE_GDDR3
@ AMDSMI_VRAM_TYPE_GDDR3
Graphics Double Data Rate, Generation 3.
Definition: amdsmi.h:260
AMDSMI_VRAM_TYPE_GDDR1
@ AMDSMI_VRAM_TYPE_GDDR1
Graphics Double Data Rate, Generation 1.
Definition: amdsmi.h:258
AMDSMI_VRAM_TYPE_HBM3
@ AMDSMI_VRAM_TYPE_HBM3
High Bandwidth Memory, Generation 3.
Definition: amdsmi.h:251
AMDSMI_VRAM_TYPE_HBM3E
@ AMDSMI_VRAM_TYPE_HBM3E
High Bandwidth Memory, Generation 3 Enhanced.
Definition: amdsmi.h:252
AMDSMI_VRAM_TYPE_GDDR5
@ AMDSMI_VRAM_TYPE_GDDR5
Graphics Double Data Rate, Generation 5.
Definition: amdsmi.h:262
AMDSMI_VRAM_TYPE_DDR3
@ AMDSMI_VRAM_TYPE_DDR3
Double Data Rate, Generation 3.
Definition: amdsmi.h:255
AMDSMI_VRAM_TYPE_GDDR4
@ AMDSMI_VRAM_TYPE_GDDR4
Graphics Double Data Rate, Generation 4.
Definition: amdsmi.h:261
AMDSMI_VRAM_TYPE_DDR2
@ AMDSMI_VRAM_TYPE_DDR2
Double Data Rate, Generation 2.
Definition: amdsmi.h:254
AMDSMI_VRAM_TYPE_GDDR7
@ AMDSMI_VRAM_TYPE_GDDR7
Graphics Double Data Rate, Generation 7.
Definition: amdsmi.h:264
AMDSMI_VRAM_TYPE_HBM2
@ AMDSMI_VRAM_TYPE_HBM2
High Bandwidth Memory, Generation 2.
Definition: amdsmi.h:249
AMDSMI_VRAM_TYPE_DDR4
@ AMDSMI_VRAM_TYPE_DDR4
Double Data Rate, Generation 4.
Definition: amdsmi.h:256
AMDSMI_VRAM_TYPE_UNKNOWN
@ AMDSMI_VRAM_TYPE_UNKNOWN
Unknown memory type.
Definition: amdsmi.h:246
amdsmi_event_vf_max_t
amdsmi_event_vf_max_t
Event VF.
Definition: amdsmi.h:1495
amdsmi_metric_type_t
amdsmi_metric_type_t
Metric Type.
Definition: amdsmi.h:1971
AMDSMI_METRIC_TYPE_COUNTER
@ AMDSMI_METRIC_TYPE_COUNTER
counter metric
Definition: amdsmi.h:1972
AMDSMI_METRIC_TYPE_CHIPLET
@ AMDSMI_METRIC_TYPE_CHIPLET
chiplet metric
Definition: amdsmi.h:1973
AMDSMI_METRIC_TYPE_ACC
@ AMDSMI_METRIC_TYPE_ACC
accumulated metric
Definition: amdsmi.h:1975
AMDSMI_METRIC_TYPE_INST
@ AMDSMI_METRIC_TYPE_INST
instantaneous metric
Definition: amdsmi.h:1974
AMDSMI_MAX_ACCELERATOR_PARTITIONS
#define AMDSMI_MAX_ACCELERATOR_PARTITIONS
Maximum number of accelerator partitions.
Definition: amdsmi.h:163
amdsmi_cper_notify_type_t
amdsmi_cper_notify_type_t
Cper notify.
Definition: amdsmi.h:1021
AMDSMI_CPER_NOTIFY_TYPE_DMAR
@ AMDSMI_CPER_NOTIFY_TYPE_DMAR
Direct Memory Access Remapping Error.
Definition: amdsmi.h:1029
AMDSMI_CPER_NOTIFY_TYPE_NMI
@ AMDSMI_CPER_NOTIFY_TYPE_NMI
Non_Maskable Interrupt.
Definition: amdsmi.h:1027
AMDSMI_CPER_NOTIFY_TYPE_SEI
@ AMDSMI_CPER_NOTIFY_TYPE_SEI
System Error Interface.
Definition: amdsmi.h:1031
AMDSMI_CPER_NOTIFY_TYPE_CMC
@ AMDSMI_CPER_NOTIFY_TYPE_CMC
Corrected Memory Check.
Definition: amdsmi.h:1022
AMDSMI_CPER_NOTIFY_TYPE_CPE
@ AMDSMI_CPER_NOTIFY_TYPE_CPE
Corrected Platform Error.
Definition: amdsmi.h:1023
AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT
@ AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT
Compute Express Link Component Error.
Definition: amdsmi.h:1033
AMDSMI_CPER_NOTIFY_TYPE_SEA
@ AMDSMI_CPER_NOTIFY_TYPE_SEA
System Error Architecture.
Definition: amdsmi.h:1030
AMDSMI_CPER_NOTIFY_TYPE_PEI
@ AMDSMI_CPER_NOTIFY_TYPE_PEI
Platform Error Interface.
Definition: amdsmi.h:1032
AMDSMI_CPER_NOTIFY_TYPE_MCE
@ AMDSMI_CPER_NOTIFY_TYPE_MCE
Machine Check Exception.
Definition: amdsmi.h:1024
AMDSMI_CPER_NOTIFY_TYPE_BOOT
@ AMDSMI_CPER_NOTIFY_TYPE_BOOT
Boot Error.
Definition: amdsmi.h:1028
AMDSMI_CPER_NOTIFY_TYPE_PCIE
@ AMDSMI_CPER_NOTIFY_TYPE_PCIE
PCI Express Error.
Definition: amdsmi.h:1025
AMDSMI_CPER_NOTIFY_TYPE_INIT
@ AMDSMI_CPER_NOTIFY_TYPE_INIT
Initialization Error.
Definition: amdsmi.h:1026
AMDSMI_MAX_CP_PROFILE_RESOURCES
#define AMDSMI_MAX_CP_PROFILE_RESOURCES
Maximum number of compute profile resources.
Definition: amdsmi.h:162
amdsmi_fw_block_t
amdsmi_fw_block_t
The values of this enum are used to identify the various firmware blocks.
Definition: amdsmi.h:493
AMDSMI_FW_ID_ASD
@ AMDSMI_FW_ID_ASD
Asynchronous Shader Dispatcher.
Definition: amdsmi.h:567
AMDSMI_FW_ID_RS64_ME_P0_DATA
@ AMDSMI_FW_ID_RS64_ME_P0_DATA
Hardware Block RS64 - Micro Engine Partition 0 Data.
Definition: amdsmi.h:549
AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM
@ AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM
Rasterizier and L2 Cache Restore List System RAM Memory.
Definition: amdsmi.h:520
AMDSMI_FW_ID_SDMA7
@ AMDSMI_FW_ID_SDMA7
System Direct Memory Access 7 (high speed data transfers)
Definition: amdsmi.h:512
AMDSMI_FW_ID_PSP_BL
@ AMDSMI_FW_ID_PSP_BL
Platform Security Processor Bootloader (initial firmware)
Definition: amdsmi.h:532
AMDSMI_FW_ID_RLC
@ AMDSMI_FW_ID_RLC
Rasterizer and L2 Cache (rasterization processs)
Definition: amdsmi.h:504
AMDSMI_FW_ID_RS64_PFP
@ AMDSMI_FW_ID_RS64_PFP
Hardware Block RS64 - Pixel Front End Processor.
Definition: amdsmi.h:551
AMDSMI_FW_ID_SDMA_TH1
@ AMDSMI_FW_ID_SDMA_TH1
System Direct Memory Access - Thread Handler 1.
Definition: amdsmi.h:540
AMDSMI_FW_ID_MMSCH
@ AMDSMI_FW_ID_MMSCH
Multi-Media Shader Hardware Scheduler.
Definition: amdsmi.h:523
AMDSMI_FW_ID_RLX6
@ AMDSMI_FW_ID_RLX6
Hardware Block RLX6.
Definition: amdsmi.h:546
AMDSMI_FW_ID_PSP_SOSDRV
@ AMDSMI_FW_ID_PSP_SOSDRV
Platform Security Processor Secure Operating System Driver.
Definition: amdsmi.h:525
AMDSMI_FW_ID_TA_RAS
@ AMDSMI_FW_ID_TA_RAS
Trusted Applications - Reliablity Availability and Serviceability.
Definition: amdsmi.h:568
AMDSMI_FW_ID_PSP_KEYDB
@ AMDSMI_FW_ID_PSP_KEYDB
Platform Security Processor Table of Contents.
Definition: amdsmi.h:527
AMDSMI_FW_ID_RLC_SRLS
@ AMDSMI_FW_ID_RLC_SRLS
Rasterizier and L2 Cache - Shared Resource Local Segment.
Definition: amdsmi.h:572
AMDSMI_FW_ID_VCE
@ AMDSMI_FW_ID_VCE
Video Coding Engine (Encoding video)
Definition: amdsmi.h:515
AMDSMI_FW_ID_DMCU_ISR
@ AMDSMI_FW_ID_DMCU_ISR
Digital Micro Controller Unit - Interrupt Service Routine (interrupt handlers)
Definition: amdsmi.h:518
AMDSMI_FW_ID_SDMA6
@ AMDSMI_FW_ID_SDMA6
System Direct Memory Access 6 (high speed data transfers)
Definition: amdsmi.h:511
AMDSMI_FW_ID_PSP_DBG
@ AMDSMI_FW_ID_PSP_DBG
Platform Security Processor - Debug.
Definition: amdsmi.h:561
AMDSMI_FW_ID_CP_CE
@ AMDSMI_FW_ID_CP_CE
Compute Processor - Command_Engine (fetch, decode, dispatch)
Definition: amdsmi.h:497
AMDSMI_FW_ID_P2S_TABLE
@ AMDSMI_FW_ID_P2S_TABLE
Processor-to-System Table Firmware.
Definition: amdsmi.h:577
AMDSMI_FW_ID_DRV_CAP
@ AMDSMI_FW_ID_DRV_CAP
Driver Capabilities (capabilities, features)
Definition: amdsmi.h:530
AMDSMI_FW_ID_RS64_ME_P1_DATA
@ AMDSMI_FW_ID_RS64_ME_P1_DATA
Hardware Block RS64 - Micro Engine Partition 1 Data.
Definition: amdsmi.h:550
AMDSMI_FW_ID_MES_THREAD1
@ AMDSMI_FW_ID_MES_THREAD1
Micro Engine Scheduler - Thread 1.
Definition: amdsmi.h:544
AMDSMI_FW_ID_PM
@ AMDSMI_FW_ID_PM
Power Management Firmware.
Definition: amdsmi.h:573
AMDSMI_FW_ID_SDMA0
@ AMDSMI_FW_ID_SDMA0
System Direct Memory Access 0 (high speed data transfers)
Definition: amdsmi.h:505
AMDSMI_FW_ID_ISP
@ AMDSMI_FW_ID_ISP
Image Signal Processor (processing raw image data from sensors)
Definition: amdsmi.h:516
AMDSMI_FW_ID_PSP_SOC
@ AMDSMI_FW_ID_PSP_SOC
Platform Security Processor - System On a Chip.
Definition: amdsmi.h:560
AMDSMI_FW_ID_CP_PM4
@ AMDSMI_FW_ID_CP_PM4
Compute Processor Packet Processor 4 (processing command packets)
Definition: amdsmi.h:533
AMDSMI_FW_ID_RLC_P
@ AMDSMI_FW_ID_RLC_P
Rasterizier and L2 Cache Partition.
Definition: amdsmi.h:534
AMDSMI_FW_ID_SDMA_TH0
@ AMDSMI_FW_ID_SDMA_TH0
System Direct Memory Access - Thread Handler 0.
Definition: amdsmi.h:539
AMDSMI_FW_ID_MC
@ AMDSMI_FW_ID_MC
Memory Contoller (RAM and VRAM)
Definition: amdsmi.h:531
AMDSMI_FW_ID_VCN
@ AMDSMI_FW_ID_VCN
Video Core Next (encoding and decoding)
Definition: amdsmi.h:513
AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1
@ AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1
Hardware Block RLX6 Core 1 - Dynamic RAM Boot.
Definition: amdsmi.h:564
AMDSMI_FW_ID_MES_STACK
@ AMDSMI_FW_ID_MES_STACK
Micro Engine Scheduler - Stack.
Definition: amdsmi.h:543
AMDSMI_FW_ID_XGMI
@ AMDSMI_FW_ID_XGMI
XGMI (Interconnect) Firmware.
Definition: amdsmi.h:570
AMDSMI_FW_ID_PSP_TOC
@ AMDSMI_FW_ID_PSP_TOC
Platform Security Processor Table of Contents.
Definition: amdsmi.h:526
AMDSMI_FW_ID_IMU_IRAM
@ AMDSMI_FW_ID_IMU_IRAM
Input/Output Memory Management Unit - Instruction RAM.
Definition: amdsmi.h:538
AMDSMI_FW_ID_SEC_POLICY_STAGE2
@ AMDSMI_FW_ID_SEC_POLICY_STAGE2
Security Policy Stage 2 (security features)
Definition: amdsmi.h:535
AMDSMI_FW_ID_RS64_MEC_P2_DATA
@ AMDSMI_FW_ID_RS64_MEC_P2_DATA
Hardware Block RS64 - Micro Engine Controller Partition 2 Data.
Definition: amdsmi.h:557
AMDSMI_FW_ID_PLDM_BUNDLE
@ AMDSMI_FW_ID_PLDM_BUNDLE
Platform Level Data Model Firmware Bundle.
Definition: amdsmi.h:578
AMDSMI_FW_ID_TA_XGMI
@ AMDSMI_FW_ID_TA_XGMI
Trusted Applications - Reliablity XGMI.
Definition: amdsmi.h:569
AMDSMI_FW_ID_RS64_ME
@ AMDSMI_FW_ID_RS64_ME
Hardware Block RS64 - Micro Engine.
Definition: amdsmi.h:548
AMDSMI_FW_ID_SDMA3
@ AMDSMI_FW_ID_SDMA3
System Direct Memory Access 3 (high speed data transfers)
Definition: amdsmi.h:508
AMDSMI_FW_ID_SDMA1
@ AMDSMI_FW_ID_SDMA1
System Direct Memory Access 1 (high speed data transfers)
Definition: amdsmi.h:506
AMDSMI_FW_ID_CP_ME
@ AMDSMI_FW_ID_CP_ME
Compute Processor - Micro Engine (specialize processing)
Definition: amdsmi.h:499
AMDSMI_FW_ID_RS64_MEC_P3_DATA
@ AMDSMI_FW_ID_RS64_MEC_P3_DATA
Hardware Block RS64 - Micro Engine Controller Partition 3 Data.
Definition: amdsmi.h:558
AMDSMI_FW_ID_CP_MEC_JT1
@ AMDSMI_FW_ID_CP_MEC_JT1
Compute Processor - Micro Engine Controler Job Table 1 (queues, scheduling)
Definition: amdsmi.h:500
AMDSMI_FW_ID_UVD
@ AMDSMI_FW_ID_UVD
Unified Video Decoder (decode specific video formats)
Definition: amdsmi.h:514
AMDSMI_FW_ID_RLC_V
@ AMDSMI_FW_ID_RLC_V
Rasterizier and L2 Cache Virtual memory.
Definition: amdsmi.h:522
AMDSMI_FW_ID_SMC
@ AMDSMI_FW_ID_SMC
System Management Controller Firmware.
Definition: amdsmi.h:574
AMDSMI_FW_ID_SDMA4
@ AMDSMI_FW_ID_SDMA4
System Direct Memory Access 4 (high speed data transfers)
Definition: amdsmi.h:509
AMDSMI_FW_ID_MES_KIQ
@ AMDSMI_FW_ID_MES_KIQ
Micro Engine Scheduler - Kernel Indirect Queue.
Definition: amdsmi.h:542
AMDSMI_FW_ID_DMCU
@ AMDSMI_FW_ID_DMCU
Display Micro-Controller Unit.
Definition: amdsmi.h:575
AMDSMI_FW_ID_RLC_SRLG
@ AMDSMI_FW_ID_RLC_SRLG
Rasterizier and L2 Cache - Shared Resource Local Group.
Definition: amdsmi.h:571
AMDSMI_FW_ID_RS64_PFP_P1_DATA
@ AMDSMI_FW_ID_RS64_PFP_P1_DATA
Hardware Block RS64 - Pixel Front End Processor Partition 1 Data.
Definition: amdsmi.h:553
AMDSMI_FW_ID_RLX6_DRAM_BOOT
@ AMDSMI_FW_ID_RLX6_DRAM_BOOT
Hardware Block RLX6 - Dynamic Ram Boot.
Definition: amdsmi.h:547
AMDSMI_FW_ID_IMU_DRAM
@ AMDSMI_FW_ID_IMU_DRAM
Input/Output Memory Management Unit - Dynamic RAM.
Definition: amdsmi.h:537
AMDSMI_FW_ID_CP_MEC1
@ AMDSMI_FW_ID_CP_MEC1
Compute Processor - Micro Engine Controler 1 (scheduling, managing resources)
Definition: amdsmi.h:502
AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL
@ AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL
Rasterizier and L2 Cache Restore List Control.
Definition: amdsmi.h:521
AMDSMI_FW_ID_RS64_MEC_P0_DATA
@ AMDSMI_FW_ID_RS64_MEC_P0_DATA
Hardware Block RS64 - Micro Engine Controller Partition 0 Data.
Definition: amdsmi.h:555
AMDSMI_FW_ID_RLX6_CORE1
@ AMDSMI_FW_ID_RLX6_CORE1
Hardware Block RLX6 - Core 1.
Definition: amdsmi.h:563
AMDSMI_FW_ID_RS64_MEC_P1_DATA
@ AMDSMI_FW_ID_RS64_MEC_P1_DATA
Hardware Block RS64 - Micro Engine Controller Partition 1 Data.
Definition: amdsmi.h:556
AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM
@ AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM
Rasterizier and L2 Cache Restore List Graphics Processor Memory.
Definition: amdsmi.h:519
AMDSMI_FW_ID_PSP_INTF
@ AMDSMI_FW_ID_PSP_INTF
Platform Security Processor - Interface.
Definition: amdsmi.h:562
AMDSMI_FW_ID_CP_MEC_JT2
@ AMDSMI_FW_ID_CP_MEC_JT2
Compute Processor - Micro Engine Controler Job Table 2 (queues, scheduling)
Definition: amdsmi.h:501
AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST
@ AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST
Rasterizier and L2 Cache - Save Restore List.
Definition: amdsmi.h:566
AMDSMI_FW_ID_CP_PFP
@ AMDSMI_FW_ID_CP_PFP
Compute Processor - Pixel Front End Processor (pixelating process)
Definition: amdsmi.h:498
AMDSMI_FW_ID_PSP_RAS
@ AMDSMI_FW_ID_PSP_RAS
Platform Security Processor - Reliability, Availability, and Serviceability Firmware.
Definition: amdsmi.h:576
AMDSMI_FW_ID_MES_THREAD1_STACK
@ AMDSMI_FW_ID_MES_THREAD1_STACK
Micro Engine Scheduler - Thread 1 Stack.
Definition: amdsmi.h:545
AMDSMI_FW_ID_SMU
@ AMDSMI_FW_ID_SMU
Definition: amdsmi.h:494
AMDSMI_FW_ID_PPTABLE
@ AMDSMI_FW_ID_PPTABLE
Power Policy Table (power management policies)
Definition: amdsmi.h:559
AMDSMI_FW_ID_PSP_SPL
@ AMDSMI_FW_ID_PSP_SPL
Platform Security Processor Secure Program Loader.
Definition: amdsmi.h:529
AMDSMI_FW_ID_REG_ACCESS_WHITELIST
@ AMDSMI_FW_ID_REG_ACCESS_WHITELIST
Register Access Whitelist (Prevent unathorizied access)
Definition: amdsmi.h:536
AMDSMI_FW_ID_PSP_SYSDRV
@ AMDSMI_FW_ID_PSP_SYSDRV
Platform Security Processor System Driver.
Definition: amdsmi.h:524
AMDSMI_FW_ID_RS64_PFP_P0_DATA
@ AMDSMI_FW_ID_RS64_PFP_P0_DATA
Hardware Block RS64 - Pixel Front End Processor Partition 0 Data.
Definition: amdsmi.h:552
AMDSMI_FW_ID_SDMA5
@ AMDSMI_FW_ID_SDMA5
System Direct Memory Access 5 (high speed data transfers)
Definition: amdsmi.h:510
AMDSMI_FW_ID_SDMA2
@ AMDSMI_FW_ID_SDMA2
System Direct Memory Access 2 (high speed data transfers)
Definition: amdsmi.h:507
AMDSMI_FW_ID_CP_MES
@ AMDSMI_FW_ID_CP_MES
Compute Processor - Micro Engine Scheduler.
Definition: amdsmi.h:541
AMDSMI_FW_ID_DMCU_ERAM
@ AMDSMI_FW_ID_DMCU_ERAM
Digital Micro Controller Unit - Embedded RAM (memory used by DMU)
Definition: amdsmi.h:517
AMDSMI_FW_ID_RLCV_LX7
@ AMDSMI_FW_ID_RLCV_LX7
Hardware Block RLCV - Subsystem LX7.
Definition: amdsmi.h:565
AMDSMI_FW_ID_RS64_MEC
@ AMDSMI_FW_ID_RS64_MEC
Hardware Block RS64 - Micro Engine Controller.
Definition: amdsmi.h:554
AMDSMI_FW_ID_DFC
@ AMDSMI_FW_ID_DFC
Data Fabric Controler (bandwidth and coherency)
Definition: amdsmi.h:528
AMDSMI_FW_ID_CP_MEC2
@ AMDSMI_FW_ID_CP_MEC2
Compute Processor - Micro Engine Controler 2 (scheduling, managing resources)
Definition: amdsmi.h:503
amdsmi_driver_t
amdsmi_driver_t
Driver.
Definition: amdsmi.h:1714
AMDSMI_MAX_NIC_PORTS
#define AMDSMI_MAX_NIC_PORTS
Maximum size definitions AMDSMI NIC.
Definition: amdsmi.h:2395
AMDSMI_MAX_DATE_STRING_LENGTH
#define AMDSMI_MAX_DATE_STRING_LENGTH
Maximum size definitions for date strings.
Definition: amdsmi.h:1158
AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS
#define AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS
Maximum number of TA (Trusted Application) white list elements.
Definition: amdsmi.h:186
amdsmi_virtualization_mode_t
amdsmi_virtualization_mode_t
Variant placeholder.
Definition: amdsmi.h:590
AMDSMI_VIRTUALIZATION_MODE_BAREMETAL
@ AMDSMI_VIRTUALIZATION_MODE_BAREMETAL
Baremetal Virtualization Mode.
Definition: amdsmi.h:592
AMDSMI_VIRTUALIZATION_MODE_UNKNOWN
@ AMDSMI_VIRTUALIZATION_MODE_UNKNOWN
Unknown Virtualization Mode.
Definition: amdsmi.h:591
AMDSMI_VIRTUALIZATION_MODE_HOST
@ AMDSMI_VIRTUALIZATION_MODE_HOST
Host Virtualization Mode.
Definition: amdsmi.h:593
AMDSMI_VIRTUALIZATION_MODE_GUEST
@ AMDSMI_VIRTUALIZATION_MODE_GUEST
Guest Virtualization Mode.
Definition: amdsmi.h:594
AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH
@ AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH
Passthrough Virtualization Mode.
Definition: amdsmi.h:595
AMDSMI_MAX_STRING_LENGTH
#define AMDSMI_MAX_STRING_LENGTH
Maximum length for string buffers.
Definition: amdsmi.h:160
amdsmi_guest_fw_engine_id_t
amdsmi_guest_fw_engine_id_t
The values of this enum are used to identify the various firmware blocks.
Definition: amdsmi.h:1632
amdsmi_metric_unit_t
amdsmi_metric_unit_t
Metric Unit.
Definition: amdsmi.h:1948
amdsmi_link_status_t
amdsmi_link_status_t
Link Status.
Definition: amdsmi.h:613
amdsmi_ecc_correction_schema_support_t
amdsmi_ecc_correction_schema_support_t
The values of this enum are used to identify supported ecc correction schema.
Definition: amdsmi.h:1620
amdsmi_event_driver_t
amdsmi_event_driver_t
Event Driver.
Definition: amdsmi.h:1214
AMDSMI_MAX_BLACK_LIST_ELEMENTS
#define AMDSMI_MAX_BLACK_LIST_ELEMENTS
Maximum number of black list elements for device access control.
Definition: amdsmi.h:184
amdsmi_processor_type_t
amdsmi_processor_type_t
Processor types detectable by AMD SMI.
Definition: amdsmi.h:133
AMDSMI_PROCESSOR_TYPE_AMD_APU
@ AMDSMI_PROCESSOR_TYPE_AMD_APU
AMD Accelerated processor type (GPU and CPU)
Definition: amdsmi.h:140
AMDSMI_PROCESSOR_TYPE_UNKNOWN
@ AMDSMI_PROCESSOR_TYPE_UNKNOWN
Unknown processor type.
Definition: amdsmi.h:134
AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU
@ AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU
Non-AMD CPU processor type.
Definition: amdsmi.h:138
AMDSMI_PROCESSOR_TYPE_AMD_CPU
@ AMDSMI_PROCESSOR_TYPE_AMD_CPU
AMD CPU processor type.
Definition: amdsmi.h:136
AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE
@ AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE
AMD CPU-Core processor type.
Definition: amdsmi.h:139
AMDSMI_PROCESSOR_TYPE_AMD_GPU
@ AMDSMI_PROCESSOR_TYPE_AMD_GPU
AMD Graphics processor type.
Definition: amdsmi.h:135
AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU
@ AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU
Non-AMD Graphics processor type.
Definition: amdsmi.h:137
AMDSMI_PROCESSOR_TYPE_AMD_NIC
@ AMDSMI_PROCESSOR_TYPE_AMD_NIC
AMD Network Interface Card processor type.
Definition: amdsmi.h:141
amdsmi_memory_partition_type_t
amdsmi_memory_partition_type_t
Memory Partitions.
Definition: amdsmi.h:203
AMDSMI_MEMORY_PARTITION_NPS8
@ AMDSMI_MEMORY_PARTITION_NPS8
Definition: amdsmi.h:213
AMDSMI_MEMORY_PARTITION_NPS1
@ AMDSMI_MEMORY_PARTITION_NPS1
Definition: amdsmi.h:205
AMDSMI_MEMORY_PARTITION_NPS2
@ AMDSMI_MEMORY_PARTITION_NPS2
Definition: amdsmi.h:207
AMDSMI_MEMORY_PARTITION_NPS4
@ AMDSMI_MEMORY_PARTITION_NPS4
Definition: amdsmi.h:210
AMDSMI_MAX_NIC_RDMA_DEV
#define AMDSMI_MAX_NIC_RDMA_DEV
Maximum number of NIC RDMA devices.
Definition: amdsmi.h:2396
amdsmi_event_iov_t
amdsmi_event_iov_t
Event IOV.
Definition: amdsmi.h:1350
amdsmi_guard_state_t
amdsmi_guard_state_t
Guard State.
Definition: amdsmi.h:1728
amdsmi_sched_block_t
amdsmi_sched_block_t
Schedule Block.
Definition: amdsmi.h:1739
amdsmi_processor_handle
void * amdsmi_processor_handle
opaque handler point to underlying implementation
Definition: amdsmi.h:59
amdsmi_event_gpu_t
amdsmi_event_gpu_t
Below are the error subcodes of each category.
Definition: amdsmi.h:1196
amdsmi_cache_property_type_t
amdsmi_cache_property_type_t
cache properties
Definition: amdsmi.h:448
AMDSMI_CACHE_PROPERTY_ENABLED
@ AMDSMI_CACHE_PROPERTY_ENABLED
Cache enabled.
Definition: amdsmi.h:449
AMDSMI_CACHE_PROPERTY_INST_CACHE
@ AMDSMI_CACHE_PROPERTY_INST_CACHE
Instruction cache.
Definition: amdsmi.h:451
AMDSMI_CACHE_PROPERTY_DATA_CACHE
@ AMDSMI_CACHE_PROPERTY_DATA_CACHE
Data cache.
Definition: amdsmi.h:450
AMDSMI_CACHE_PROPERTY_SIMD_CACHE
@ AMDSMI_CACHE_PROPERTY_SIMD_CACHE
Single Instruction, Multiple Data Cache.
Definition: amdsmi.h:453
AMDSMI_CACHE_PROPERTY_CPU_CACHE
@ AMDSMI_CACHE_PROPERTY_CPU_CACHE
CPU cache.
Definition: amdsmi.h:452
amdsmi_event_mmsch_t
amdsmi_event_mmsch_t
Event MM Schedule.
Definition: amdsmi.h:1576
AMDSMI_MAX_DEVICES
#define AMDSMI_MAX_DEVICES
Maximum number of devices supported.
Definition: amdsmi.h:159
amdsmi_status_t
amdsmi_status_t
Error codes returned by amdsmi functions.
Definition: amdsmi.h:70
AMDSMI_STATUS_NOT_INIT
@ AMDSMI_STATUS_NOT_INIT
Processor not initialized.
Definition: amdsmi.h:96
AMDSMI_STATUS_NON_AMD_CPU
@ AMDSMI_STATUS_NON_AMD_CPU
System has different cpu than AMD.
Definition: amdsmi.h:106
AMDSMI_STATUS_DIRECTORY_NOT_FOUND
@ AMDSMI_STATUS_DIRECTORY_NOT_FOUND
Error when a directory is not found, maps to ENOTDIR.
Definition: amdsmi.h:92
AMDSMI_STATUS_INVAL
@ AMDSMI_STATUS_INVAL
Invalid parameters.
Definition: amdsmi.h:73
AMDSMI_STATUS_BUSY
@ AMDSMI_STATUS_BUSY
Processor busy.
Definition: amdsmi.h:94
AMDSMI_STATUS_UNKNOWN_ERROR
@ AMDSMI_STATUS_UNKNOWN_ERROR
An unknown error occurred.
Definition: amdsmi.h:121
AMDSMI_STATUS_DRIVER_NOT_LOADED
@ AMDSMI_STATUS_DRIVER_NOT_LOADED
Processor driver not loaded.
Definition: amdsmi.h:98
AMDSMI_STATUS_FILE_ERROR
@ AMDSMI_STATUS_FILE_ERROR
Problem accessing a file.
Definition: amdsmi.h:86
AMDSMI_STATUS_DRM_ERROR
@ AMDSMI_STATUS_DRM_ERROR
Error when call libdrm.
Definition: amdsmi.h:78
AMDSMI_STATUS_CORRUPTED_EEPROM
@ AMDSMI_STATUS_CORRUPTED_EEPROM
EEPROM is corrupted.
Definition: amdsmi.h:118
AMDSMI_STATUS_ARG_PTR_NULL
@ AMDSMI_STATUS_ARG_PTR_NULL
Parsed argument is invalid.
Definition: amdsmi.h:115
AMDSMI_STATUS_IO
@ AMDSMI_STATUS_IO
I/O Error.
Definition: amdsmi.h:84
AMDSMI_STATUS_NO_HSMP_DRV
@ AMDSMI_STATUS_NO_HSMP_DRV
HSMP driver not found.
Definition: amdsmi.h:109
AMDSMI_STATUS_HSMP_TIMEOUT
@ AMDSMI_STATUS_HSMP_TIMEOUT
HSMP message timed out.
Definition: amdsmi.h:112
AMDSMI_STATUS_NO_DATA
@ AMDSMI_STATUS_NO_DATA
No data was found for a given input.
Definition: amdsmi.h:101
AMDSMI_STATUS_RETRY
@ AMDSMI_STATUS_RETRY
Retry operation.
Definition: amdsmi.h:81
AMDSMI_STATUS_UNEXPECTED_SIZE
@ AMDSMI_STATUS_UNEXPECTED_SIZE
An unexpected amount of data was read.
Definition: amdsmi.h:103
AMDSMI_STATUS_SETTING_UNAVAILABLE
@ AMDSMI_STATUS_SETTING_UNAVAILABLE
Setting is not available.
Definition: amdsmi.h:117
AMDSMI_STATUS_FILE_NOT_FOUND
@ AMDSMI_STATUS_FILE_NOT_FOUND
file or directory not found
Definition: amdsmi.h:114
AMDSMI_STATUS_INTERNAL_EXCEPTION
@ AMDSMI_STATUS_INTERNAL_EXCEPTION
An internal exception was caught.
Definition: amdsmi.h:88
AMDSMI_STATUS_NO_HSMP_SUP
@ AMDSMI_STATUS_NO_HSMP_SUP
HSMP not supported.
Definition: amdsmi.h:110
AMDSMI_STATUS_MAP_ERROR
@ AMDSMI_STATUS_MAP_ERROR
The internal library error did not map to a status code.
Definition: amdsmi.h:120
AMDSMI_STATUS_FAIL_LOAD_SYMBOL
@ AMDSMI_STATUS_FAIL_LOAD_SYMBOL
Fail to load symbol.
Definition: amdsmi.h:77
AMDSMI_STATUS_INSUFFICIENT_SIZE
@ AMDSMI_STATUS_INSUFFICIENT_SIZE
Not enough resources were available for the operation.
Definition: amdsmi.h:102
AMDSMI_STATUS_INIT_ERROR
@ AMDSMI_STATUS_INIT_ERROR
An error occurred when initializing internal data structures.
Definition: amdsmi.h:90
AMDSMI_STATUS_OUT_OF_RESOURCES
@ AMDSMI_STATUS_OUT_OF_RESOURCES
Not enough memory.
Definition: amdsmi.h:87
AMDSMI_STATUS_NO_SLOT
@ AMDSMI_STATUS_NO_SLOT
No more free slot.
Definition: amdsmi.h:97
AMDSMI_STATUS_NO_MSR_DRV
@ AMDSMI_STATUS_NO_MSR_DRV
MSR driver not found.
Definition: amdsmi.h:108
AMDSMI_STATUS_INTERRUPT
@ AMDSMI_STATUS_INTERRUPT
An interrupt occurred during execution of function.
Definition: amdsmi.h:83
AMDSMI_STATUS_SUCCESS
@ AMDSMI_STATUS_SUCCESS
Call succeeded.
Definition: amdsmi.h:71
AMDSMI_STATUS_NO_ENERGY_DRV
@ AMDSMI_STATUS_NO_ENERGY_DRV
Energy driver not found.
Definition: amdsmi.h:107
AMDSMI_STATUS_ADDRESS_FAULT
@ AMDSMI_STATUS_ADDRESS_FAULT
Bad address.
Definition: amdsmi.h:85
AMDSMI_STATUS_MORE_DATA
@ AMDSMI_STATUS_MORE_DATA
There is more data than the buffer size the user passed.
Definition: amdsmi.h:100
AMDSMI_STATUS_NOT_YET_IMPLEMENTED
@ AMDSMI_STATUS_NOT_YET_IMPLEMENTED
Not implemented yet.
Definition: amdsmi.h:75
AMDSMI_STATUS_NO_DRV
@ AMDSMI_STATUS_NO_DRV
No Energy and HSMP driver present.
Definition: amdsmi.h:113
AMDSMI_STATUS_NO_PERM
@ AMDSMI_STATUS_NO_PERM
Permission Denied.
Definition: amdsmi.h:82
AMDSMI_STATUS_NOT_FOUND
@ AMDSMI_STATUS_NOT_FOUND
Processor Not found.
Definition: amdsmi.h:95
AMDSMI_STATUS_FAIL_LOAD_MODULE
@ AMDSMI_STATUS_FAIL_LOAD_MODULE
Fail to load lib.
Definition: amdsmi.h:76
AMDSMI_STATUS_AMDGPU_RESTART_ERR
@ AMDSMI_STATUS_AMDGPU_RESTART_ERR
AMDGPU restart failed.
Definition: amdsmi.h:116
AMDSMI_STATUS_NOT_SUPPORTED
@ AMDSMI_STATUS_NOT_SUPPORTED
Command not supported.
Definition: amdsmi.h:74
AMDSMI_STATUS_UNEXPECTED_DATA
@ AMDSMI_STATUS_UNEXPECTED_DATA
The data read or provided to function is not what was expected.
Definition: amdsmi.h:104
AMDSMI_STATUS_API_FAILED
@ AMDSMI_STATUS_API_FAILED
API call failed.
Definition: amdsmi.h:79
AMDSMI_STATUS_TIMEOUT
@ AMDSMI_STATUS_TIMEOUT
Timeout in API call.
Definition: amdsmi.h:80
AMDSMI_STATUS_NO_HSMP_MSG_SUP
@ AMDSMI_STATUS_NO_HSMP_MSG_SUP
HSMP message/feature not supported.
Definition: amdsmi.h:111
AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS
@ AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS
The provided input is out of allowable or safe range.
Definition: amdsmi.h:89
AMDSMI_STATUS_REFCOUNT_OVERFLOW
@ AMDSMI_STATUS_REFCOUNT_OVERFLOW
An internal reference counter exceeded INT32_MAX.
Definition: amdsmi.h:91
AMDSMI_MAX_NUM_PM_POLICIES
#define AMDSMI_MAX_NUM_PM_POLICIES
Maximum number of power management policies.
Definition: amdsmi.h:150
amdsmi_guest_fw_load_status_t
amdsmi_guest_fw_load_status_t
Guest firmware load status.
Definition: amdsmi.h:1753
amdsmi_xgmi_fb_sharing_mode_t
amdsmi_xgmi_fb_sharing_mode_t
XGMI FB Sharing Mode.
Definition: amdsmi.h:1766
amdsmi_affinity_scope_t
amdsmi_affinity_scope_t
Scope for Numa affinity or Socket affinity.
Definition: amdsmi.h:603
AMDSMI_AFFINITY_SCOPE_NODE
@ AMDSMI_AFFINITY_SCOPE_NODE
Memory affinity as numa node.
Definition: amdsmi.h:604
AMDSMI_AFFINITY_SCOPE_SOCKET
@ AMDSMI_AFFINITY_SCOPE_SOCKET
socket affinity
Definition: amdsmi.h:605
amdsmi_temperature_metric_t
amdsmi_temperature_metric_t
Temperature Metrics. This enum is used to identify various temperature metrics. Corresponding values ...
Definition: amdsmi.h:387
AMDSMI_TEMP_CRITICAL_HYST
@ AMDSMI_TEMP_CRITICAL_HYST
Definition: amdsmi.h:398
AMDSMI_TEMP_CRITICAL
@ AMDSMI_TEMP_CRITICAL
Definition: amdsmi.h:396
AMDSMI_TEMP_OFFSET
@ AMDSMI_TEMP_OFFSET
Definition: amdsmi.h:410
AMDSMI_TEMP_EMERGENCY
@ AMDSMI_TEMP_EMERGENCY
Definition: amdsmi.h:400
AMDSMI_TEMP_LOWEST
@ AMDSMI_TEMP_LOWEST
Historical min temperature.
Definition: amdsmi.h:412
AMDSMI_TEMP_CRIT_MIN
@ AMDSMI_TEMP_CRIT_MIN
Definition: amdsmi.h:406
AMDSMI_TEMP_SHUTDOWN
@ AMDSMI_TEMP_SHUTDOWN
Shutdown temperature.
Definition: amdsmi.h:414
AMDSMI_TEMP_EMERGENCY_HYST
@ AMDSMI_TEMP_EMERGENCY_HYST
Definition: amdsmi.h:404
AMDSMI_TEMP_CURRENT
@ AMDSMI_TEMP_CURRENT
Current temperature.
Definition: amdsmi.h:388
AMDSMI_TEMP_MIN
@ AMDSMI_TEMP_MIN
Min temperature.
Definition: amdsmi.h:391
AMDSMI_TEMP_HIGHEST
@ AMDSMI_TEMP_HIGHEST
Historical max temperature.
Definition: amdsmi.h:413
AMDSMI_TEMP_CRIT_MIN_HYST
@ AMDSMI_TEMP_CRIT_MIN_HYST
Definition: amdsmi.h:408
AMDSMI_TEMP_MIN_HYST
@ AMDSMI_TEMP_MIN_HYST
Definition: amdsmi.h:394
AMDSMI_TEMP_MAX_HYST
@ AMDSMI_TEMP_MAX_HYST
Definition: amdsmi.h:392
AMDSMI_TEMP_MAX
@ AMDSMI_TEMP_MAX
Max temperature.
Definition: amdsmi.h:390
amdsmi_event_category_t
amdsmi_event_category_t
Event Category.
Definition: amdsmi.h:1172
amdsmi_cper_sev_t
amdsmi_cper_sev_t
Cper sev.
Definition: amdsmi.h:1008
AMDSMI_CPER_SEV_NUM
@ AMDSMI_CPER_SEV_NUM
CPER severity Number.
Definition: amdsmi.h:1012
AMDSMI_CPER_SEV_NON_FATAL_CORRECTED
@ AMDSMI_CPER_SEV_NON_FATAL_CORRECTED
CPER Non-Fatal Corrected severity.
Definition: amdsmi.h:1011
AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED
@ AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED
CPER Non-Fatal Uncorrected severity.
Definition: amdsmi.h:1009
AMDSMI_CPER_SEV_FATAL
@ AMDSMI_CPER_SEV_FATAL
CPER Fatal severity.
Definition: amdsmi.h:1010
AMDSMI_CPER_SEV_UNUSED
@ AMDSMI_CPER_SEV_UNUSED
CPER Unused severity.
Definition: amdsmi.h:1013
amdsmi_gpu_block_t
amdsmi_gpu_block_t
This enum is used to identify different GPU blocks.
Definition: amdsmi.h:461
AMDSMI_GPU_BLOCK_XGMI_WAFL
@ AMDSMI_GPU_BLOCK_XGMI_WAFL
XGMI block.
Definition: amdsmi.h:471
AMDSMI_GPU_BLOCK_GFX
@ AMDSMI_GPU_BLOCK_GFX
GFX block.
Definition: amdsmi.h:466
AMDSMI_GPU_BLOCK_IH
@ AMDSMI_GPU_BLOCK_IH
IH block.
Definition: amdsmi.h:481
AMDSMI_GPU_BLOCK_VCN
@ AMDSMI_GPU_BLOCK_VCN
VCN block.
Definition: amdsmi.h:479
AMDSMI_GPU_BLOCK_INVALID
@ AMDSMI_GPU_BLOCK_INVALID
Invalid block.
Definition: amdsmi.h:462
AMDSMI_GPU_BLOCK_MP0
@ AMDSMI_GPU_BLOCK_MP0
MP0 block.
Definition: amdsmi.h:475
AMDSMI_GPU_BLOCK_HDP
@ AMDSMI_GPU_BLOCK_HDP
HDP block.
Definition: amdsmi.h:470
AMDSMI_GPU_BLOCK_MPIO
@ AMDSMI_GPU_BLOCK_MPIO
MPIO block.
Definition: amdsmi.h:482
AMDSMI_GPU_BLOCK_ATHUB
@ AMDSMI_GPU_BLOCK_ATHUB
ATHUB block.
Definition: amdsmi.h:468
AMDSMI_GPU_BLOCK_MP1
@ AMDSMI_GPU_BLOCK_MP1
MP1 block.
Definition: amdsmi.h:476
AMDSMI_GPU_BLOCK_PCIE_BIF
@ AMDSMI_GPU_BLOCK_PCIE_BIF
PCIE_BIF block.
Definition: amdsmi.h:469
AMDSMI_GPU_BLOCK_SDMA
@ AMDSMI_GPU_BLOCK_SDMA
SDMA block.
Definition: amdsmi.h:465
AMDSMI_GPU_BLOCK_JPEG
@ AMDSMI_GPU_BLOCK_JPEG
JPEG block.
Definition: amdsmi.h:480
AMDSMI_GPU_BLOCK_UMC
@ AMDSMI_GPU_BLOCK_UMC
UMC block.
Definition: amdsmi.h:464
AMDSMI_GPU_BLOCK_FUSE
@ AMDSMI_GPU_BLOCK_FUSE
Fuse block.
Definition: amdsmi.h:477
AMDSMI_GPU_BLOCK_DF
@ AMDSMI_GPU_BLOCK_DF
DF block.
Definition: amdsmi.h:472
AMDSMI_GPU_BLOCK_MMHUB
@ AMDSMI_GPU_BLOCK_MMHUB
MMHUB block.
Definition: amdsmi.h:467
AMDSMI_GPU_BLOCK_SMN
@ AMDSMI_GPU_BLOCK_SMN
SMN block.
Definition: amdsmi.h:473
AMDSMI_GPU_BLOCK_SEM
@ AMDSMI_GPU_BLOCK_SEM
SEM block.
Definition: amdsmi.h:474
AMDSMI_GPU_BLOCK_MCA
@ AMDSMI_GPU_BLOCK_MCA
MCA block.
Definition: amdsmi.h:478
amdsmi_metric_name_t
amdsmi_metric_name_t
Metric Name.
Definition: amdsmi.h:1814
amdsmi_vf_sched_state_t
amdsmi_vf_sched_state_t
VF Schedule State.
Definition: amdsmi.h:1684
amdsmi_event_sched_t
amdsmi_event_sched_t
Event Schedule.
Definition: amdsmi.h:1457
amdsmi_driver_model_type_t
amdsmi_driver_model_type_t
The values of this enum are used to identify driver model type.
Definition: amdsmi.h:2011
amdsmi_temperature_type_t
amdsmi_temperature_type_t
This enumeration is used to indicate from which part of the processor a temperature reading should be...
Definition: amdsmi.h:311
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_D_VR
OAM X 0.4V HBM D voltage regulator temperature.
Definition: amdsmi.h:331
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD3
VDDCR VDD3 voltage regulator temperature.
Definition: amdsmi.h:340
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_HSC
OAM 0-1 HSC temperature.
Definition: amdsmi.h:361
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_A
VDDCR SOC A voltage regulator temperature.
Definition: amdsmi.h:341
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_6_7_HSC
OAM 6-7 HSC temperature.
Definition: amdsmi.h:364
AMDSMI_TEMPERATURE_TYPE_HBM_2
@ AMDSMI_TEMPERATURE_TYPE_HBM_2
High Bandwidth 2 temperature per stack.
Definition: amdsmi.h:319
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC_2
OAM X IBC 2 temperature.
Definition: amdsmi.h:328
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_0V9_VR
Retimer 4-5 0.9V voltage regulator temperature.
Definition: amdsmi.h:370
AMDSMI_TEMPERATURE_TYPE_HOTSPOT
@ AMDSMI_TEMPERATURE_TYPE_HOTSPOT
Hottest temperature reported for entire die.
Definition: amdsmi.h:314
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_085_HBM
VDD 0.85V HBM voltage regulator temperature.
Definition: amdsmi.h:345
AMDSMI_TEMPERATURE_TYPE_HBM_0
@ AMDSMI_TEMPERATURE_TYPE_HBM_0
High Bandwidth 0 temperature per stack.
Definition: amdsmi.h:317
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD2
VDDCR VDD2 voltage regulator temperature.
Definition: amdsmi.h:339
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_IBC
UBB IBC temperature.
Definition: amdsmi.h:358
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_D
VDDCR 1.1V HBM D voltage regulator temperature.
Definition: amdsmi.h:347
AMDSMI_TEMPERATURE_TYPE_JUNCTION
@ AMDSMI_TEMPERATURE_TYPE_JUNCTION
Synonymous with HOTSPOT.
Definition: amdsmi.h:315
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_4_5_6_7_1V2_VR
Retimer 4-5-6-7 1.2V voltage regulator temperature.
Definition: amdsmi.h:368
AMDSMI_TEMPERATURE_TYPE_HBM_3
@ AMDSMI_TEMPERATURE_TYPE_HBM_3
High Bandwidth 3 temperature per stack.
Definition: amdsmi.h:320
AMDSMI_TEMPERATURE_TYPE_VRAM
@ AMDSMI_TEMPERATURE_TYPE_VRAM
VRAM temperature on graphics card.
Definition: amdsmi.h:316
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_2_3_HSC
OAM 2-3 HSC temperature.
Definition: amdsmi.h:362
AMDSMI_TEMPERATURE_TYPE_EDGE
@ AMDSMI_TEMPERATURE_TYPE_EDGE
Edge temperature.
Definition: amdsmi.h:312
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_UFPGA
UBB UFPGA temperature.
Definition: amdsmi.h:359
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDD_USR
VDD USR voltage regulator temperature.
Definition: amdsmi.h:348
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_04_HBM_B_VR
OAM X 0.4V HBM B voltage regulator temperature.
Definition: amdsmi.h:330
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOC_C
VDDCR SOC C voltage regulator temperature.
Definition: amdsmi.h:342
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_A
VDDCR SOCIO A voltage regulator temperature.
Definition: amdsmi.h:343
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC_HSC
IBC HSC temperature.
Definition: amdsmi.h:375
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_HSC
OAM 4-5 HSC temperature.
Definition: amdsmi.h:363
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_2_3_0V9_VR
Retimer 2-3 0.9V voltage regulator temperature.
Definition: amdsmi.h:371
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD1
VDDCR VDD1 voltage regulator temperature.
Definition: amdsmi.h:338
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_SOCIO_C
VDDCR SOCIO C voltage regulator temperature.
Definition: amdsmi.h:344
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_0V9_VR
Retimer 0-1 0.9V voltage regulator temperature.
Definition: amdsmi.h:369
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_VDD0
VDDCR VDD0 voltage regulator temperature.
Definition: amdsmi.h:336
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_0V72_VR
UBB FPGA 0.72V voltage regulator temperature.
Definition: amdsmi.h:365
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA_3V3_VR
UBB FPGA 3.3V voltage regulator temperature.
Definition: amdsmi.h:366
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDIO_11_E32
VDDIO 1.1V E32 voltage regulator temperature.
Definition: amdsmi.h:349
AMDSMI_TEMPERATURE_TYPE_PLX
@ AMDSMI_TEMPERATURE_TYPE_PLX
PCIe switch temperature.
Definition: amdsmi.h:321
AMDSMI_TEMPERATURE_TYPE_HBM_1
@ AMDSMI_TEMPERATURE_TYPE_HBM_1
High Bandwidth 1 temperature per stack.
Definition: amdsmi.h:318
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM7
UBB OAM7 temperature.
Definition: amdsmi.h:357
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_0_1_2_3_3V3_VR
OAM 0-1-2-3 3.3V voltage regulator temperature.
Definition: amdsmi.h:373
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_VDDCR_11_HBM_B
VDDCR 1.1V HBM B voltage regulator temperature.
Definition: amdsmi.h:346
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_BACK
UBB back temperature.
Definition: amdsmi.h:356
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FPGA
UBB FPGA temperature.
Definition: amdsmi.h:354
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_RETIMER_X
Retimer X temperature.
Definition: amdsmi.h:325
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_IBC
IBC temperature.
Definition: amdsmi.h:376
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_VDD18_VR
OAM X VDD 1.8V voltage regulator temperature.
Definition: amdsmi.h:329
AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC
@ AMDSMI_TEMPERATURE_TYPE_GPUBOARD_NODE_OAM_X_IBC
OAM X IBC temperature.
Definition: amdsmi.h:327
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_0_1_2_3_1V2_VR
Retimer 0-1-2-3 1.2V voltage regulator temperature.
Definition: amdsmi.h:367
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_FRONT
UBB front temperature.
Definition: amdsmi.h:355
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_RETIMER_6_7_0V9_VR
Retimer 6-7 0.9V voltage regulator temperature.
Definition: amdsmi.h:372
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_OAM_4_5_6_7_3V3_VR
OAM 4-5-6-7 3.3V voltage regulator temperature.
Definition: amdsmi.h:374
AMDSMI_TEMPERATURE_TYPE__MAX
@ AMDSMI_TEMPERATURE_TYPE__MAX
Maximum per GPU temperature type.
Definition: amdsmi.h:378
AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1
@ AMDSMI_TEMPERATURE_TYPE_BASEBOARD_UBB_OAM1
UBB OAM1 temperature.
Definition: amdsmi.h:360
AMDSMI_MAX_UUID_ELEMENTS
#define AMDSMI_MAX_UUID_ELEMENTS
Maximum number of UUID elements supported.
Definition: amdsmi.h:185
AMDSMI_MAX_CACHE_TYPES
#define AMDSMI_MAX_CACHE_TYPES
Maximum number of cache types.
Definition: amdsmi.h:161
AMDSMI_DFC_FW_NUMBER_OF_ENTRIES
#define AMDSMI_DFC_FW_NUMBER_OF_ENTRIES
Number of DFC firmware entries supported.
Definition: amdsmi.h:182
AMDSMI_MAX_NUM_NUMA_NODES
#define AMDSMI_MAX_NUM_NUMA_NODES
Maximum number of NUMA nodes.
Definition: amdsmi.h:165
amdsmi_set_gpu_accelerator_partition_profile
amdsmi_status_t amdsmi_set_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, uint32_t profile_index)
Set accelerator partition setting based on profile_index from amdsmi_get_gpu_accelerator_partition_pr...
amdsmi_get_gpu_accelerator_partition_profile_config
amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile_config(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_config_t *profile_config)
Returns gpu accelerator partition caps as currently configured in the system.
amdsmi_get_gpu_accelerator_partition_profile_config_global
amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile_config_global(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_config_global_t *config)
Returns all GPU accelerator partition capabilities which can be configured on the system.
amdsmi_get_gpu_accelerator_partition_profile
amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_t *profile, uint32_t *partition_id)
Returns current gpu accelerator partition cap.
amdsmi_get_fb_layout
amdsmi_status_t amdsmi_get_fb_layout(amdsmi_processor_handle processor_handle, amdsmi_pf_fb_info_t *info)
Returns the framebuffer info for the ASIC.
amdsmi_get_power_cap_info
amdsmi_status_t amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, amdsmi_power_cap_info_t *info)
Returns the power caps as currently configured in the system.
amdsmi_get_pcie_info
amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle, amdsmi_pcie_info_t *info)
Returns the PCIe info for the GPU.
amdsmi_get_gpu_vram_info
amdsmi_status_t amdsmi_get_gpu_vram_info(amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info)
Returns vram info.
amdsmi_get_gpu_board_info
amdsmi_status_t amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info)
Returns the board part number and board information for the requested device.
amdsmi_get_gpu_asic_info
amdsmi_status_t amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info)
Returns the ASIC information for the device.
amdsmi_get_xgmi_plpd
amdsmi_status_t amdsmi_get_xgmi_plpd(amdsmi_processor_handle processor_handle, amdsmi_dpm_policy_t *xgmi_plpd)
Get the xgmi per-link power down policy parameter for the processor.
amdsmi_set_xgmi_plpd
amdsmi_status_t amdsmi_set_xgmi_plpd(amdsmi_processor_handle processor_handle, uint32_t policy_id)
Set the xgmi per-link power down policy parameter for the processor.
amdsmi_get_soc_pstate
amdsmi_status_t amdsmi_get_soc_pstate(amdsmi_processor_handle processor_handle, amdsmi_dpm_policy_t *policy)
Get the soc pstate policy for the processor.
amdsmi_set_soc_pstate
amdsmi_status_t amdsmi_set_soc_pstate(amdsmi_processor_handle processor_handle, uint32_t policy_id)
Set the soc pstate policy for the processor.
amdsmi_reset_gpu
amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle)
Reset the gpu associated with the device with provided processor handle. It is not supported on virtu...
amdsmi_get_gpu_total_ecc_count
amdsmi_status_t amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec)
Returns the total number of ECC errors (correctable, uncorrectable and deferred) in the given GPU....
amdsmi_get_gpu_ecc_count
amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_gpu_block_t block, amdsmi_error_count_t *ec)
Retrieve the error counts for a GPU block. It is not supported on virtual machine guest.
amdsmi_get_gpu_ecc_enabled
amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle, uint64_t *enabled_blocks)
Retrieve the enabled ECC bit-mask. It is not supported on virtual machine guest.
amdsmi_status_code_to_string
amdsmi_status_t amdsmi_status_code_to_string(amdsmi_status_t status, const char **status_string)
Get a description of a provided AMDSMI error status.
amdsmi_event_destroy
amdsmi_status_t amdsmi_event_destroy(amdsmi_event_set set)
Destroys and frees an event set.
amdsmi_event_read
amdsmi_status_t amdsmi_event_read(amdsmi_event_set set, int64_t timeout_usec, amdsmi_event_entry_t *event)
The call blocks till timeout is expired to copy one event specified by the event set into the user pr...
amdsmi_event_create
amdsmi_status_t amdsmi_event_create(amdsmi_processor_handle *processor_list, uint32_t num_devices, uint64_t event_types, amdsmi_event_set *set)
Allocate a new event set notifier to monitor different types of issues with the GPU running virtualiz...
amdsmi_get_gpu_vbios_info
amdsmi_status_t amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info)
Returns the static information for the vBIOS on the device.
amdsmi_get_fw_info
amdsmi_status_t amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info)
Returns the firmware versions running on the device.
amdsmi_get_dfc_fw_table
amdsmi_status_t amdsmi_get_dfc_fw_table(amdsmi_processor_handle processor_handle, amdsmi_dfc_fw_t *info)
Returns the DFC fw table.
amdsmi_get_fw_error_records
amdsmi_status_t amdsmi_get_fw_error_records(amdsmi_processor_handle processor_handle, amdsmi_fw_error_record_t *records)
Gets firmware error records.
amdsmi_get_power_info
amdsmi_status_t amdsmi_get_power_info(amdsmi_processor_handle processor_handle, amdsmi_power_info_t *info)
Returns the current power and voltage of the GPU.
amdsmi_get_gpu_metrics
amdsmi_status_t amdsmi_get_gpu_metrics(amdsmi_processor_handle processor_handle, uint32_t *metrics_size, amdsmi_metric_t *metrics)
Return metrics information.
amdsmi_get_temp_metric
amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle, amdsmi_temperature_type_t sensor_type, amdsmi_temperature_metric_t metric, int64_t *temperature)
Get the temperature metric value for the specified metric, from the specified temperature sensor on t...
amdsmi_get_gpu_activity
amdsmi_status_t amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info)
Returns the current usage of the GPU engines (GFX, MM and MEM). Each usage is reported as a percentag...
amdsmi_get_clock_info
amdsmi_status_t amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info)
Returns the measurements of the clocks in the GPU for the GFX and multimedia engines and Memory....
amdsmi_is_gpu_power_management_enabled
amdsmi_status_t amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled)
Returns is power management enabled.
amdsmi_get_xgmi_fb_sharing_caps
amdsmi_status_t amdsmi_get_xgmi_fb_sharing_caps(amdsmi_processor_handle processor_handle, amdsmi_xgmi_fb_sharing_caps_t *caps)
Return XGMI capabilities.
amdsmi_set_xgmi_fb_sharing_mode_v2
amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode_v2(amdsmi_processor_handle *processor_list, uint32_t num_processors, amdsmi_xgmi_fb_sharing_mode_t mode)
Set XGMI framebuffer custom sharing mode.
amdsmi_get_xgmi_fb_sharing_mode_info
amdsmi_status_t amdsmi_get_xgmi_fb_sharing_mode_info(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_xgmi_fb_sharing_mode_t mode, uint8_t *fb_sharing)
Return XGMI framebuffer sharing information between two GPUs.
amdsmi_topo_get_numa_node_number
amdsmi_status_t amdsmi_topo_get_numa_node_number(amdsmi_processor_handle processor_handle, uint32_t *numa_node)
Retrieve the NUMA CPU node number for a device.
amdsmi_get_link_topology
amdsmi_status_t amdsmi_get_link_topology(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_link_topology_t *topology_info)
Return link topology information between two connected processors.
amdsmi_get_link_metrics
amdsmi_status_t amdsmi_get_link_metrics(amdsmi_processor_handle processor_handle, amdsmi_link_metrics_t *link_metrics)
Return link metric information.
amdsmi_topo_get_p2p_status
amdsmi_status_t amdsmi_topo_get_p2p_status(amdsmi_processor_handle processor_handle_src, amdsmi_processor_handle processor_handle_dst, amdsmi_link_type_t *type, amdsmi_p2p_capability_t *cap)
Retrieve connection type and P2P capabilities between 2 GPUs.
amdsmi_set_xgmi_fb_sharing_mode
amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode(amdsmi_processor_handle processor_handle, amdsmi_xgmi_fb_sharing_mode_t mode)
Set XGMI framebuffer sharing mode.
amdsmi_get_link_topology_nearest
amdsmi_status_t amdsmi_get_link_topology_nearest(amdsmi_processor_handle processor_handle, amdsmi_link_type_t link_type, amdsmi_topology_nearest_t *topology_nearest_info)
Retrieve the set of GPUs that are nearest to a given device at a specific interconnectivity level.
amdsmi_get_guest_data
amdsmi_status_t amdsmi_get_guest_data(amdsmi_vf_handle_t vf_handle, amdsmi_guest_data_t *info)
Returns guest OS information of the queried VF. The fw_info field from the amdsmi_guest_data structur...
amdsmi_get_vf_fw_info
amdsmi_status_t amdsmi_get_vf_fw_info(amdsmi_vf_handle_t vf_handle, amdsmi_fw_info_t *info)
Returns the firmware versions running on a VF. In case the VM is not started on the VF,...
amdsmi_shut_down
amdsmi_status_t amdsmi_shut_down(void)
Shutdown the AMD SMI library.
amdsmi_init
amdsmi_status_t amdsmi_init(uint64_t init_flags)
Initialize the AMD SMI library.
amdsmi_get_gpu_memory_partition_config
amdsmi_status_t amdsmi_get_gpu_memory_partition_config(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_config_t *config)
Returns current gpu memory partition capabilities.
amdsmi_set_gpu_memory_partition_mode
amdsmi_status_t amdsmi_set_gpu_memory_partition_mode(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_type_t mode)
Sets memory partition mode Set memory partition setting based on memory_partition mode from amdsmi_ge...
amdsmi_get_nic_rdma_dev_info
amdsmi_status_t amdsmi_get_nic_rdma_dev_info(amdsmi_processor_handle processor_handle, amdsmi_nic_rdma_devices_info_t *info)
Retrieves RDMA devices information for the NIC.
amdsmi_get_nic_rdma_port_statistics
amdsmi_status_t amdsmi_get_nic_rdma_port_statistics(amdsmi_processor_handle processor_handle, uint32_t rdma_port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)
Retrieve RDMA port statistics for the NIC.
amdsmi_get_nic_port_info
amdsmi_status_t amdsmi_get_nic_port_info(amdsmi_processor_handle processor_handle, amdsmi_nic_port_info_t *info)
Retrieves PORT information for the NIC.
amdsmi_get_nic_vendor_statistics
amdsmi_status_t amdsmi_get_nic_vendor_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)
Retrieve vendor specific statistics for the NIC port.
amdsmi_get_nic_port_statistics
amdsmi_status_t amdsmi_get_nic_port_statistics(amdsmi_processor_handle processor_handle, uint32_t port_index, uint32_t *num_stats, amdsmi_nic_stat_t *stats)
Retrieve PORT statistics for the specified NIC port.
amdsmi_get_nic_driver_info
amdsmi_status_t amdsmi_get_nic_driver_info(amdsmi_processor_handle processor_handle, amdsmi_nic_driver_info_t *info)
Retrieves information about the NIC driver.
amdsmi_get_nic_bus_info
amdsmi_status_t amdsmi_get_nic_bus_info(amdsmi_processor_handle processor_handle, amdsmi_nic_bus_info_t *info)
Retrieves BUS information for the NIC.
amdsmi_get_nic_asic_info
amdsmi_status_t amdsmi_get_nic_asic_info(amdsmi_processor_handle processor_handle, amdsmi_nic_asic_info_t *info)
Retrieves ASIC information for the NIC.
amdsmi_get_nic_numa_info
amdsmi_status_t amdsmi_get_nic_numa_info(amdsmi_processor_handle processor_handle, amdsmi_nic_numa_info_t *info)
Retrieves NUMA information for the NIC.
amdsmi_get_gpu_cache_info
amdsmi_status_t amdsmi_get_gpu_cache_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info)
Returns gpu cache info.
amdsmi_set_power_cap
amdsmi_status_t amdsmi_set_power_cap(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, uint64_t cap)
Set the maximum gpu power cap value. It is not supported on virtual machine guest.
amdsmi_get_processor_handles
amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle, uint32_t *processor_count, amdsmi_processor_handle *processor_handles)
Get the list of the processor handles associated to a socket.
amdsmi_get_processor_type
amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle, amdsmi_processor_type_t *processor_type)
Get the processor type of the processor_handle.
amdsmi_get_processor_handles_by_type
amdsmi_status_t amdsmi_get_processor_handles_by_type(amdsmi_socket_handle socket_handle, amdsmi_processor_type_t processor_type, amdsmi_processor_handle *processor_handles, uint32_t *processor_count)
Returns a list of processor handles of the specified type in the system.
amdsmi_get_index_from_processor_handle
amdsmi_status_t amdsmi_get_index_from_processor_handle(amdsmi_processor_handle processor_handle, uint32_t *processor_index)
Returns the index of the given processor handle.
amdsmi_get_gpu_device_uuid
amdsmi_status_t amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid)
Returns the UUID of the device.
amdsmi_get_socket_info
amdsmi_status_t amdsmi_get_socket_info(amdsmi_socket_handle socket_handle, size_t len, char *name)
Get information about the given socket.
amdsmi_get_gpu_virtualization_mode
amdsmi_status_t amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle, amdsmi_virtualization_mode_t *mode)
Returns the virtualization mode for the target device.
amdsmi_get_nic_device_bdf
amdsmi_status_t amdsmi_get_nic_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given NIC device.
amdsmi_get_processor_handle_from_uuid
amdsmi_status_t amdsmi_get_processor_handle_from_uuid(const char *uuid, amdsmi_processor_handle *processor_handle)
Returns the processor handle from the given UUID.
amdsmi_get_socket_handles
amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count, amdsmi_socket_handle *socket_handles)
Get the list of socket handles in the system.
amdsmi_get_vf_bdf
amdsmi_status_t amdsmi_get_vf_bdf(amdsmi_vf_handle_t vf_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given device (VF).
amdsmi_get_vf_handle_from_bdf
amdsmi_status_t amdsmi_get_vf_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_vf_handle_t *vf_handle)
Returns VF handle from the given BDF.
amdsmi_get_processor_handle_from_bdf
amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_processor_handle *processor_handle)
Get processor handle with the matching bdf.
amdsmi_get_vf_handle_from_vf_index
amdsmi_status_t amdsmi_get_vf_handle_from_vf_index(amdsmi_processor_handle processor_handle, uint32_t fcn_idx, amdsmi_vf_handle_t *vf_handle)
Returns the handle of a virtual function given its index.
amdsmi_get_vf_uuid
amdsmi_status_t amdsmi_get_vf_uuid(amdsmi_vf_handle_t processor_handle, unsigned int *uuid_length, char *uuid)
Returns the UUID of the VF.
amdsmi_get_gpu_device_bdf
amdsmi_status_t amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given GPU device.
amdsmi_get_processor_bdf
amdsmi_status_t amdsmi_get_processor_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given device.
amdsmi_get_vf_handle_from_uuid
amdsmi_status_t amdsmi_get_vf_handle_from_uuid(const char *uuid, amdsmi_vf_handle_t *vf_handle)
Returns the handle of a virtual function from the given UUID.
amdsmi_get_cpu_affinity_with_scope
amdsmi_status_t amdsmi_get_cpu_affinity_with_scope(amdsmi_processor_handle processor_handle, uint32_t cpu_set_size, uint64_t *cpu_set, amdsmi_affinity_scope_t scope)
Retrieves an array of uint64_t (sized to cpu_set_size) of bitmasks with the affinity within numa node...
amdsmi_get_processor_handle_from_index
amdsmi_status_t amdsmi_get_processor_handle_from_index(uint32_t processor_index, amdsmi_processor_handle *processor_handle)
Returns the processor handle from the given processor index.
amdsmi_get_afids_from_cper
amdsmi_status_t amdsmi_get_afids_from_cper(char *cper_buffer, uint32_t buf_size, uint64_t *afids, uint32_t *num_afids)
Get the AFIDs from CPER buffer.
amdsmi_get_bad_page_threshold
amdsmi_status_t amdsmi_get_bad_page_threshold(amdsmi_processor_handle processor_handle, uint32_t *threshold)
Get the bad page threshold for a device.
amdsmi_get_gpu_cper_entries
amdsmi_status_t amdsmi_get_gpu_cper_entries(amdsmi_processor_handle processor_handle, uint32_t severity_mask, char *cper_data, uint64_t *buf_size, amdsmi_cper_hdr_t **cper_hdrs, uint64_t *entry_count, uint64_t *cursor)
Retrieve CPER entries cached in the driver.
amdsmi_get_gpu_ras_feature_info
amdsmi_status_t amdsmi_get_gpu_ras_feature_info(amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature)
Returns RAS features info.
amdsmi_get_gpu_bad_page_info
amdsmi_status_t amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *bad_page_size, amdsmi_eeprom_table_record_t *bad_pages)
Returns the bad page info.
amdsmi_get_gpu_driver_info
amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info)
Returns the driver version information.
amdsmi_get_gpu_driver_model
amdsmi_status_t amdsmi_get_gpu_driver_model(amdsmi_processor_handle processor_handle, amdsmi_driver_model_type_t *model)
Returns the driver model information.
amdsmi_get_vf_info
amdsmi_status_t amdsmi_get_vf_info(amdsmi_vf_handle_t vf_handle, amdsmi_vf_info_t *config)
Returns the configuration structure for a VF.
amdsmi_get_vf_data
amdsmi_status_t amdsmi_get_vf_data(amdsmi_vf_handle_t vf_handle, amdsmi_vf_data_t *info)
Returns the data structure for a VF.
amdsmi_get_vf_partition_info
amdsmi_status_t amdsmi_get_vf_partition_info(amdsmi_processor_handle processor_handle, unsigned int vf_buffer_num, amdsmi_partition_info_t *info)
Returns the current framebuffer partitioning structure as currently configured by the driver.
amdsmi_get_num_vf
amdsmi_status_t amdsmi_get_num_vf(amdsmi_processor_handle processor_handle, uint32_t *num_vf_enabled, uint32_t *num_vf_supported)
Returns the number of VFs enabled by gpuv in the ASIC.
amdsmi_get_partition_profile_info
amdsmi_status_t amdsmi_get_partition_profile_info(amdsmi_processor_handle processor_handle, amdsmi_profile_info_t *profile_info)
Return the list of supported profiles on the given GPU device.
amdsmi_clear_vf_fb
amdsmi_status_t amdsmi_clear_vf_fb(amdsmi_vf_handle_t vf_handle)
Clear the framebuffer of a VF. If trying to clear the framebuffer of an active function,...
amdsmi_set_num_vf
amdsmi_status_t amdsmi_set_num_vf(amdsmi_processor_handle processor_handle, uint32_t num_vf)
Enable a given number of VF.
amdsmi_get_lib_version
amdsmi_status_t amdsmi_get_lib_version(amdsmi_version_t *version)
Get the build version information for the currently running build of AMDSMI.
amdsmi_accelerator_partition_profile_config_global_t
Definition: amdsmi.h:2381
amdsmi_accelerator_partition_profile_config_global_t::num_profiles
uint32_t num_profiles
The length of profiles array.
Definition: amdsmi.h:2382
amdsmi_accelerator_partition_profile_config_global_t::default_profile_index
uint32_t default_profile_index
The index of the default profile in the profiles array.
Definition: amdsmi.h:2385
amdsmi_accelerator_partition_profile_config_t
Accelerator Partition Profile Configurations.
Definition: amdsmi.h:890
amdsmi_accelerator_partition_profile_config_t::default_profile_index
uint32_t default_profile_index
The index of the default profile in the profiles array.
Definition: amdsmi.h:894
amdsmi_accelerator_partition_profile_config_t::num_profiles
uint32_t num_profiles
The length of profiles array.
Definition: amdsmi.h:891
amdsmi_accelerator_partition_profile_global_t
Definition: amdsmi.h:2375
amdsmi_accelerator_partition_profile_global_t::vf_mode
uint32_t vf_mode
Bitmask of VF modes (see amdsmi_vf_mode_t)
Definition: amdsmi.h:2377
amdsmi_accelerator_partition_profile_t
Accelerator Partition Resource Profile.
Definition: amdsmi.h:861
amdsmi_accelerator_partition_profile_t::profile_index
uint32_t profile_index
Index in the profiles array in amdsmi_accelerator_partition_profile_t.
Definition: amdsmi.h:865
amdsmi_accelerator_partition_profile_t::num_partitions
uint32_t num_partitions
On MI300X: SPX=>1, DPX=>2, QPX=>4, CPX=>8; length of resources.
Definition: amdsmi.h:863
amdsmi_accelerator_partition_profile_t::memory_caps
amdsmi_nps_caps_t memory_caps
Possible memory partition capabilities.
Definition: amdsmi.h:864
amdsmi_accelerator_partition_profile_t::profile_type
amdsmi_accelerator_partition_type_t profile_type
SPX, DPX, QPX, CPX and so on.
Definition: amdsmi.h:862
amdsmi_accelerator_partition_profile_t::num_resources
uint32_t num_resources
length of index_of_resources_profile
Definition: amdsmi.h:866
amdsmi_accelerator_partition_resource_profile_t
Accelerator Partition Resources. This struct is used to identify various partition resource profiles.
Definition: amdsmi.h:877
amdsmi_accelerator_partition_resource_profile_t::partition_resource
uint32_t partition_resource
Resources a partition can use, which may be shared.
Definition: amdsmi.h:880
amdsmi_accelerator_partition_resource_profile_t::num_partitions_share_resource
uint32_t num_partitions_share_resource
If it is greater than 1, then resource is shared.
Definition: amdsmi.h:881
amdsmi_asic_info_t
ASIC Information.
Definition: amdsmi.h:723
amdsmi_asic_info_t::target_graphics_version
uint64_t target_graphics_version
0xFFFFFFFFFFFFFFFF if not supported
Definition: amdsmi.h:733
amdsmi_asic_info_t::vendor_id
uint32_t vendor_id
Use 32 bit to be compatible with other platform.
Definition: amdsmi.h:725
amdsmi_asic_info_t::device_id
uint64_t device_id
The device ID of a GPU.
Definition: amdsmi.h:728
amdsmi_asic_info_t::oam_id
uint32_t oam_id
0xFFFFFFFF if not supported
Definition: amdsmi.h:731
amdsmi_asic_info_t::num_of_compute_units
uint32_t num_of_compute_units
0xFFFFFFFF if not supported
Definition: amdsmi.h:732
amdsmi_asic_info_t::subvendor_id
uint32_t subvendor_id
The subsystem vendor ID.
Definition: amdsmi.h:727
amdsmi_asic_info_t::rev_id
uint32_t rev_id
The revision ID of a GPU.
Definition: amdsmi.h:729
amdsmi_bdf_t::bdf_
Definition: amdsmi.h:626
amdsmi_board_info_t
Board Information.
Definition: amdsmi.h:904
amdsmi_clk_info_t
Clock Information.
Definition: amdsmi.h:801
amdsmi_clk_info_t::clk
uint32_t clk
In MHz.
Definition: amdsmi.h:802
amdsmi_clk_info_t::clk_locked
uint8_t clk_locked
True/False.
Definition: amdsmi.h:805
amdsmi_clk_info_t::clk_deep_sleep
uint8_t clk_deep_sleep
True/False.
Definition: amdsmi.h:806
amdsmi_clk_info_t::min_clk
uint32_t min_clk
In MHz.
Definition: amdsmi.h:803
amdsmi_clk_info_t::max_clk
uint32_t max_clk
In MHz.
Definition: amdsmi.h:804
amdsmi_cper_guid_t
Cper.
Definition: amdsmi.h:1043
amdsmi_cper_hdr_t
Definition: amdsmi.h:1068
amdsmi_cper_hdr_t::notify_type
amdsmi_cper_guid_t notify_type
CMC, MCE, can use amdsmi_cper_notifiy_type_t to decode.
Definition: amdsmi.h:1080
amdsmi_cper_hdr_t::persistence_info
uint64_t persistence_info
Reserved.
Definition: amdsmi.h:1083
amdsmi_cper_hdr_t::signature_end
uint32_t signature_end
0xFFFFFFFF
Definition: amdsmi.h:1071
amdsmi_cper_hdr_t::flags
uint32_t flags
Reserved.
Definition: amdsmi.h:1082
amdsmi_cper_hdr_t::partition_id
amdsmi_cper_guid_t partition_id
Reserved.
Definition: amdsmi.h:1078
amdsmi_cper_hdr_t::record_length
uint32_t record_length
Total size of CPER Entry.
Definition: amdsmi.h:1075
amdsmi_cper_timestamp_t
Definition: amdsmi.h:1047
amdsmi_cper_valid_bits_t::valid_bits_
Definition: amdsmi.h:1059
amdsmi_dfc_fw_data_t
DFC Firmware Data.
Definition: amdsmi.h:2236
amdsmi_dfc_fw_data_t::customer_ordinal
uint32_t customer_ordinal
only used in driver version on NV32+
Definition: amdsmi.h:2239
amdsmi_dfc_fw_header_t
DFC Firmware Header.
Definition: amdsmi.h:2204
amdsmi_dfc_fw_t
DFC Firmware.
Definition: amdsmi.h:2253
amdsmi_dfc_fw_ta_uuid_t
DFC Firmware TA UUID.
Definition: amdsmi.h:2227
amdsmi_dfc_fw_white_list_t
DFC Firmware White List.
Definition: amdsmi.h:2217
amdsmi_dpm_policy_entry_t
The dpm policy.
Definition: amdsmi.h:964
amdsmi_dpm_policy_t
DPM Policy.
Definition: amdsmi.h:976
amdsmi_dpm_policy_t::num_supported
uint32_t num_supported
The number of supported policies.
Definition: amdsmi.h:977
amdsmi_dpm_policy_t::current
uint32_t current
The current policy index.
Definition: amdsmi.h:978
amdsmi_driver_info_t
Driver Information.
Definition: amdsmi.h:759
amdsmi_eeprom_table_record_t
Structure representing an EEPROM table record for tracking memory errors.
Definition: amdsmi.h:2267
amdsmi_eeprom_table_record_t::retired_page
uint64_t retired_page
Bad page frame address.
Definition: amdsmi.h:2268
amdsmi_engine_usage_t
Engine Usage amdsmi_engine_usage_t: This structure holds common GPU activity values seen in both BM o...
Definition: amdsmi.h:789
amdsmi_engine_usage_t::gfx_activity
uint32_t gfx_activity
In %.
Definition: amdsmi.h:790
amdsmi_engine_usage_t::umc_activity
uint32_t umc_activity
In %.
Definition: amdsmi.h:791
amdsmi_engine_usage_t::mm_activity
uint32_t mm_activity
In %.
Definition: amdsmi.h:792
amdsmi_error_count_t
This structure holds error counts.
Definition: amdsmi.h:815
amdsmi_error_count_t::uncorrectable_count
uint64_t uncorrectable_count
Accumulated uncorrectable errors.
Definition: amdsmi.h:817
amdsmi_error_count_t::correctable_count
uint64_t correctable_count
Accumulated correctable errors.
Definition: amdsmi.h:816
amdsmi_error_count_t::deferred_count
uint64_t deferred_count
Accumulated deferred errors.
Definition: amdsmi.h:818
amdsmi_event_entry_t
Event Entry.
Definition: amdsmi.h:2032
amdsmi_event_entry_t::timestamp
uint64_t timestamp
UTC microseconds.
Definition: amdsmi.h:2035
amdsmi_fw_error_record_t
Firmware Error Record.
Definition: amdsmi.h:2298
amdsmi_fw_info_t
Firmware Information.
Definition: amdsmi.h:949
amdsmi_fw_load_error_record_t
Firmware Load Error Record.
Definition: amdsmi.h:2285
amdsmi_fw_load_error_record_t::timestamp
uint64_t timestamp
UTC microseconds.
Definition: amdsmi.h:2286
amdsmi_fw_load_error_record_t::status
uint16_t status
amdsmi_guest_fw_load_status
Definition: amdsmi.h:2289
amdsmi_gpu_cache_info_t::cache_
Definition: amdsmi.h:933
amdsmi_gpu_cache_info_t::cache_::num_cache_instance
uint32_t num_cache_instance
total number of instance of this cache type
Definition: amdsmi.h:938
amdsmi_gpu_cache_info_t::cache_::cache_size
uint32_t cache_size
In KB.
Definition: amdsmi.h:935
amdsmi_gpu_cache_info_t::cache_::max_num_cu_shared
uint32_t max_num_cu_shared
Indicates how many Compute Units share this cache instance.
Definition: amdsmi.h:937
amdsmi_gpu_cache_info_t::cache_::cache_properties
uint32_t cache_properties
amdsmi_cache_property_type_t which is a bitmask
Definition: amdsmi.h:934
amdsmi_gpu_cache_info_t
GPU Cache Information.
Definition: amdsmi.h:931
amdsmi_guard_info_t
Guard Information.
Definition: amdsmi.h:2097
amdsmi_guest_data_t
Guest Data.
Definition: amdsmi.h:2193
amdsmi_guest_data_t::fb_usage
uint32_t fb_usage
guest framebuffer usage in MB
Definition: amdsmi.h:2195
amdsmi_handshake_t
Handshake.
Definition: amdsmi.h:2051
amdsmi_link_metrics_t::_links
Definition: amdsmi.h:677
amdsmi_link_metrics_t::_links::write
uint64_t write
total data transfered for each link in KB
Definition: amdsmi.h:683
amdsmi_link_metrics_t::_links::link_status
amdsmi_link_status_t link_status
HW status of the link.
Definition: amdsmi.h:684
amdsmi_link_metrics_t::_links::read
uint64_t read
total data received for each link in KB
Definition: amdsmi.h:682
amdsmi_link_metrics_t::_links::bit_rate
uint32_t bit_rate
current link speed in Gb/s
Definition: amdsmi.h:679
amdsmi_link_metrics_t::_links::link_type
amdsmi_link_type_t link_type
type of the link
Definition: amdsmi.h:681
amdsmi_link_metrics_t::_links::bdf
amdsmi_bdf_t bdf
bdf of the destination gpu
Definition: amdsmi.h:678
amdsmi_link_metrics_t::_links::max_bandwidth
uint32_t max_bandwidth
max bandwidth of the link in Gb/s
Definition: amdsmi.h:680
amdsmi_link_metrics_t
Link Metrics.
Definition: amdsmi.h:675
amdsmi_link_metrics_t::num_links
uint32_t num_links
number of links
Definition: amdsmi.h:676
amdsmi_link_topology_t
Link Topology.
Definition: amdsmi.h:2309
amdsmi_link_topology_t::weight
uint64_t weight
link weight
Definition: amdsmi.h:2310
amdsmi_link_topology_t::link_type
amdsmi_link_type_t link_type
type of the link
Definition: amdsmi.h:2312
amdsmi_link_topology_t::num_hops
uint8_t num_hops
number of hops
Definition: amdsmi.h:2313
amdsmi_link_topology_t::link_status
amdsmi_link_status_t link_status
HW status of the link.
Definition: amdsmi.h:2311
amdsmi_link_topology_t::fb_sharing
uint8_t fb_sharing
framebuffer sharing flag
Definition: amdsmi.h:2314
amdsmi_memory_partition_config_t::numa_range_
Definition: amdsmi.h:848
amdsmi_memory_partition_config_t
Memory Partition Configuration. This structure is used to identify various memory partition configura...
Definition: amdsmi.h:844
amdsmi_metric_t
Metric.
Definition: amdsmi.h:2351
amdsmi_metric_t::res_group
amdsmi_metric_res_group_t res_group
Resource group this metric belongs to.
Definition: amdsmi.h:2358
amdsmi_metric_t::res_subgroup
amdsmi_metric_res_subgroup_t res_subgroup
Resource subgroup this metric belongs to.
Definition: amdsmi.h:2359
amdsmi_metric_t::flags
uint32_t flags
used to determine type of the metric (amdsmi_metric_type_t)
Definition: amdsmi.h:2355
amdsmi_metric_t::res_instance
uint32_t res_instance
Resource instance this metric belongs to.
Definition: amdsmi.h:2360
amdsmi_metric_t::vf_mask
uint32_t vf_mask
Mask of all active VFs + PF that this metric applies to.
Definition: amdsmi.h:2356
amdsmi_nic_asic_info_t
NIC asic information.
Definition: amdsmi.h:2416
amdsmi_nic_bus_info_t
NIC bus information.
Definition: amdsmi.h:2434
amdsmi_nic_bus_info_t::max_pcie_speed
uint32_t max_pcie_speed
maximum PCIe speed in GT/s
Definition: amdsmi.h:2437
amdsmi_nic_driver_info_t
NIC driver information.
Definition: amdsmi.h:2511
amdsmi_nic_fw_info_t
NIC firmware information collection.
Definition: amdsmi.h:2467
amdsmi_nic_fw_t
NIC firmware information.
Definition: amdsmi.h:2457
amdsmi_nic_numa_info_t
NIC NUMA information.
Definition: amdsmi.h:2447
amdsmi_nic_port_info_t
NIC port information collection.
Definition: amdsmi.h:2501
amdsmi_nic_port_t
NIC port information.
Definition: amdsmi.h:2477
amdsmi_nic_rdma_dev_info_t
NIC RDMA device information.
Definition: amdsmi.h:2534
amdsmi_nic_rdma_devices_info_t
NIC RDMA devices information collection.
Definition: amdsmi.h:2549
amdsmi_nic_rdma_port_info_t
NIC RDMA port information.
Definition: amdsmi.h:2521
amdsmi_nic_stat_t
Structure for NIC statistic name-value pairs.
Definition: amdsmi.h:2406
amdsmi_nps_caps_t::nps_flags_
Definition: amdsmi.h:828
amdsmi_nps_caps_t::nps_flags_::nps8_cap
uint32_t nps8_cap
bool 1 = true; 0 = false
Definition: amdsmi.h:832
amdsmi_nps_caps_t::nps_flags_::nps4_cap
uint32_t nps4_cap
bool 1 = true; 0 = false
Definition: amdsmi.h:831
amdsmi_nps_caps_t::nps_flags_::nps2_cap
uint32_t nps2_cap
bool 1 = true; 0 = false
Definition: amdsmi.h:830
amdsmi_nps_caps_t::nps_flags_::nps1_cap
uint32_t nps1_cap
bool 1 = true; 0 = false
Definition: amdsmi.h:829
amdsmi_p2p_capability_t
IO Link P2P Capability.
Definition: amdsmi.h:918
amdsmi_p2p_capability_t::is_iolink_atomics_64bit
uint8_t is_iolink_atomics_64bit
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:921
amdsmi_p2p_capability_t::is_iolink_atomics_32bit
uint8_t is_iolink_atomics_32bit
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:920
amdsmi_p2p_capability_t::is_iolink_bi_directional
uint8_t is_iolink_bi_directional
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:923
amdsmi_p2p_capability_t::is_iolink_coherent
uint8_t is_iolink_coherent
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:919
amdsmi_p2p_capability_t::is_iolink_dma
uint8_t is_iolink_dma
1 = true, 0 = false, UINT8_MAX = Not defined
Definition: amdsmi.h:922
amdsmi_partition_info_t
Partition Information.
Definition: amdsmi.h:2086
amdsmi_pcie_info_t::pcie_metric_
Definition: amdsmi.h:655
amdsmi_pcie_info_t::pcie_metric_::pcie_nak_received_count
uint64_t pcie_nak_received_count
total number of NAKs issued on the PCIe link by the receiver
Definition: amdsmi.h:663
amdsmi_pcie_info_t::pcie_metric_::pcie_replay_count
uint64_t pcie_replay_count
total number of the replays issued on the PCIe link
Definition: amdsmi.h:659
amdsmi_pcie_info_t::pcie_metric_::pcie_width
uint16_t pcie_width
current PCIe width
Definition: amdsmi.h:656
amdsmi_pcie_info_t::pcie_metric_::pcie_speed
uint32_t pcie_speed
current PCIe speed in MT/s
Definition: amdsmi.h:657
amdsmi_pcie_info_t::pcie_metric_::pcie_bandwidth
uint32_t pcie_bandwidth
current PCIe bandwidth in Mb/s
Definition: amdsmi.h:658
amdsmi_pcie_info_t::pcie_metric_::pcie_l0_to_recovery_count
uint64_t pcie_l0_to_recovery_count
total number of times the PCIe link transitioned from L0 to the recovery state
Definition: amdsmi.h:660
amdsmi_pcie_info_t::pcie_metric_::pcie_nak_sent_count
uint64_t pcie_nak_sent_count
total number of NAKs issued on the PCIe link by the device
Definition: amdsmi.h:662
amdsmi_pcie_info_t::pcie_metric_::pcie_replay_roll_over_count
uint64_t pcie_replay_roll_over_count
total number of replay rollovers issued on the PCIe link
Definition: amdsmi.h:661
amdsmi_pcie_info_t::pcie_metric_::pcie_lc_perf_other_end_recovery_count
uint32_t pcie_lc_perf_other_end_recovery_count
PCIe other end recovery counter.
Definition: amdsmi.h:664
amdsmi_pcie_info_t::pcie_static_
Definition: amdsmi.h:647
amdsmi_pcie_info_t::pcie_static_::max_pcie_width
uint16_t max_pcie_width
maximum number of PCIe lanes
Definition: amdsmi.h:648
amdsmi_pcie_info_t::pcie_static_::max_pcie_interface_version
uint32_t max_pcie_interface_version
maximum PCIe link generation
Definition: amdsmi.h:652
amdsmi_pcie_info_t::pcie_static_::slot_type
amdsmi_card_form_factor_t slot_type
card form factor
Definition: amdsmi.h:651
amdsmi_pcie_info_t::pcie_static_::max_pcie_speed
uint32_t max_pcie_speed
maximum PCIe speed in GT/s
Definition: amdsmi.h:649
amdsmi_pcie_info_t::pcie_static_::pcie_interface_version
uint32_t pcie_interface_version
PCIe interface version.
Definition: amdsmi.h:650
amdsmi_pcie_info_t
pcie information
Definition: amdsmi.h:646
amdsmi_pf_fb_info_t
PF FB Information.
Definition: amdsmi.h:2060
amdsmi_pf_fb_info_t::pf_fb_reserved
uint32_t pf_fb_reserved
Total fb consumed by PF.
Definition: amdsmi.h:2062
amdsmi_pf_fb_info_t::min_vf_fb_usable
uint32_t min_vf_fb_usable
Minimum usable fb size in MB.
Definition: amdsmi.h:2066
amdsmi_pf_fb_info_t::fb_alignment
uint32_t fb_alignment
FB alignment.
Definition: amdsmi.h:2064
amdsmi_pf_fb_info_t::total_fb_size
uint32_t total_fb_size
Total GPU fb size in MB.
Definition: amdsmi.h:2061
amdsmi_pf_fb_info_t::max_vf_fb_usable
uint32_t max_vf_fb_usable
Maximum usable fb size in MB.
Definition: amdsmi.h:2065
amdsmi_pf_fb_info_t::pf_fb_offset
uint32_t pf_fb_offset
PF FB offset.
Definition: amdsmi.h:2063
amdsmi_power_cap_info_t
Power Cap Information.
Definition: amdsmi.h:695
amdsmi_power_cap_info_t::power_cap
uint64_t power_cap
current power cap Units uW {@linux_bm} or W {@host}
Definition: amdsmi.h:696
amdsmi_power_cap_info_t::dpm_cap
uint64_t dpm_cap
dpm power cap Units MHz {@linux_bm} or Hz {@host}
Definition: amdsmi.h:698
amdsmi_power_cap_info_t::max_power_cap
uint64_t max_power_cap
maximum power cap Units uW {@linux_bm} or W {@host}
Definition: amdsmi.h:700
amdsmi_power_cap_info_t::default_power_cap
uint64_t default_power_cap
default power cap Units uW {@linux_bm} or W {@host}
Definition: amdsmi.h:697
amdsmi_power_cap_info_t::min_power_cap
uint64_t min_power_cap
minimum power cap Units uW {@linux_bm} or W {@host}
Definition: amdsmi.h:699
amdsmi_power_info_t
Power Information.
Definition: amdsmi.h:743
amdsmi_power_info_t::soc_voltage
uint64_t soc_voltage
SOC voltage measurement in mV {@linux_bm} or V {@host}.
Definition: amdsmi.h:748
amdsmi_power_info_t::socket_power
uint64_t socket_power
Socket power in W {@linux_bm}, uW {@host}.
Definition: amdsmi.h:744
amdsmi_power_info_t::power_limit
uint32_t power_limit
The power limit in W {@linux_bm}, Linux only.
Definition: amdsmi.h:750
amdsmi_power_info_t::mem_voltage
uint64_t mem_voltage
MEM voltage measurement in mV {@linux_bm} or V {@host}.
Definition: amdsmi.h:749
amdsmi_power_info_t::current_socket_power
uint32_t current_socket_power
Current socket power in W {@linux_bm}, Linux only, Mi 300+ Series cards.
Definition: amdsmi.h:745
amdsmi_power_info_t::average_socket_power
uint32_t average_socket_power
Average socket power in W {@linux_bm}, Linux only, Navi + Mi 200 and earlier Series cards.
Definition: amdsmi.h:746
amdsmi_power_info_t::gfx_voltage
uint64_t gfx_voltage
GFX voltage measurement in mV {@linux_bm} or V {@host}.
Definition: amdsmi.h:747
amdsmi_profile_caps_info_t
Profile Caps Information.
Definition: amdsmi.h:2164
amdsmi_profile_info_t
Profile Information.
Definition: amdsmi.h:2178
amdsmi_ras_feature_t
This structure holds ras feature information.
Definition: amdsmi.h:987
amdsmi_ras_feature_t::ras_eeprom_version
uint32_t ras_eeprom_version
Definition: amdsmi.h:995
amdsmi_ras_feature_t::ecc_correction_schema_flag
uint32_t ecc_correction_schema_flag
Definition: amdsmi.h:997
amdsmi_sched_info_t
Schedule Information.
Definition: amdsmi.h:2129
amdsmi_sched_info_t::boot_up_time
uint64_t boot_up_time
in microseconds
Definition: amdsmi.h:2131
amdsmi_topology_nearest_t
Topology Nearest.
Definition: amdsmi.h:2323
amdsmi_vbios_info_t
VBios Information.
Definition: amdsmi.h:709
amdsmi_version_t
This structure holds version information.
Definition: amdsmi.h:2369
amdsmi_version_t::minor
uint32_t minor
Minor version.
Definition: amdsmi.h:2371
amdsmi_version_t::major
uint32_t major
Major version.
Definition: amdsmi.h:2370
amdsmi_version_t::release
uint32_t release
Patch, build or stepping version.
Definition: amdsmi.h:2372
amdsmi_vf_data_t
VF Data.
Definition: amdsmi.h:2153
amdsmi_vf_fb_info_t
VF FB Information.
Definition: amdsmi.h:2075
amdsmi_vf_fb_info_t::fb_size
uint32_t fb_size
Size in MB Must be divisible by 16 and not less than 256.
Definition: amdsmi.h:2077
amdsmi_vf_fb_info_t::fb_offset
uint32_t fb_offset
Offset in MB from start of the framebuffer.
Definition: amdsmi.h:2076
amdsmi_vf_handle_t
VF Handle.
Definition: amdsmi.h:2023
amdsmi_vf_info_t
VF Information.
Definition: amdsmi.h:2118
amdsmi_vf_info_t::gfx_timeslice
uint32_t gfx_timeslice
Graphics timeslice in us, maximum value is 1000 ms.
Definition: amdsmi.h:2120
amdsmi_vram_info_t
VRam Information.
Definition: amdsmi.h:771
amdsmi_vram_info_t::vram_bit_width
uint32_t vram_bit_width
In bits.
Definition: amdsmi.h:775
amdsmi_vram_info_t::vram_size
uint64_t vram_size
vram size in MB
Definition: amdsmi.h:774
amdsmi_vram_info_t::vram_max_bandwidth
uint64_t vram_max_bandwidth
The VRAM max bandwidth at current memory clock (GB/s)
Definition: amdsmi.h:776
amdsmi_xgmi_fb_sharing_caps_t::cap_
Definition: amdsmi.h:2335
amdsmi_bdf_t
bdf types
Definition: amdsmi.h:625
amdsmi_cper_valid_bits_t
Definition: amdsmi.h:1058
amdsmi_nps_caps_t
This union holds memory partition bitmask.
Definition: amdsmi.h:827
amdsmi_xgmi_fb_sharing_caps_t
XGMI FB Sharing Caps.
Definition: amdsmi.h:2334