amdsmi.h Source File

amdsmi.h Source File#

AMD SMI: amdsmi.h Source File
amdsmi.h
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1 /*
2  * Copyright (c) 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy
5  * of this software and associated documentation files (the "Software"), to deal
6  * in the Software without restriction, including without limitation the rights
7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8  * copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20  * THE SOFTWARE.
21  */
22 
29 #ifndef __AMDSMI_H__
30 #define __AMDSMI_H__
31 
32 #ifndef __KERNEL__
33 #include <stdint.h>
34 #include <stdbool.h>
35 #include <stddef.h>
36 #endif
37 
43 typedef enum {
45  AMDSMI_INIT_AMD_CPUS = (1 << 0),
46  AMDSMI_INIT_AMD_GPUS = (1 << 1),
47  AMDSMI_INIT_NON_AMD_CPUS = (1 << 2),
48  AMDSMI_INIT_NON_AMD_GPUS = (1 << 3),
49  AMDSMI_INIT_AMD_APUS = (AMDSMI_INIT_AMD_CPUS | AMDSMI_INIT_AMD_GPUS) // Default option
51 
55 #define AMDSMI_MAX_DEVICES 32
56 #define AMDSMI_MAX_VF_COUNT 32
57 #define AMDSMI_PF_INDEX (AMDSMI_MAX_VF_COUNT - 1)
58 #define AMDSMI_MAX_STRING_LENGTH 256
59 #define AMDSMI_MAX_DRIVER_INFO_RSVD 64
60 #define AMDSMI_MAX_MM_IP_COUNT 8
61 #define AMDSMI_MAX_CACHE_TYPES 10
62 #define AMDSMI_MAX_NUM_PM_POLICIES 32
63 #define AMDSMI_MAX_NAME 32
64 
66 #define AMDSMI_MAX_DRIVER_NUM 2
67 
69 #define AMDSMI_MAX_DATE_LENGTH 32
70 
71 #define AMDSMI_GPU_UUID_SIZE 38
72 
73 #define AMDSMI_DFC_FW_NUMBER_OF_ENTRIES 9
74 
75 #define AMDSMI_MAX_WHITE_LIST_ELEMENTS 16
76 #define AMDSMI_MAX_BLACK_LIST_ELEMENTS 64
77 #define AMDSMI_MAX_UUID_ELEMENTS 16
78 #define AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS 8
79 
80 #define AMDSMI_MAX_ERR_RECORDS 10
81 
83 #define AMDSMI_EVENT_MSG_SIZE 256
84 
85 #define AMDSMI_MAX_PROFILE_COUNT 16
86 
90 #define AMDSMI_TIME_FORMAT "%02d:%02d:%02d.%03d"
91 #define AMDSMI_DATE_FORMAT "%04d-%02d-%02d:%02d:%02d:%02d.%03d"
92 
98 #define AMDSMI_MASK_ALL (~0ULL)
99 
101 #define AMDSMI_MASK_DEFAULT ((1ULL << 62) - 1)
102 
104 #define AMDSMI_MASK_INIT (0ULL)
105 
107 #define AMDSMI_MASK_HIGH_AND_MED_SEVERITY (~((1ULL << 61) - 1))
108 
112 #define AMDSMI_MASK_HIGH_ERROR_SEVERITY_ONLY(mask) (mask & ((1ULL << 60) - 1))
113 #define AMDSMI_MASK_INCLUDE_MED_ERROR_SEVERITY(mask) (mask | (1ULL << 60))
114 #define AMDSMI_MASK_INCLUDE_LOW_ERROR_SEVERITY(mask) (mask | (1ULL << 61))
115 #define AMDSMI_MASK_INCLUDE_WARN_SEVERITY(mask) (mask | (1ULL << 62))
116 #define AMDSMI_MASK_INCLUDE_INFO_SEVERITY(mask) (mask | (1ULL << 63))
117 
121 #define AMDSMI_MASK_HIGH_SEVERITY_ONLY(mask) (mask & ((1ULL << 62) - 1))
122 #define AMDSMI_MASK_INCLUDE_MED_SEVERITY(mask) AMDSMI_MASK_INCLUDE_WARN_SEVERITY(mask)
123 #define AMDSMI_MASK_INCLUDE_LOW_SEVERITY(mask) AMDSMI_MASK_INCLUDE_INFO_SEVERITY(mask)
124 
125 #define AMDSMI_MASK_INCLUDE_CATEGORY(mask, cate) (mask | (1ULL << cate))
126 #define AMDSMI_MASK_EXCLUDE_CATEGORY(mask, cate) (mask & (~(1ULL << cate)))
127 
128 #define AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK 64
129 #define AMDSMI_MAX_FB_SHARING_GROUPS 64
130 #define AMDSMI_MAX_NUM_CONNECTED_NODES 64
131 
132 #define AMDSMI_MAX_NUM_METRICS_V1 255
133 #define AMDSMI_MAX_NUM_METRICS AMDSMI_MAX_NUM_METRICS_V1
134 
135 #define AMDSMI_MAX_BAD_PAGE_RECORD_V1 512
136 #define AMDSMI_MAX_BAD_PAGE_RECORD_V2 16384
137 #define AMDSMI_MAX_BAD_PAGE_RECORD AMDSMI_MAX_BAD_PAGE_RECORD_V2
138 
139 #define AMDSMI_MAX_CP_PROFILE_RESOURCES 32
140 #define AMDSMI_MAX_ACCELERATOR_PARTITIONS 8
141 #define AMDSMI_MAX_ACCELERATOR_PROFILE 32
142 #define AMDSMI_MAX_NUM_NUMA_NODES 32
143 
144 #define MAX_NUMBER_OF_AFIDS_PER_RECORD 12
145 
147 typedef void *amdsmi_socket_handle;
148 typedef void *amdsmi_event_set;
149 typedef void *amdsmi_processor_handle;
150 
154 typedef enum {
156  // Library usage errors
176  AMDSMI_STATUS_MORE_DATA = 20,
177  // Processor related errors
183  // Data and size errors
188  //esmi errors
201 
202  // General errors
203  AMDSMI_STATUS_MAP_ERROR = 0xFFFFFFFE,
206 
210 typedef enum {
211  AMDSMI_CACHE_PROPERTY_ENABLED = 0x00000001,
212  AMDSMI_CACHE_PROPERTY_DATA_CACHE = 0x00000002,
213  AMDSMI_CACHE_PROPERTY_INST_CACHE = 0x00000004,
214  AMDSMI_CACHE_PROPERTY_CPU_CACHE = 0x00000008,
215  AMDSMI_CACHE_PROPERTY_SIMD_CACHE = 0x00000010,
217 
218 typedef enum {
219  AMDSMI_FW_ID_SMU = 1,
220  AMDSMI_FW_ID_FIRST = AMDSMI_FW_ID_SMU,
221  AMDSMI_FW_ID_CP_CE,
222  AMDSMI_FW_ID_CP_PFP,
223  AMDSMI_FW_ID_CP_ME,
224  AMDSMI_FW_ID_CP_MEC_JT1,
225  AMDSMI_FW_ID_CP_MEC_JT2,
226  AMDSMI_FW_ID_CP_MEC1,
227  AMDSMI_FW_ID_CP_MEC2,
228  AMDSMI_FW_ID_RLC,
229  AMDSMI_FW_ID_SDMA0,
230  AMDSMI_FW_ID_SDMA1,
231  AMDSMI_FW_ID_SDMA2,
232  AMDSMI_FW_ID_SDMA3,
233  AMDSMI_FW_ID_SDMA4,
234  AMDSMI_FW_ID_SDMA5,
235  AMDSMI_FW_ID_SDMA6,
236  AMDSMI_FW_ID_SDMA7,
237  AMDSMI_FW_ID_VCN,
238  AMDSMI_FW_ID_UVD,
239  AMDSMI_FW_ID_VCE,
240  AMDSMI_FW_ID_ISP,
243  AMDSMI_FW_ID_RLC_RESTORE_LIST_GPM_MEM,
244  AMDSMI_FW_ID_RLC_RESTORE_LIST_SRM_MEM,
245  AMDSMI_FW_ID_RLC_RESTORE_LIST_CNTL,
246  AMDSMI_FW_ID_RLC_V,
247  AMDSMI_FW_ID_MMSCH,
248  AMDSMI_FW_ID_PSP_SYSDRV,
249  AMDSMI_FW_ID_PSP_SOSDRV,
250  AMDSMI_FW_ID_PSP_TOC,
251  AMDSMI_FW_ID_PSP_KEYDB,
252  AMDSMI_FW_ID_DFC,
253  AMDSMI_FW_ID_PSP_SPL,
254  AMDSMI_FW_ID_DRV_CAP,
255  AMDSMI_FW_ID_MC,
256  AMDSMI_FW_ID_PSP_BL,
257  AMDSMI_FW_ID_CP_PM4,
258  AMDSMI_FW_ID_RLC_P,
259  AMDSMI_FW_ID_SEC_POLICY_STAGE2,
260  AMDSMI_FW_ID_REG_ACCESS_WHITELIST,
261  AMDSMI_FW_ID_IMU_DRAM,
262  AMDSMI_FW_ID_IMU_IRAM,
263  AMDSMI_FW_ID_SDMA_TH0,
264  AMDSMI_FW_ID_SDMA_TH1,
265  AMDSMI_FW_ID_CP_MES,
266  AMDSMI_FW_ID_MES_STACK,
268  AMDSMI_FW_ID_MES_THREAD1_STACK,
270  AMDSMI_FW_ID_RLX6_DRAM_BOOT,
271  AMDSMI_FW_ID_RS64_ME,
272  AMDSMI_FW_ID_RS64_ME_P0_DATA,
273  AMDSMI_FW_ID_RS64_ME_P1_DATA,
274  AMDSMI_FW_ID_RS64_PFP,
275  AMDSMI_FW_ID_RS64_PFP_P0_DATA,
276  AMDSMI_FW_ID_RS64_PFP_P1_DATA,
277  AMDSMI_FW_ID_RS64_MEC,
278  AMDSMI_FW_ID_RS64_MEC_P0_DATA,
279  AMDSMI_FW_ID_RS64_MEC_P1_DATA,
280  AMDSMI_FW_ID_RS64_MEC_P2_DATA,
281  AMDSMI_FW_ID_RS64_MEC_P3_DATA,
282  AMDSMI_FW_ID_PPTABLE,
283  AMDSMI_FW_ID_PSP_SOC,
284  AMDSMI_FW_ID_PSP_DBG,
285  AMDSMI_FW_ID_PSP_INTF,
286  AMDSMI_FW_ID_RLX6_CORE1,
287  AMDSMI_FW_ID_RLX6_DRAM_BOOT_CORE1,
288  AMDSMI_FW_ID_RLCV_LX7,
289  AMDSMI_FW_ID_RLC_SAVE_RESTORE_LIST,
290  AMDSMI_FW_ID_ASD,
291  AMDSMI_FW_ID_TA_RAS,
292  AMDSMI_FW_ID_XGMI,
293  AMDSMI_FW_ID_RLC_SRLG,
294  AMDSMI_FW_ID_RLC_SRLS,
295  AMDSMI_FW_ID_SMC,
296  AMDSMI_FW_ID_DMCU,
297  AMDSMI_FW_ID_PSP_RAS,
298  AMDSMI_FW_ID_P2S_TABLE,
299  AMDSMI_FW_ID_PLDM_BUNDLE,
300  AMDSMI_FW_ID__MAX
302 
306 typedef enum {
307  AMDSMI_MM_UVD,
308  AMDSMI_MM_VCE,
309  AMDSMI_MM_VCN,
310  AMDSMI_MM__MAX
312 
316 typedef enum {
318  AMDSMI_CLK_TYPE_FIRST = AMDSMI_CLK_TYPE_SYS,
319  AMDSMI_CLK_TYPE_GFX = AMDSMI_CLK_TYPE_SYS,
323  AMDSMI_CLK_TYPE_SOC,
324  AMDSMI_CLK_TYPE_MEM,
325  AMDSMI_CLK_TYPE_PCIE,
326  AMDSMI_CLK_TYPE_VCLK0,
327  AMDSMI_CLK_TYPE_VCLK1,
328  AMDSMI_CLK_TYPE_DCLK0,
329  AMDSMI_CLK_TYPE_DCLK1,
330  AMDSMI_CLK_TYPE__MAX = AMDSMI_CLK_TYPE_DCLK1
336 typedef enum {
337  AMDSMI_TEMPERATURE_TYPE_EDGE,
338  AMDSMI_TEMPERATURE_TYPE_FIRST = AMDSMI_TEMPERATURE_TYPE_EDGE,
339  AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
340  AMDSMI_TEMPERATURE_TYPE_JUNCTION = AMDSMI_TEMPERATURE_TYPE_HOTSPOT,
341  AMDSMI_TEMPERATURE_TYPE_VRAM,
342  AMDSMI_TEMPERATURE_TYPE_HBM_0,
343  AMDSMI_TEMPERATURE_TYPE_HBM_1,
344  AMDSMI_TEMPERATURE_TYPE_HBM_2,
345  AMDSMI_TEMPERATURE_TYPE_HBM_3,
346  AMDSMI_TEMPERATURE_TYPE_PLX,
347  AMDSMI_TEMPERATURE_TYPE__MAX = AMDSMI_TEMPERATURE_TYPE_PLX
353 typedef enum {
355  AMDSMI_TEMP_FIRST = AMDSMI_TEMP_CURRENT,
387  AMDSMI_TEMP_LAST = AMDSMI_TEMP_SHUTDOWN
389 
390 
391 typedef enum {
392  AMDSMI_PROCESSOR_TYPE_UNKNOWN = 0,
393  AMDSMI_PROCESSOR_TYPE_AMD_GPU,
394  AMDSMI_PROCESSOR_TYPE_AMD_CPU,
395  AMDSMI_PROCESSOR_TYPE_NON_AMD_GPU,
396  AMDSMI_PROCESSOR_TYPE_NON_AMD_CPU,
397  AMDSMI_PROCESSOR_TYPE_AMD_CPU_CORE,
398  AMDSMI_PROCESSOR_TYPE_AMD_APU
399 } processor_type_t;
400 
401 typedef enum {
402  AMDSMI_EVENT_CATEGORY_NON_USED = 0,
403  AMDSMI_EVENT_CATEGORY_DRIVER = 1,
404  AMDSMI_EVENT_CATEGORY_RESET = 2,
405  AMDSMI_EVENT_CATEGORY_SCHED = 3,
406  AMDSMI_EVENT_CATEGORY_VBIOS = 4,
407  AMDSMI_EVENT_CATEGORY_ECC = 5,
408  AMDSMI_EVENT_CATEGORY_PP = 6,
409  AMDSMI_EVENT_CATEGORY_IOV = 7,
410  AMDSMI_EVENT_CATEGORY_VF = 8,
411  AMDSMI_EVENT_CATEGORY_FW = 9,
412  AMDSMI_EVENT_CATEGORY_GPU = 10,
413  AMDSMI_EVENT_CATEGORY_GUARD = 11,
414  AMDSMI_EVENT_CATEGORY_GPUMON = 12,
415  AMDSMI_EVENT_CATEGORY_MMSCH = 13,
416  AMDSMI_EVENT_CATEGORY_XGMI = 14,
417  AMDSMI_EVENT_CATEGORY__MAX
418 } amdsmi_event_category_t;
419 
423 typedef enum {
424  AMDSMI_EVENT_GPU_DEVICE_LOST = 0,
425  AMDSMI_EVENT_GPU_NOT_SUPPORTED,
426  AMDSMI_EVENT_GPU_RMA,
427  AMDSMI_EVENT_GPU_NOT_INITIALIZED,
428  AMDSMI_EVENT_GPU_MMSCH_ABNORMAL_STATE,
429  AMDSMI_EVENT_GPU_RLCV_ABNORMAL_STATE,
430  AMDSMI_EVENT_GPU_SDMA_ENGINE_BUSY,
431  AMDSMI_EVENT_GPU_RLC_ENGINE_BUSY,
432  AMDSMI_EVENT_GPU_GC_ENGINE_BUSY,
433  AMDSMI_EVENT_GPU__MAX
435 
436 typedef enum {
437  AMDSMI_EVENT_DRIVER_SPIN_LOCK_BUSY = 0,
438  AMDSMI_EVENT_DRIVER_ALLOC_SYSTEM_MEM_FAIL,
439  AMDSMI_EVENT_DRIVER_CREATE_GFX_WORKQUEUE_FAIL,
440  AMDSMI_EVENT_DRIVER_CREATE_MM_WORKQUEUE_FAIL,
441  AMDSMI_EVENT_DRIVER_BUFFER_OVERFLOW,
442 
443  AMDSMI_EVENT_DRIVER_DEV_INIT_FAIL,
444  AMDSMI_EVENT_DRIVER_CREATE_THREAD_FAIL,
445  AMDSMI_EVENT_DRIVER_NO_ACCESS_PCI_REGION,
446  AMDSMI_EVENT_DRIVER_MMIO_FAIL,
447  AMDSMI_EVENT_DRIVER_INTERRUPT_INIT_FAIL,
448 
449  AMDSMI_EVENT_DRIVER_INVALID_VALUE,
450  AMDSMI_EVENT_DRIVER_CREATE_MUTEX_FAIL,
451  AMDSMI_EVENT_DRIVER_CREATE_TIMER_FAIL,
452  AMDSMI_EVENT_DRIVER_CREATE_EVENT_FAIL,
453  AMDSMI_EVENT_DRIVER_CREATE_SPIN_LOCK_FAIL,
454 
455  AMDSMI_EVENT_DRIVER_ALLOC_FB_MEM_FAIL,
456  AMDSMI_EVENT_DRIVER_ALLOC_DMA_MEM_FAIL,
457  AMDSMI_EVENT_DRIVER_NO_FB_MANAGER,
458  AMDSMI_EVENT_DRIVER_HW_INIT_FAIL,
459  AMDSMI_EVENT_DRIVER_SW_INIT_FAIL,
460 
461  AMDSMI_EVENT_DRIVER_INIT_CONFIG_ERROR,
462  AMDSMI_EVENT_DRIVER_ERROR_LOGGING_FAILED,
463  AMDSMI_EVENT_DRIVER_CREATE_RWLOCK_FAIL,
464  AMDSMI_EVENT_DRIVER_CREATE_RWSEMA_FAIL,
465  AMDSMI_EVENT_DRIVER_GET_READ_LOCK_FAIL,
466 
467  AMDSMI_EVENT_DRIVER_GET_WRITE_LOCK_FAIL,
468  AMDSMI_EVENT_DRIVER_GET_READ_SEMA_FAIL,
469  AMDSMI_EVENT_DRIVER_GET_WRITE_SEMA_FAIL,
470 
471  AMDSMI_EVENT_DRIVER_DIAG_DATA_INIT_FAIL,
472  AMDSMI_EVENT_DRIVER_DIAG_DATA_MEM_REQ_FAIL,
473  AMDSMI_EVENT_DRIVER_DIAG_DATA_VADDR_REQ_FAIL,
474  AMDSMI_EVENT_DRIVER_DIAG_DATA_BUS_ADDR_REQ_FAIL,
475 
476  AMDSMI_EVENT_DRIVER_HRTIMER_START_FAIL,
477  AMDSMI_EVENT_DRIVER_CREATE_DRIVER_FILE_FAIL,
478  AMDSMI_EVENT_DRIVER_CREATE_DEVICE_FILE_FAIL,
479  AMDSMI_EVENT_DRIVER_CREATE_DEBUGFS_FILE_FAIL,
480  AMDSMI_EVENT_DRIVER_CREATE_DEBUGFS_DIR_FAIL,
481 
482  AMDSMI_EVENT_DRIVER_PCI_ENABLE_DEVICE_FAIL,
483  AMDSMI_EVENT_DRIVER_FB_MAP_FAIL,
484  AMDSMI_EVENT_DRIVER_DOORBELL_MAP_FAIL,
485  AMDSMI_EVENT_DRIVER_PCI_REGISTER_DRIVER_FAIL,
486 
487  AMDSMI_EVENT_DRIVER_ALLOC_IOVA_ALIGN_FAIL,
488 
489  AMDSMI_EVENT_DRIVER_ROM_MAP_FAIL,
490  AMDSMI_EVENT_DRIVER_FULL_ACCESS_TIMEOUT,
491 
492  AMDSMI_EVENT_DRIVER__MAX
493 } amdsmi_event_driver_t;
494 
495 typedef enum {
496  AMDSMI_EVENT_FW_CMD_ALLOC_BUF_FAIL = 0,
497  AMDSMI_EVENT_FW_CMD_BUF_PREP_FAIL,
498  AMDSMI_EVENT_FW_RING_INIT_FAIL,
499  AMDSMI_EVENT_FW_FW_APPLY_SECURITY_POLICY_FAIL,
500  AMDSMI_EVENT_FW_START_RING_FAIL,
501 
502  AMDSMI_EVENT_FW_FW_LOAD_FAIL,
503  AMDSMI_EVENT_FW_EXIT_FAIL,
504  AMDSMI_EVENT_FW_INIT_FAIL,
505  AMDSMI_EVENT_FW_CMD_SUBMIT_FAIL,
506  AMDSMI_EVENT_FW_CMD_FENCE_WAIT_FAIL,
507 
508  AMDSMI_EVENT_FW_TMR_LOAD_FAIL,
509  AMDSMI_EVENT_FW_TOC_LOAD_FAIL,
510  AMDSMI_EVENT_FW_RAS_LOAD_FAIL,
511  AMDSMI_EVENT_FW_RAS_UNLOAD_FAIL,
512  AMDSMI_EVENT_FW_RAS_TA_INVOKE_FAIL,
513  AMDSMI_EVENT_FW_RAS_TA_ERR_INJECT_FAIL,
514 
515  AMDSMI_EVENT_FW_ASD_LOAD_FAIL,
516  AMDSMI_EVENT_FW_ASD_UNLOAD_FAIL,
517  AMDSMI_EVENT_FW_AUTOLOAD_FAIL,
518  AMDSMI_EVENT_FW_VFGATE_FAIL,
519 
520  AMDSMI_EVENT_FW_XGMI_LOAD_FAIL,
521  AMDSMI_EVENT_FW_XGMI_UNLOAD_FAIL,
522  AMDSMI_EVENT_FW_XGMI_TA_INVOKE_FAIL,
523 
524  AMDSMI_EVENT_FW_TMR_INIT_FAIL,
525  AMDSMI_EVENT_FW_NOT_SUPPORTED_FEATURE,
526  AMDSMI_EVENT_FW_GET_PSP_TRACELOG_FAIL,
527 
528  AMDSMI_EVENT_FW_SET_SNAPSHOT_ADDR_FAIL,
529  AMDSMI_EVENT_FW_SNAPSHOT_TRIGGER_FAIL,
530 
531  AMDSMI_EVENT_FW_MIGRATION_GET_PSP_INFO_FAIL,
532  AMDSMI_EVENT_FW_MIGRATION_EXPORT_FAIL,
533  AMDSMI_EVENT_FW_MIGRATION_IMPORT_FAIL,
534 
535  AMDSMI_EVENT_FW_BL_FAIL,
536  AMDSMI_EVENT_FW_RAS_BOOT_FAIL,
537  AMDSMI_EVENT_FW_MAILBOX_ERROR,
538 
539  AMDSMI_EVENT_FW__MAX
540 } amdsmi_event_fw_t;
541 
542 #define AMDSMI_EVENT_FW_FW_INIT_FAIL AMDSMI_EVENT_FW_RING_INIT_FAIL
543 
544 typedef enum {
545  AMDSMI_EVENT_RESET_GPU = 0,
546  AMDSMI_EVENT_RESET_GPU_FAILED,
547  AMDSMI_EVENT_RESET_FLR,
548  AMDSMI_EVENT_RESET_FLR_FAILED,
549  AMDSMI_EVENT_RESET__MAX
550 } amdsmi_event_reset_t;
551 
552 typedef enum {
553  AMDSMI_EVENT_IOV_NO_GPU_IOV_CAP = 0,
554  AMDSMI_EVENT_IOV_ASIC_NO_SRIOV_SUPPORT,
555  AMDSMI_EVENT_IOV_ENABLE_SRIOV_FAIL,
556  AMDSMI_EVENT_IOV_CMD_TIMEOUT,
557  AMDSMI_EVENT_IOV_CMD_ERROR,
558 
559  AMDSMI_EVENT_IOV_INIT_IV_RING_FAIL,
560  AMDSMI_EVENT_IOV_SRIOV_STRIDE_ERROR,
561  AMDSMI_EVENT_IOV_WS_SAVE_TIMEOUT,
562  AMDSMI_EVENT_IOV_WS_IDLE_TIMEOUT,
563  AMDSMI_EVENT_IOV_WS_RUN_TIMEOUT,
564  AMDSMI_EVENT_IOV_WS_LOAD_TIMEOUT,
565  AMDSMI_EVENT_IOV_WS_SHUTDOWN_TIMEOUT,
566  AMDSMI_EVENT_IOV_WS_ALREADY_SHUTDOWN,
567  AMDSMI_EVENT_IOV_WS_INFINITE_LOOP,
568  AMDSMI_EVENT_IOV_WS_REENTRANT_ERROR,
569  AMDSMI_EVENT_IOV__MAX
570 } amdsmi_event_iov_t;
571 
572 typedef enum {
573  AMDSMI_EVENT_ECC_UCE = 0,
574  AMDSMI_EVENT_ECC_CE,
575  AMDSMI_EVENT_ECC_IN_PF_FB,
576  AMDSMI_EVENT_ECC_IN_CRI_REG,
577  AMDSMI_EVENT_ECC_IN_VF_CRI,
578  AMDSMI_EVENT_ECC_REACH_THD,
579  AMDSMI_EVENT_ECC_VF_CE,
580  AMDSMI_EVENT_ECC_VF_UE,
581  AMDSMI_EVENT_ECC_IN_SAME_ROW,
582  AMDSMI_EVENT_ECC_UMC_UE,
583  AMDSMI_EVENT_ECC_GFX_CE,
584  AMDSMI_EVENT_ECC_GFX_UE,
585  AMDSMI_EVENT_ECC_SDMA_CE,
586  AMDSMI_EVENT_ECC_SDMA_UE,
587  AMDSMI_EVENT_ECC_GFX_CE_TOTAL,
588  AMDSMI_EVENT_ECC_GFX_UE_TOTAL,
589  AMDSMI_EVENT_ECC_SDMA_CE_TOTAL,
590  AMDSMI_EVENT_ECC_SDMA_UE_TOTAL,
591  AMDSMI_EVENT_ECC_UMC_CE_TOTAL,
592  AMDSMI_EVENT_ECC_UMC_UE_TOTAL,
593  AMDSMI_EVENT_ECC_MMHUB_CE,
594  AMDSMI_EVENT_ECC_MMHUB_UE,
595  AMDSMI_EVENT_ECC_MMHUB_CE_TOTAL,
596  AMDSMI_EVENT_ECC_MMHUB_UE_TOTAL,
597  AMDSMI_EVENT_ECC_XGMI_WAFL_CE,
598  AMDSMI_EVENT_ECC_XGMI_WAFL_UE,
599  AMDSMI_EVENT_ECC_XGMI_WAFL_CE_TOTAL,
600  AMDSMI_EVENT_ECC_XGMI_WAFL_UE_TOTAL,
601  AMDSMI_EVENT_ECC_FATAL_ERROR,
602  AMDSMI_EVENT_ECC_POISON_CONSUMPTION,
603  AMDSMI_EVENT_ECC_ACA_DUMP,
604  AMDSMI_EVENT_ECC_WRONG_SOCKET_ID,
605  AMDSMI_EVENT_ECC_ACA_UNKNOWN_BLOCK_INSTANCE,
606  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_CE,
607  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_UE,
608  AMDSMI_EVENT_ECC_UMC_CHIPLET_CE,
609  AMDSMI_EVENT_ECC_UMC_CHIPLET_UE,
610  AMDSMI_EVENT_ECC_GFX_CHIPLET_CE,
611  AMDSMI_EVENT_ECC_GFX_CHIPLET_UE,
612  AMDSMI_EVENT_ECC_SDMA_CHIPLET_CE,
613  AMDSMI_EVENT_ECC_SDMA_CHIPLET_UE,
614  AMDSMI_EVENT_ECC_MMHUB_CHIPLET_CE,
615  AMDSMI_EVENT_ECC_MMHUB_CHIPLET_UE,
616  AMDSMI_EVENT_ECC_XGMI_WAFL_CHIPLET_CE,
617  AMDSMI_EVENT_ECC_XGMI_WAFL_CHIPLET_UE,
618  AMDSMI_EVENT_ECC_EEPROM_ENTRIES_FOUND,
619  AMDSMI_EVENT_ECC_UMC_DE,
620  AMDSMI_EVENT_ECC_UMC_DE_TOTAL,
621  AMDSMI_EVENT_ECC_UNKNOWN,
622  AMDSMI_EVENT_ECC_EEPROM_REACH_THD,
623  AMDSMI_EVENT_ECC_UMC_CHIPLET_DE,
624  AMDSMI_EVENT_ECC_UNKNOWN_CHIPLET_DE,
625  AMDSMI_EVENT_ECC_EEPROM_CHK_MISMATCH,
626  AMDSMI_EVENT_ECC_EEPROM_RESET,
627  AMDSMI_EVENT_ECC_EEPROM_RESET_FAILED,
628  AMDSMI_EVENT_ECC_EEPROM_APPEND,
629  AMDSMI_EVENT_ECC_THD_CHANGED,
630  AMDSMI_EVENT_ECC_DUP_ENTRIES,
631  AMDSMI_EVENT_ECC_EEPROM_WRONG_HDR,
632  AMDSMI_EVENT_ECC_EEPROM_WRONG_VER,
633 
634  AMDSMI_EVENT_ECC__MAX
635 } amdsmi_event_ecc_t;
636 
637 typedef enum {
638  AMDSMI_EVENT_PP_SET_DPM_POLICY_FAIL = 0,
639  AMDSMI_EVENT_PP_ACTIVATE_DPM_POLICY_FAIL,
640  AMDSMI_EVENT_PP_I2C_SLAVE_NOT_PRESENT,
641  AMDSMI_EVENT_PP_THROTTLER_EVENT,
642  AMDSMI_EVENT_PP__MAX
643 } amdsmi_event_pp_t;
644 
645 typedef enum {
646  AMDSMI_EVENT_SCHED_WORLD_SWITCH_FAIL = 0,
647  AMDSMI_EVENT_SCHED_DISABLE_AUTO_HW_SWITCH_FAIL,
648  AMDSMI_EVENT_SCHED_ENABLE_AUTO_HW_SWITCH_FAIL,
649  AMDSMI_EVENT_SCHED_GFX_SAVE_REG_FAIL,
650  AMDSMI_EVENT_SCHED_GFX_IDLE_REG_FAIL,
651 
652  AMDSMI_EVENT_SCHED_GFX_RUN_REG_FAIL,
653  AMDSMI_EVENT_SCHED_GFX_LOAD_REG_FAIL,
654  AMDSMI_EVENT_SCHED_GFX_INIT_REG_FAIL,
655  AMDSMI_EVENT_SCHED_MM_SAVE_REG_FAIL,
656  AMDSMI_EVENT_SCHED_MM_IDLE_REG_FAIL,
657 
658  AMDSMI_EVENT_SCHED_MM_RUN_REG_FAIL,
659  AMDSMI_EVENT_SCHED_MM_LOAD_REG_FAIL,
660  AMDSMI_EVENT_SCHED_MM_INIT_REG_FAIL,
661  AMDSMI_EVENT_SCHED_INIT_GPU_FAIL,
662  AMDSMI_EVENT_SCHED_RUN_GPU_FAIL,
663 
664  AMDSMI_EVENT_SCHED_SAVE_GPU_STATE_FAIL,
665  AMDSMI_EVENT_SCHED_LOAD_GPU_STATE_FAIL,
666  AMDSMI_EVENT_SCHED_IDLE_GPU_FAIL,
667  AMDSMI_EVENT_SCHED_FINI_GPU_FAIL,
668  AMDSMI_EVENT_SCHED_DEAD_VF,
669 
670  AMDSMI_EVENT_SCHED_EVENT_QUEUE_FULL,
671  AMDSMI_EVENT_SCHED_SHUTDOWN_VF_FAIL,
672  AMDSMI_EVENT_SCHED_RESET_VF_NUM_FAIL,
673  AMDSMI_EVENT_SCHED_IGNORE_EVENT,
674  AMDSMI_EVENT_SCHED_PF_SWITCH_FAIL,
675  AMDSMI_EVENT_SCHED__MAX
676 } amdsmi_event_sched_t;
677 
678 typedef enum {
679  AMDSMI_EVENT_VF_ATOMBIOS_INIT_FAIL = 0,
680  AMDSMI_EVENT_VF_NO_VBIOS,
681  AMDSMI_EVENT_VF_GPU_POST_ERROR,
682  AMDSMI_EVENT_VF_ATOMBIOS_GET_CLOCK_FAIL,
683  AMDSMI_EVENT_VF_FENCE_INIT_FAIL,
684  AMDSMI_EVENT_VF_AMDGPU_INIT_FAIL,
685  AMDSMI_EVENT_VF_IB_INIT_FAIL,
686  AMDSMI_EVENT_VF_AMDGPU_LATE_INIT_FAIL,
687  AMDSMI_EVENT_VF_ASIC_RESUME_FAIL,
688  AMDSMI_EVENT_VF_GPU_RESET_FAIL,
689  AMDSMI_EVENT_VF__MAX
690 } amdsmi_event_vf_max_t;
691 
692 typedef enum {
693  AMDSMI_EVENT_VBIOS_INVALID = 0,
694  AMDSMI_EVENT_VBIOS_IMAGE_MISSING,
695  AMDSMI_EVENT_VBIOS_CHECKSUM_ERR,
696  AMDSMI_EVENT_VBIOS_POST_FAIL,
697  AMDSMI_EVENT_VBIOS_READ_FAIL,
698 
699  AMDSMI_EVENT_VBIOS_READ_IMG_HEADER_FAIL,
700  AMDSMI_EVENT_VBIOS_READ_IMG_SIZE_FAIL,
701  AMDSMI_EVENT_VBIOS_GET_FW_INFO_FAIL,
702  AMDSMI_EVENT_VBIOS_GET_TBL_REVISION_FAIL,
703  AMDSMI_EVENT_VBIOS_PARSER_TBL_FAIL,
704 
705  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_FAIL,
706  AMDSMI_EVENT_VBIOS_TIMEOUT,
707  AMDSMI_EVENT_VBIOS_HASH_INVALID,
708  AMDSMI_EVENT_VBIOS_HASH_UPDATED,
709  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_BINARY_CHECKSUM_FAIL,
710  AMDSMI_EVENT_VBIOS_IP_DISCOVERY_TABLE_CHECKSUM_FAIL,
711  AMDSMI_EVENT_VBIOS__MAX
712 } amdsmi_event_vbios_t;
713 
714 typedef enum {
715  AMDSMI_EVENT_GUARD_RESET_FAIL = 0,
716  AMDSMI_EVENT_GUARD_EVENT_OVERFLOW,
717  AMDSMI_EVENT_GUARD__MAX
718 } amdsmi_event_guard_t;
719 
720 typedef enum {
721  AMDSMI_EVENT_GPUMON_INVALID_OPTION = 0,
722  AMDSMI_EVENT_GPUMON_INVALID_VF_INDEX,
723  AMDSMI_EVENT_GPUMON_INVALID_FB_SIZE,
724  AMDSMI_EVENT_GPUMON_NO_SUITABLE_SPACE,
725  AMDSMI_EVENT_GPUMON_NO_AVAILABLE_SLOT,
726 
727  AMDSMI_EVENT_GPUMON_OVERSIZE_ALLOCATION,
728  AMDSMI_EVENT_GPUMON_OVERLAPPING_FB,
729  AMDSMI_EVENT_GPUMON_INVALID_GFX_TIMESLICE,
730  AMDSMI_EVENT_GPUMON_INVALID_MM_TIMESLICE,
731  AMDSMI_EVENT_GPUMON_INVALID_GFX_PART,
732 
733  AMDSMI_EVENT_GPUMON_VF_BUSY,
734  AMDSMI_EVENT_GPUMON_INVALID_VF_NUM,
735  AMDSMI_EVENT_GPUMON_NOT_SUPPORTED,
736  AMDSMI_EVENT_GPUMON__MAX
737 } amdsmi_event_gpumon_t;
738 
739 typedef enum {
740  AMDSMI_EVENT_MMSCH_IGNORED_JOB = 0,
741  AMDSMI_EVENT_MMSCH_UNSUPPORTED_VCN_FW,
742  AMDSMI_EVENT_MMSCH__MAX
743 } amdsmi_event_mmsch_t;
744 
745 typedef enum {
746  AMDSMI_EVENT_XGMI_TOPOLOGY_UPDATE_FAILED = 0,
747  AMDSMI_EVENT_XGMI_TOPOLOGY_HW_INIT_UPDATE,
748  AMDSMI_EVENT_XGMI_TOPOLOGY_UPDATE_DONE,
749  AMDSMI_EVENT_XGMI_FB_SHARING_SETTING_ERROR,
750  AMDSMI_EVENT_XGMI_FB_SHARING_SETTING_RESET,
751  AMDSMI_EVENT_XGMI__MAX
752 } amdsmi_event_xgmi_t;
753 
757 typedef enum {
758  AMDSMI_RAS_ECC_SUPPORT_PARITY = (1 << 0),
759  AMDSMI_RAS_ECC_SUPPORT_CORRECTABLE = (1 << 1),
760  AMDSMI_RAS_ECC_SUPPORT_UNCORRECTABLE = (1 << 2),
761  AMDSMI_RAS_ECC_SUPPORT_POISON = (1 << 3)
763 
768 typedef enum {
769  AMDSMI_GUEST_FW_ID_VCE = 0,
770  AMDSMI_GUEST_FW_ID_UVD,
771  AMDSMI_GUEST_FW_ID_MC,
772  AMDSMI_GUEST_FW_ID_ME,
773  AMDSMI_GUEST_FW_ID_PFP,
774  AMDSMI_GUEST_FW_ID_CE,
775  AMDSMI_GUEST_FW_ID_RLC,
776  AMDSMI_GUEST_FW_ID_RLC_SRLC,
777  AMDSMI_GUEST_FW_ID_RLC_SRLG,
778  AMDSMI_GUEST_FW_ID_RLC_SRLS,
779  AMDSMI_GUEST_FW_ID_MEC,
780  AMDSMI_GUEST_FW_ID_MEC2,
781  AMDSMI_GUEST_FW_ID_SOS,
782  AMDSMI_GUEST_FW_ID_ASD,
783  AMDSMI_GUEST_FW_ID_TA_RAS,
784  AMDSMI_GUEST_FW_ID_TA_XGMI,
785  AMDSMI_GUEST_FW_ID_SMC,
786  AMDSMI_GUEST_FW_ID_SDMA,
787  AMDSMI_GUEST_FW_ID_SDMA2,
788  AMDSMI_GUEST_FW_ID_VCN,
789  AMDSMI_GUEST_FW_ID_DMCU,
790  AMDSMI_GUEST_FW_ID__MAX
792 
793 typedef enum {
794  AMDSMI_VF_CONFIG_FB_SIZE_SET = 0,
795  AMDSMI_VF_CONFIG_FB_OFFSET_SET,
796  AMDSMI_VF_CONFIG_GFX_TIMESLICE_US_SET,
797  AMDSMI_VF_CONFIG_ENG_COMPUTE_BW_SET,
798  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_FLR_SET,
799  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_EXCL_MOD_SET,
800  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_EXCL_TIMEOUT_SET,
801  AMDSMI_VF_CONFIG_GUARD_THRESHOLD_ALL_INT_SET,
802  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_UVD_SET,
803  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCE_SET,
804  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_UVD1_SET,
805  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCN_SET,
806  AMDSMI_VF_CONFIG_ENG_ENCODE_BW_VCN1_SET,
807  AMDSMI_VF_CONFIG__MAX
808 } amdsmi_vf_config_flags_t;
809 
810 typedef enum {
811  AMDSMI_VF_STATE_UNAVAILABLE,
812  AMDSMI_VF_STATE_AVAILABLE,
813  AMDSMI_VF_STATE_ACTIVE,
814  AMDSMI_VF_STATE_SUSPENDED,
815  AMDSMI_VF_STATE_FULLACCESS,
816  AMDSMI_VF_STATE_DEFAULT_AVAILABLE
817 } amdsmi_vf_sched_state_t;
818 
819 typedef enum {
820  AMDSMI_GUARD_EVENT_FLR,
821  AMDSMI_GUARD_EVENT_EXCLUSIVE_MOD,
822  AMDSMI_GUARD_EVENT_EXCLUSIVE_TIMEOUT,
823  AMDSMI_GUARD_EVENT_ALL_INT,
824  AMDSMI_GUARD_EVENT__MAX
825 } amdsmi_guard_type_t;
826 
827 typedef enum {
828  AMDSMI_DRIVER_LIBGV,
829  AMDSMI_DRIVER_KMD,
830  AMDSMI_DRIVER_AMDGPUV,
831  AMDSMI_DRIVER_AMDGPU,
832  AMDSMI_DRIVER_VMWGPUV,
833  AMDSMI_DRIVER__MAX
834 } amdsmi_driver_t;
835 
836 typedef enum {
837  AMDSMI_GUARD_STATE_NORMAL = 0,
838  AMDSMI_GUARD_STATE_FULL = 1,
839  AMDSMI_GUARD_STATE_OVERFLOW = 2,
840 } amdsmi_guard_state_t;
841 
842 typedef enum {
843  AMDSMI_SCHED_BLOCK_GFX = 0x0,
844  AMDSMI_SCHED_BLOCK_UVD = 0x1,
845  AMDSMI_SCHED_BLOCK_VCE = 0x2,
846  AMDSMI_SCHED_BLOCK_UVD1 = 0x3,
847  AMDSMI_SCHED_BLOCK_VCN = 0x4,
848  AMDSMI_SCHED_BLOCK_VCN1 = 0x5,
849 } amdsmi_sched_block_t;
850 
851 typedef enum {
852  GUEST_FW_LOAD_STATUS_OK = 0,
853  GUEST_FW_LOAD_STATUS_OBSOLETE_FW = 1,
854  GUEST_FW_LOAD_STATUS_BAD_SIG = 2,
855  GUEST_FW_LOAD_STATUS_FW_LOAD_FAIL = 3,
856  GUEST_FW_LOAD_STATUS_ERR_GENERIC = 4
857 } amdsmi_guest_fw_load_status_t;
858 
859 
860 typedef enum {
861  AMDSMI_LINK_STATUS_ENABLED = 0,
862  AMDSMI_LINK_STATUS_DISABLED = 1,
863  AMDSMI_LINK_STATUS_ERROR = 2
864 } amdsmi_link_status_t;
865 
866 typedef enum {
867  AMDSMI_LINK_TYPE_INTERNAL,
868  AMDSMI_LINK_TYPE_XGMI,
869  AMDSMI_LINK_TYPE_PCIE,
870  AMDSMI_LINK_TYPE_NOT_APPLICABLE,
871  AMDSMI_LINK_TYPE_UNKNOWN
872 } amdsmi_link_type_t;
873 
874 typedef enum {
875  AMDSMI_XGMI_FB_SHARING_MODE_CUSTOM = 0,
876  AMDSMI_XGMI_FB_SHARING_MODE_1 = 1,
877  AMDSMI_XGMI_FB_SHARING_MODE_2 = 2,
878  AMDSMI_XGMI_FB_SHARING_MODE_4 = 4,
879  AMDSMI_XGMI_FB_SHARING_MODE_8 = 8,
880  AMDSMI_XGMI_FB_SHARING_MODE_UNKNOWN = 0xFFFFFFFF
881 } amdsmi_xgmi_fb_sharing_mode_t;
882 
883 typedef enum {
888  AMDSMI_PROFILE_CAPABILITY__MAX,
890 
891 typedef enum {
892  AMDSMI_VRAM_TYPE_UNKNOWN = 0,
893  // HBM
894  AMDSMI_VRAM_TYPE_HBM = 1,
895  AMDSMI_VRAM_TYPE_HBM2 = 2,
896  AMDSMI_VRAM_TYPE_HBM2E = 3,
897  AMDSMI_VRAM_TYPE_HBM3 = 4,
898  // DDR
899  AMDSMI_VRAM_TYPE_DDR2 = 10,
900  AMDSMI_VRAM_TYPE_DDR3 = 11,
901  AMDSMI_VRAM_TYPE_DDR4 = 12,
902  // GDDR
903  AMDSMI_VRAM_TYPE_GDDR1 = 17,
904  AMDSMI_VRAM_TYPE_GDDR2 = 18,
905  AMDSMI_VRAM_TYPE_GDDR3 = 19,
906  AMDSMI_VRAM_TYPE_GDDR4 = 20,
907  AMDSMI_VRAM_TYPE_GDDR5 = 21,
908  AMDSMI_VRAM_TYPE_GDDR6 = 22,
909  AMDSMI_VRAM_TYPE_GDDR7 = 23,
910 } amdsmi_vram_type_t;
911 
912 typedef enum {
913  AMDSMI_VRAM_VENDOR_SAMSUNG,
914  AMDSMI_VRAM_VENDOR_INFINEON,
915  AMDSMI_VRAM_VENDOR_ELPIDA,
916  AMDSMI_VRAM_VENDOR_ETRON,
917  AMDSMI_VRAM_VENDOR_NANYA,
918  AMDSMI_VRAM_VENDOR_HYNIX,
919  AMDSMI_VRAM_VENDOR_MOSEL,
920  AMDSMI_VRAM_VENDOR_WINBOND,
921  AMDSMI_VRAM_VENDOR_ESMT,
922  AMDSMI_VRAM_VENDOR_MICRON,
923  AMDSMI_VRAM_VENDOR_UNKNOWN
924 } amdsmi_vram_vendor_t;
925 
926 typedef enum {
929  AMDSMI_GPU_BLOCK_FIRST = (1 << 0),
930 
931  AMDSMI_GPU_BLOCK_UMC = AMDSMI_GPU_BLOCK_FIRST,
933  AMDSMI_GPU_BLOCK_GFX = (1 << 2),
937  AMDSMI_GPU_BLOCK_HDP = (1 << 6),
939  AMDSMI_GPU_BLOCK_DF = (1 << 8),
940  AMDSMI_GPU_BLOCK_SMN = (1 << 9),
941  AMDSMI_GPU_BLOCK_SEM = (1 << 10),
942  AMDSMI_GPU_BLOCK_MP0 = (1 << 11),
943  AMDSMI_GPU_BLOCK_MP1 = (1 << 12),
944  AMDSMI_GPU_BLOCK_FUSE = (1 << 13),
945  AMDSMI_GPU_BLOCK_MCA = (1 << 14),
946  AMDSMI_GPU_BLOCK_VCN = (1 << 15),
947  AMDSMI_GPU_BLOCK_JPEG = (1 << 16),
948  AMDSMI_GPU_BLOCK_IH = (1 << 17),
949  AMDSMI_GPU_BLOCK_MPIO = (1 << 18),
950  AMDSMI_GPU_BLOCK_LAST = AMDSMI_GPU_BLOCK_MPIO,
952 
953 typedef enum {
954  AMDSMI_CARD_FORM_FACTOR_PCIE,
955  AMDSMI_CARD_FORM_FACTOR_OAM,
956  AMDSMI_CARD_FORM_FACTOR_CEM,
957  AMDSMI_CARD_FORM_FACTOR_UNKNOWN
958 } amdsmi_card_form_factor_t;
959 
960 
961 typedef enum {
962  AMDSMI_METRIC_CATEGORY_ACC_COUNTER,
963  AMDSMI_METRIC_CATEGORY_FREQUENCY,
964  AMDSMI_METRIC_CATEGORY_ACTIVITY,
965  AMDSMI_METRIC_CATEGORY_TEMPERATURE,
966  AMDSMI_METRIC_CATEGORY_POWER,
967  AMDSMI_METRIC_CATEGORY_ENERGY,
968  AMDSMI_METRIC_CATEGORY_THROTTLE,
969  AMDSMI_METRIC_CATEGORY_PCIE,
970  AMDSMI_METRIC_CATEGORY_UNKNOWN
971 } amdsmi_metric_category_t;
972 
973 typedef enum {
974  AMDSMI_METRIC_NAME_METRIC_ACC_COUNTER,
975  AMDSMI_METRIC_NAME_FW_TIMESTAMP,
976  AMDSMI_METRIC_NAME_CLK_GFX,
977  AMDSMI_METRIC_NAME_CLK_SOC,
978  AMDSMI_METRIC_NAME_CLK_MEM,
979  AMDSMI_METRIC_NAME_CLK_VCLK,
980  AMDSMI_METRIC_NAME_CLK_DCLK,
981 
982  AMDSMI_METRIC_NAME_USAGE_GFX,
983  AMDSMI_METRIC_NAME_USAGE_MEM,
984  AMDSMI_METRIC_NAME_USAGE_MM,
985  AMDSMI_METRIC_NAME_USAGE_VCN,
986  AMDSMI_METRIC_NAME_USAGE_JPEG,
987 
988  AMDSMI_METRIC_NAME_VOLT_GFX,
989  AMDSMI_METRIC_NAME_VOLT_SOC,
990  AMDSMI_METRIC_NAME_VOLT_MEM,
991 
992  AMDSMI_METRIC_NAME_TEMP_HOTSPOT_CURR,
993  AMDSMI_METRIC_NAME_TEMP_HOTSPOT_LIMIT,
994  AMDSMI_METRIC_NAME_TEMP_MEM_CURR,
995  AMDSMI_METRIC_NAME_TEMP_MEM_LIMIT,
996  AMDSMI_METRIC_NAME_TEMP_VR_CURR,
997  AMDSMI_METRIC_NAME_TEMP_SHUTDOWN,
998 
999  AMDSMI_METRIC_NAME_POWER_CURR,
1000  AMDSMI_METRIC_NAME_POWER_LIMIT,
1001 
1002  AMDSMI_METRIC_NAME_ENERGY_SOCKET,
1003  AMDSMI_METRIC_NAME_ENERGY_CCD,
1004  AMDSMI_METRIC_NAME_ENERGY_XCD,
1005  AMDSMI_METRIC_NAME_ENERGY_AID,
1006  AMDSMI_METRIC_NAME_ENERGY_MEM,
1007 
1008  AMDSMI_METRIC_NAME_THROTTLE_SOCKET_ACTIVE,
1009  AMDSMI_METRIC_NAME_THROTTLE_VR_ACTIVE,
1010  AMDSMI_METRIC_NAME_THROTTLE_MEM_ACTIVE,
1011 
1012  AMDSMI_METRIC_NAME_PCIE_BANDWIDTH,
1013  AMDSMI_METRIC_NAME_PCIE_L0_TO_RECOVERY_COUNT,
1014  AMDSMI_METRIC_NAME_PCIE_REPLAY_COUNT,
1015  AMDSMI_METRIC_NAME_PCIE_REPLAY_ROLLOVER_COUNT,
1016  AMDSMI_METRIC_NAME_PCIE_NAK_SENT_COUNT,
1017  AMDSMI_METRIC_NAME_PCIE_NAK_RECEIVED_COUNT,
1018 
1019  AMDSMI_METRIC_NAME_CLK_GFX_MAX_LIMIT,
1020  AMDSMI_METRIC_NAME_CLK_SOC_MAX_LIMIT,
1021  AMDSMI_METRIC_NAME_CLK_MEM_MAX_LIMIT,
1022  AMDSMI_METRIC_NAME_CLK_VCLK_MAX_LIMIT,
1023  AMDSMI_METRIC_NAME_CLK_DCLK_MAX_LIMIT,
1024 
1025  AMDSMI_METRIC_NAME_CLK_GFX_MIN_LIMIT,
1026  AMDSMI_METRIC_NAME_CLK_SOC_MIN_LIMIT,
1027  AMDSMI_METRIC_NAME_CLK_MEM_MIN_LIMIT,
1028  AMDSMI_METRIC_NAME_CLK_VCLK_MIN_LIMIT,
1029  AMDSMI_METRIC_NAME_CLK_DCLK_MIN_LIMIT,
1030 
1031  AMDSMI_METRIC_NAME_CLK_GFX_LOCKED,
1032 
1033  AMDSMI_METRIC_NAME_CLK_GFX_DS_DISABLED,
1034  AMDSMI_METRIC_NAME_CLK_MEM_DS_DISABLED,
1035  AMDSMI_METRIC_NAME_CLK_SOC_DS_DISABLED,
1036  AMDSMI_METRIC_NAME_CLK_VCLK_DS_DISABLED,
1037  AMDSMI_METRIC_NAME_CLK_DCLK_DS_DISABLED,
1038 
1039  AMDSMI_METRIC_NAME_PCIE_LINK_SPEED,
1040  AMDSMI_METRIC_NAME_PCIE_LINK_WIDTH,
1041 
1042  AMDSMI_METRIC_NAME_DRAM_BANDWIDTH,
1043  AMDSMI_METRIC_NAME_MAX_DRAM_BANDWIDTH,
1044 
1045  AMDSMI_METRIC_NAME_UNKNOWN
1046 } amdsmi_metric_name_t;
1047 
1048 typedef enum {
1049  AMDSMI_METRIC_UNIT_COUNTER,
1050  AMDSMI_METRIC_UNIT_UINT,
1051  AMDSMI_METRIC_UNIT_BOOL,
1052  AMDSMI_METRIC_UNIT_MHZ,
1053  AMDSMI_METRIC_UNIT_PERCENT,
1054  AMDSMI_METRIC_UNIT_MILLIVOLT,
1055  AMDSMI_METRIC_UNIT_CELSIUS,
1056  AMDSMI_METRIC_UNIT_WATT,
1057  AMDSMI_METRIC_UNIT_JOULE,
1058  AMDSMI_METRIC_UNIT_GBPS,
1059  AMDSMI_METRIC_UNIT_MBITPS,
1060  AMDSMI_METRIC_UNIT_PCIE_GEN,
1061  AMDSMI_METRIC_UNIT_PCIE_LANES,
1062  AMDSMI_METRIC_UNIT_UNKNOWN
1063 } amdsmi_metric_unit_t;
1064 
1065 typedef enum {
1069  AMDSMI_METRIC_TYPE_ACC = (1 << 3)
1071 
1076 typedef enum {
1077  AMDSMI_MEMORY_PARTITION_UNKNOWN = 0,
1092 
1093 typedef enum {
1094  AMDSMI_ACCELERATOR_PARTITION_INVALID = 0,
1105  AMDSMI_ACCELERATOR_PARTITION_MAX
1107 
1108 typedef enum {
1109  AMDSMI_ACCELERATOR_XCC,
1110  AMDSMI_ACCELERATOR_ENCODER,
1111  AMDSMI_ACCELERATOR_DECODER,
1112  AMDSMI_ACCELERATOR_DMA,
1113  AMDSMI_ACCELERATOR_JPEG,
1114  AMDSMI_ACCELERATOR_MAX
1115 } amdsmi_accelerator_partition_resource_type_t;
1116 
1117 typedef enum {
1118  AMDSMI_DRIVER_MODEL_TYPE_WDDM = 0,
1119  AMDSMI_DRIVER_MODEL_TYPE_WDM = 1,
1120  AMDSMI_DRIVER_MODEL_TYPE_MCDM = 2,
1121  AMDSMI_DRIVER_MODEL_TYPE__MAX = 3,
1122 } amdsmi_driver_model_type_t;
1123 
1124 typedef enum {
1125  AMDSMI_VIRTUALIZATION_MODE_UNKNOWN = 0,
1126  AMDSMI_VIRTUALIZATION_MODE_NONE,
1127  AMDSMI_VIRTUALIZATION_MODE_HOST,
1128 
1129  AMDSMI_VIRTUALIZATION_MODE_GUEST,
1130  AMDSMI_VIRTUALIZATION_MODE_PASSTHROUGH
1131 } amdsmi_virtualization_mode_t;
1132 
1137 typedef union {
1138  struct bdf_ {
1139  uint64_t function_number : 3;
1140  uint64_t device_number : 5;
1141  uint64_t bus_number : 8;
1142  uint64_t domain_number : 48;
1143  } bdf;
1144  uint64_t as_uint;
1145 } amdsmi_bdf_t;
1146 
1147 typedef struct {
1148  struct pcie_static_ {
1149  uint16_t max_pcie_width;
1150  uint32_t max_pcie_speed;
1152  amdsmi_card_form_factor_t slot_type;
1154  uint64_t reserved[9];
1155  } pcie_static;
1156  struct pcie_metric_ {
1157  uint16_t pcie_width;
1158  uint32_t pcie_speed;
1159  uint32_t pcie_bandwidth;
1166  uint64_t reserved[12];
1167  } pcie_metric;
1168  uint64_t reserved[32];
1170 
1171 
1172 typedef struct {
1173  uint64_t power_cap;
1174  uint64_t default_power_cap;
1175  uint64_t dpm_cap;
1176  uint64_t min_power_cap;
1177  uint64_t max_power_cap;
1178  uint64_t reserved[3];
1180 
1181 typedef struct {
1182  char name[AMDSMI_MAX_STRING_LENGTH];
1183  char build_date[AMDSMI_MAX_DATE_LENGTH];
1184  char part_number[AMDSMI_MAX_STRING_LENGTH];
1185  char version[AMDSMI_MAX_STRING_LENGTH];
1186  uint64_t reserved[68];
1188 
1189 typedef struct {
1190  uint32_t num_cache_types;
1191  struct cache_ {
1192  uint32_t cache_properties;
1193  uint32_t cache_size; /* In KB */
1194  uint32_t cache_level;
1195  uint32_t max_num_cu_shared; /* Indicates how many Compute Units share this cache instance */
1196  uint32_t num_cache_instance; /* total number of instance of this cache type */
1197  uint32_t reserved[3];
1198  } cache[AMDSMI_MAX_CACHE_TYPES];
1199  uint32_t reserved[15];
1201 
1202 typedef struct {
1203  uint8_t num_fw_info;
1204  struct {
1205  amdsmi_fw_block_t fw_id;
1206  uint64_t fw_version;
1207  uint64_t reserved[2];
1208  } fw_info_list[AMDSMI_FW_ID__MAX];
1209  uint64_t reserved[3];
1211 
1212 typedef struct {
1213  char market_name[AMDSMI_MAX_STRING_LENGTH];
1214  char vendor_name[AMDSMI_MAX_STRING_LENGTH];
1215  char asic_serial[AMDSMI_MAX_STRING_LENGTH];
1216  uint64_t reserved[64];
1217  uint32_t vendor_id;
1218  uint32_t subvendor_id;
1219  uint64_t device_id;
1220  uint32_t rev_id;
1221  uint32_t oam_id;
1222  uint32_t num_of_compute_units; //< 0xFFFFFFFF if not supported
1223  uint64_t target_graphics_version; //< 0xFFFFFFFFFFFFFFFF if not supported
1224  uint32_t subsystem_id;
1225  uint64_t reserved_2[10];
1227 
1228 typedef struct {
1229  char driver_version[AMDSMI_MAX_STRING_LENGTH];
1230  char driver_date[AMDSMI_MAX_DATE_LENGTH];
1231  char driver_name[AMDSMI_MAX_STRING_LENGTH];
1232  uint64_t reserved[68];
1234 
1235 typedef struct {
1236  uint64_t socket_power;
1237  uint64_t gfx_voltage;
1238  uint64_t soc_voltage;
1239  uint64_t mem_voltage;
1240  uint64_t reserved[4];
1242 
1243 typedef struct {
1244  uint32_t gfx_activity;
1245  uint32_t umc_activity;
1246  uint32_t mm_activity;
1247  uint64_t reserved[6];
1249 
1250 typedef struct {
1251  uint32_t clk;
1252  uint32_t min_clk;
1253  uint32_t max_clk;
1254  uint8_t clk_locked;
1255  uint8_t clk_deep_sleep;
1256  uint64_t reserved[2];
1258 
1259 typedef struct {
1262  uint64_t deferred_count;
1263  uint64_t reserved[5];
1265 
1266 typedef struct {
1267  uint32_t ras_eeprom_version;
1269  uint64_t reserved[3];
1271 
1272 typedef struct {
1273  uint64_t handle;
1275 
1276 typedef struct {
1277  amdsmi_vf_handle_t fcn_id;
1278  uint64_t dev_id;
1279  uint64_t timestamp;
1280  uint64_t data;
1281  uint32_t category;
1282  uint32_t subcode;
1283  uint32_t level;
1285  char message[AMDSMI_EVENT_MSG_SIZE];
1286  uint64_t reserved[6];
1288 
1289 typedef struct {
1290  char model_number[AMDSMI_MAX_STRING_LENGTH];
1291  char product_serial[AMDSMI_MAX_STRING_LENGTH];
1292  char fru_id[AMDSMI_MAX_STRING_LENGTH];
1293  char product_name[AMDSMI_MAX_STRING_LENGTH];
1294  char manufacturer_name[AMDSMI_MAX_STRING_LENGTH];
1295  uint64_t reserved[64];
1297 
1298 typedef struct {
1299  uint32_t total_fb_size;
1300  uint32_t pf_fb_reserved;
1301  uint32_t pf_fb_offset;
1302  uint32_t fb_alignment;
1303  uint32_t max_vf_fb_usable;
1304  uint32_t min_vf_fb_usable;
1305  uint64_t reserved[5];
1307 
1308 typedef struct {
1309  uint32_t fb_offset;
1310  uint32_t fb_size;
1311  uint64_t reserved[3];
1313 
1314 typedef struct {
1315  amdsmi_vf_handle_t id;
1317  uint64_t reserved[3];
1319 
1320 typedef struct {
1321  uint8_t enabled;
1322  struct {
1323  amdsmi_guard_state_t state;
1324  /* amount of monitor event after enabled */
1325  uint32_t amount;
1326  /* threshold of events in the interval(seconds) */
1327  uint64_t interval;
1328  uint32_t threshold;
1329  /* current number of events in the interval*/
1330  uint32_t active;
1331  uint32_t reserved[4];
1332  } guard[AMDSMI_GUARD_EVENT__MAX];
1333  uint32_t reserved[6];
1335 
1336 typedef struct {
1338  uint32_t gfx_timeslice;
1339  uint64_t reserved[27];
1341 
1342 typedef struct {
1343  uint64_t flr_count;
1344  uint64_t boot_up_time;
1345  uint64_t shutdown_time;
1346  uint64_t reset_time;
1347  amdsmi_vf_sched_state_t state;
1348  char last_boot_start[AMDSMI_MAX_DATE_LENGTH];
1349  char last_boot_end[AMDSMI_MAX_DATE_LENGTH];
1350  char last_shutdown_start[AMDSMI_MAX_DATE_LENGTH];
1351  char last_shutdown_end[AMDSMI_MAX_DATE_LENGTH];
1352  char last_reset_start[AMDSMI_MAX_DATE_LENGTH];
1353  char last_reset_end[AMDSMI_MAX_DATE_LENGTH];
1354  char current_active_time[AMDSMI_MAX_DATE_LENGTH];
1355  char current_running_time[AMDSMI_MAX_DATE_LENGTH];
1356  char total_active_time[AMDSMI_MAX_DATE_LENGTH];
1357  char total_running_time[AMDSMI_MAX_DATE_LENGTH];
1358  uint64_t reserved[11];
1360 
1361 typedef struct {
1362  amdsmi_sched_info_t sched;
1363  amdsmi_guard_info_t guard;
1364  uint64_t reserved[8];
1366 
1367 typedef struct {
1368  uint64_t total;
1369  uint64_t available;
1370  uint64_t optimal;
1371  uint64_t min_value;
1372  uint64_t max_value;
1373  uint64_t reserved[2];
1375 
1376 typedef struct {
1377  uint8_t profile_count;
1378  uint8_t current_profile_index;
1379  struct {
1380  uint32_t vf_count;
1381  amdsmi_profile_caps_info_t profile_caps[AMDSMI_PROFILE_CAPABILITY__MAX];
1382  } profiles[AMDSMI_MAX_PROFILE_COUNT];
1383  uint32_t reserved[6];
1385 
1386 typedef struct {
1387  char driver_version[AMDSMI_MAX_DRIVER_INFO_RSVD];
1388  uint32_t fb_usage;
1389  uint64_t reserved[23];
1391 
1392 typedef struct {
1393  uint32_t dfc_fw_version;
1394  uint32_t dfc_fw_total_entries;
1395  uint32_t dfc_gart_wr_guest_min;
1396  uint32_t dfc_gart_wr_guest_max;
1397  uint32_t reserved[12];
1399 
1400 typedef struct {
1401  uint32_t oldest;
1402  uint32_t latest;
1404 
1405 typedef struct {
1406  uint8_t ta_uuid[AMDSMI_MAX_UUID_ELEMENTS];
1408 
1409 typedef struct {
1410  uint32_t dfc_fw_type;
1411  uint32_t verification_enabled;
1412  uint32_t customer_ordinal;
1413  uint32_t reserved[13];
1414  union {
1415  amdsmi_dfc_fw_white_list_t white_list[AMDSMI_MAX_WHITE_LIST_ELEMENTS];
1416  amdsmi_dfc_fw_ta_uuid_t ta_white_list[AMDSMI_MAX_TA_WHITE_LIST_ELEMENTS];
1417  };
1418  uint32_t black_list[AMDSMI_MAX_BLACK_LIST_ELEMENTS];
1420 
1421 typedef struct {
1422  amdsmi_dfc_fw_header_t header;
1423  amdsmi_dfc_fw_data_t data[AMDSMI_DFC_FW_NUMBER_OF_ENTRIES];
1424 } amdsmi_dfc_fw_t;
1425 
1426 typedef struct {
1427  uint64_t retired_page;
1428  uint64_t ts;
1429  unsigned char err_type;
1430  union {
1431  unsigned char bank;
1432  unsigned char cu;
1433  };
1434  unsigned char mem_channel;
1435  unsigned char mcumc_id;
1436  uint32_t reserved[3];
1438 
1439 typedef struct {
1440  uint64_t timestamp;
1441  uint32_t vf_idx;
1442  uint32_t fw_id;
1443  uint16_t status;
1444  uint32_t reserved[3];
1446 
1447 typedef struct {
1448  uint8_t num_err_records;
1449  amdsmi_fw_load_error_record_t err_records[AMDSMI_MAX_ERR_RECORDS];
1450  uint64_t reserved[7];
1452 
1453 typedef struct {
1454  uint32_t num_links;
1455  struct links_ {
1456  amdsmi_bdf_t bdf;
1457  uint32_t bit_rate;
1458  uint32_t max_bandwidth;
1459  amdsmi_link_type_t link_type;
1460  uint64_t read;
1461  uint64_t write;
1462  uint64_t reserved[2];
1463  } links[AMDSMI_MAX_NUM_XGMI_PHYSICAL_LINK];
1464  uint64_t reserved[7];
1466 
1467 typedef struct {
1468  uint64_t weight;
1469  amdsmi_link_status_t link_status;
1470  amdsmi_link_type_t link_type;
1471  uint8_t num_hops;
1472  uint8_t fb_sharing;
1473  uint32_t reserved[10];
1475 
1476 typedef struct {
1477  uint32_t count;
1478  amdsmi_processor_handle processor_list[AMDSMI_MAX_DEVICES];
1479  uint64_t reserved[15];
1481 
1482 typedef union {
1483  struct cap_ {
1484  uint32_t mode_custom_cap :1;
1485  uint32_t mode_1_cap :1;
1486  uint32_t mode_2_cap :1;
1487  uint32_t mode_4_cap :1;
1488  uint32_t mode_8_cap :1;
1489  uint32_t reserved :27;
1490  } cap;
1491  uint32_t xgmi_fb_sharing_cap_mask;
1493 
1494 typedef struct {
1495  amdsmi_vram_type_t vram_type;
1496  amdsmi_vram_vendor_t vram_vendor;
1497  uint32_t vram_size;
1498  uint32_t vram_bit_width;
1499  uint64_t reserved[6];
1501 
1502 typedef struct {
1503  amdsmi_metric_unit_t unit;
1504  amdsmi_metric_name_t name;
1505  amdsmi_metric_category_t category;
1506  uint32_t flags;
1507  uint32_t vf_mask;
1508  uint64_t val;
1509  uint32_t reserved[8];
1510 } amdsmi_metric_t;
1511 
1515 typedef struct {
1516  uint32_t major;
1517  uint32_t minor;
1518  uint32_t release;
1520 
1524 typedef union {
1525  struct nps_flags_{
1526  uint32_t nps1_cap :1; // bool 1 = true; 0 = false;
1527  uint32_t nps2_cap :1; // bool 1 = true; 0 = false;
1528  uint32_t nps4_cap :1; // bool 1 = true; 0 = false;
1529  uint32_t nps8_cap :1; // bool 1 = true; 0 = false;
1530  uint32_t reserved :28; // bool 1 = true; 0 = false;
1531  } nps_flags;
1532  uint32_t nps_cap_mask;
1534 
1535 typedef struct {
1536  amdsmi_nps_caps_t partition_caps;
1538  uint32_t num_numa_ranges;
1539  struct numa_range_ {
1540  amdsmi_vram_type_t memory_type;
1541  uint64_t start;
1542  uint64_t end;
1543  } numa_range[AMDSMI_MAX_NUM_NUMA_NODES];
1544  uint64_t reserved[11];
1546 
1547 typedef struct {
1549  uint32_t num_partitions;
1551  uint32_t profile_index;
1552  uint32_t num_resources;
1553  uint32_t resources[AMDSMI_MAX_ACCELERATOR_PARTITIONS][AMDSMI_MAX_CP_PROFILE_RESOURCES];
1554  uint64_t reserved[13];
1556 
1557 typedef struct {
1558  uint32_t profile_index;
1559  amdsmi_accelerator_partition_resource_type_t resource_type;
1562  uint64_t reserved[6];
1564 
1565 typedef struct {
1566  uint32_t num_profiles;
1567  uint32_t num_resource_profiles;
1568  amdsmi_accelerator_partition_resource_profile_t resource_profiles[AMDSMI_MAX_CP_PROFILE_RESOURCES];
1570  amdsmi_accelerator_partition_profile_t profiles[AMDSMI_MAX_ACCELERATOR_PROFILE];
1571  uint64_t reserved[30];
1573 
1574 typedef struct {
1575  uint32_t policy_id;
1576  char policy_description[AMDSMI_MAX_NAME];
1577  uint64_t reserved[3];
1579 
1580 typedef struct {
1584  uint32_t num_supported;
1585 
1589  uint32_t cur;
1590 
1595  amdsmi_dpm_policy_entry_t policies[AMDSMI_MAX_NUM_PM_POLICIES];
1596  uint64_t reserved[7];
1598 
1599 #pragma pack(push, 1)
1600 
1601 typedef struct {
1602  unsigned char b[16];
1604 
1605 typedef enum {
1606  AMDSMI_CPER_SEV_NON_FATAL_UNCORRECTED = 0,
1607  AMDSMI_CPER_SEV_FATAL = 1,
1608  AMDSMI_CPER_SEV_NON_FATAL_CORRECTED = 2,
1609  AMDSMI_CPER_SEV_NUM = 3,
1610 
1611  AMDSMI_CPER_SEV_UNUSED = 10,
1612 } amdsmi_cper_sev_t;
1613 
1614 typedef struct {
1615  uint8_t seconds;
1616  uint8_t minutes;
1617  uint8_t hours;
1618  uint8_t flag;
1619  uint8_t day;
1620  uint8_t month;
1621  uint8_t year;
1622  uint8_t century;
1624 
1625 typedef union {
1626  struct valid_bits_ {
1627  uint32_t platform_id : 1;
1628  uint32_t timestamp : 1;
1629  uint32_t partition_id : 1;
1630  uint32_t reserved : 29;
1631  } valid_bits;
1632  uint32_t valid_mask;
1634 
1635 typedef struct {
1636  char signature[4]; /* "CPER" */
1637  uint16_t revision;
1638  uint32_t signature_end; /* 0xFFFFFFFF */
1639  uint16_t sec_cnt;
1640  amdsmi_cper_sev_t error_severity;
1641  amdsmi_cper_valid_bits_t cper_valid_bits;
1642  uint32_t record_length; /* Total size of CPER Entry */
1643  amdsmi_cper_timestamp_t timestamp;
1644  char platform_id[16];
1645  amdsmi_cper_guid_t partition_id; /* Reserved */
1646  char creator_id[16];
1647  amdsmi_cper_guid_t notify_type; /* CMC, MCE */
1648  char record_id[8]; /* Unique CPER Entry ID */
1649  uint32_t flags; /* Reserved */
1650  uint64_t persistence_info; /* Reserved */
1651  uint8_t reserved[12]; /* Reserved */
1653 
1654 typedef enum {
1655  AMDSMI_CPER_NOTIFY_TYPE_CMC = 0x450eBDD72DCE8BB1,
1656  AMDSMI_CPER_NOTIFY_TYPE_CPE = 0x4a55D8434E292F96,
1657  AMDSMI_CPER_NOTIFY_TYPE_MCE = 0x4cc5919CE8F56FFE,
1658  AMDSMI_CPER_NOTIFY_TYPE_PCIE = 0x4dfc1A16CF93C01F,
1659  AMDSMI_CPER_NOTIFY_TYPE_INIT = 0x454a9308CC5263E8,
1660  AMDSMI_CPER_NOTIFY_TYPE_NMI = 0x42c9B7E65BAD89FF,
1661  AMDSMI_CPER_NOTIFY_TYPE_BOOT = 0x409aAB403D61A466,
1662  AMDSMI_CPER_NOTIFY_TYPE_DMAR = 0x4c27C6B3667DD791,
1663  AMDSMI_CPER_NOTIFY_TYPE_SEA = 0x11E4BBE89A78788A,
1664  AMDSMI_CPER_NOTIFY_TYPE_SEI = 0x4E87B0AE5C284C81,
1665  AMDSMI_CPER_NOTIFY_TYPE_PEI = 0x4214520409A9D5AC,
1666  AMDSMI_CPER_NOTIFY_TYPE_CXL_COMPONENT = 0x49A341DF69293BC9,
1667 } amdsmi_cper_notify_type_t;
1668 
1669 #pragma pack(pop)
1670 
1671 typedef struct {
1673  uint8_t is_iolink_atomics_32bit;
1674  uint8_t is_iolink_atomics_64bit;
1675  uint8_t is_iolink_dma;
1676  uint8_t is_iolink_bi_directional;
1677  uint64_t reserved[3];
1679 
1680 /*****************************************************************************/
1703 amdsmi_status_t amdsmi_init(uint64_t init_flags);
1704 
1712  // end of init
1714 
1715 /*****************************************************************************/
1739 amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle, uint32_t *processor_count, amdsmi_processor_handle *processor_handles);
1740 
1756 amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle,
1757  processor_type_t *processor_type);
1758 
1772 amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count, amdsmi_socket_handle *socket_handles);
1773 
1787 amdsmi_status_t amdsmi_get_socket_info(amdsmi_socket_handle socket_handle, size_t len, char *name);
1788 
1799 amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_processor_handle *processor_handle);
1800 
1811 amdsmi_status_t amdsmi_get_index_from_processor_handle(amdsmi_processor_handle processor_handle, uint32_t *processor_index);
1812 
1824 
1834 amdsmi_status_t amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf);
1835 
1846 amdsmi_status_t amdsmi_get_processor_handle_from_index(uint32_t processor_index, amdsmi_processor_handle *processor_handle);
1847 
1858 
1870 amdsmi_status_t amdsmi_get_vf_handle_from_vf_index(amdsmi_processor_handle processor_handle, uint32_t fcn_idx, amdsmi_vf_handle_t *vf_handle);
1871 
1883 
1894 amdsmi_status_t amdsmi_get_processor_handle_from_uuid(const char *uuid, amdsmi_processor_handle *processor_handle);
1895 
1910 amdsmi_status_t amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid);
1911 
1926 amdsmi_status_t amdsmi_get_vf_uuid(amdsmi_vf_handle_t processor_handle, unsigned int *uuid_length, char *uuid);
1927 
1939  amdsmi_status_t amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle, amdsmi_virtualization_mode_t *mode); // end of discovery
1941 
1942 /*****************************************************************************/
1957 amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info);
1958 
1968 amdsmi_status_t amdsmi_get_gpu_driver_model(amdsmi_processor_handle processor_handle, amdsmi_driver_model_type_t *model);
1969 
1985 
1986 /*****************************************************************************/
2001 amdsmi_status_t amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info);
2002 
2013 amdsmi_status_t amdsmi_get_gpu_vram_info(amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info);
2014 
2030 amdsmi_status_t amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, amdsmi_power_cap_info_t *info);
2031 
2042 amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle, amdsmi_pcie_info_t *info);
2043 
2054 amdsmi_status_t amdsmi_get_fb_layout(amdsmi_processor_handle processor_handle, amdsmi_pf_fb_info_t *info);
2055  // end of asicinfo
2057 
2058 /*****************************************************************************/
2073 amdsmi_status_t amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info);
2074 
2085 amdsmi_status_t amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info);
2086 
2096 amdsmi_status_t amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info);
2097 
2108 amdsmi_status_t amdsmi_get_fw_error_records(amdsmi_processor_handle processor_handle, amdsmi_fw_error_record_t *records);
2109 
2119 amdsmi_status_t amdsmi_get_dfc_fw_table(amdsmi_processor_handle processor_handle, amdsmi_dfc_fw_t *info);
2120  // end of fwinfo
2122 
2123 /*****************************************************************************/
2138 amdsmi_status_t amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info);
2139 
2155 amdsmi_status_t amdsmi_get_power_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, amdsmi_power_info_t *info);
2156 
2176 amdsmi_status_t amdsmi_set_power_cap(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, uint64_t cap);
2177 
2187 amdsmi_status_t amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled);
2188 
2206 amdsmi_status_t amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info);
2207 
2225 amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle, amdsmi_temperature_type_t sensor_type,
2226  amdsmi_temperature_metric_t metric, int64_t *temperature);
2227 
2238 amdsmi_status_t amdsmi_get_gpu_cache_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info);
2239 
2254 amdsmi_status_t amdsmi_get_gpu_metrics(amdsmi_processor_handle processor_handle, uint32_t *metrics_size,
2255  amdsmi_metric_t *metrics);
2256 
2274 amdsmi_status_t amdsmi_get_soc_pstate(amdsmi_processor_handle processor_handle,
2275  amdsmi_dpm_policy_t *policy);
2276 
2294 amdsmi_status_t amdsmi_set_soc_pstate(amdsmi_processor_handle processor_handle,
2295  uint32_t policy_id);
2296  // end of gpumon
2298 
2299 /*****************************************************************************/
2315 amdsmi_status_t amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec);
2316 
2330 amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_gpu_block_t block, amdsmi_error_count_t *ec);
2331 
2341 amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle, uint64_t *enabled_blocks);
2342 
2357 amdsmi_status_t amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *bad_page_size,
2358  amdsmi_eeprom_table_record_t *bad_pages);
2359 
2370 amdsmi_status_t amdsmi_get_gpu_ras_feature_info(amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature);
2371 
2393 amdsmi_status_t amdsmi_get_bad_page_threshold(amdsmi_processor_handle processor_handle, uint32_t *threshold);
2394  // end of eccinfo
2396 
2397 /*****************************************************************************/
2416 amdsmi_get_num_vf(amdsmi_processor_handle processor_handle, uint32_t *num_vf_enabled, uint32_t *num_vf_supported);
2417 
2418 
2428 amdsmi_status_t amdsmi_set_num_vf(amdsmi_processor_handle processor_handle, uint32_t num_vf);
2429 
2445 amdsmi_get_vf_partition_info(amdsmi_processor_handle processor_handle, unsigned int vf_buffer_num,
2446  amdsmi_partition_info_t *info);
2447  // end of fbpart
2449 
2450 /*****************************************************************************/
2467 
2480  // end of vfconf
2482 
2483 /*****************************************************************************/
2520 amdsmi_event_create(amdsmi_processor_handle *processor_list, uint32_t num_devices,
2521  uint64_t event_types, amdsmi_event_set *set);
2522 
2551 amdsmi_event_read(amdsmi_event_set set, int64_t timeout_usec, amdsmi_event_entry_t *event);
2552 
2561 amdsmi_event_destroy(amdsmi_event_set set);
2562  // end of eventmon
2564 
2565 /*****************************************************************************/
2585 
2599 
2611 amdsmi_get_partition_profile_info(amdsmi_processor_handle processor_handle,
2612  amdsmi_profile_info_t *profile_info);
2613  // end of hostguest
2615 
2616 /*****************************************************************************/
2631 amdsmi_status_t amdsmi_get_link_metrics(amdsmi_processor_handle processor_handle,
2632  amdsmi_link_metrics_t *link_metrics);
2633 
2646 amdsmi_status_t amdsmi_get_link_topology(amdsmi_processor_handle processor_handle_src,
2647  amdsmi_processor_handle processor_handle_dst,
2648  amdsmi_link_topology_t *topology_info);
2649 
2674 amdsmi_status_t amdsmi_get_link_topology_nearest(amdsmi_processor_handle processor_handle,
2675  amdsmi_link_type_t link_type,
2676  amdsmi_topology_nearest_t *topology_nearest_info);
2677 
2688 amdsmi_status_t amdsmi_get_xgmi_fb_sharing_caps(amdsmi_processor_handle processor_handle,
2690 
2705 amdsmi_status_t amdsmi_get_xgmi_fb_sharing_mode_info(amdsmi_processor_handle processor_handle_src,
2706  amdsmi_processor_handle processor_handle_dst,
2707  amdsmi_xgmi_fb_sharing_mode_t mode,
2708  uint8_t *fb_sharing);
2709 
2721 amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode(amdsmi_processor_handle processor_handle,
2722  amdsmi_xgmi_fb_sharing_mode_t mode);
2723 
2746 amdsmi_status_t amdsmi_set_xgmi_fb_sharing_mode_v2(amdsmi_processor_handle *processor_list, uint32_t num_processors,
2747  amdsmi_xgmi_fb_sharing_mode_t mode);
2748 
2749 
2775 amdsmi_topo_get_p2p_status(amdsmi_processor_handle processor_handle_src,
2776  amdsmi_processor_handle processor_handle_dst,
2777  amdsmi_link_type_t *type, amdsmi_p2p_capability_t *cap);
2778 
2779 
2780  // end of xgmi
2782 
2783 /*****************************************************************************/
2796 amdsmi_status_t amdsmi_clear_vf_fb(amdsmi_vf_handle_t vf_handle); // end of vfmanagement
2798 
2815 
2816 /*****************************************************************************/
2832  amdsmi_get_gpu_memory_partition_config(amdsmi_processor_handle processor_handle,
2834 
2845 amdsmi_set_gpu_memory_partition_mode(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_type_t mode);
2846 
2858 amdsmi_get_gpu_accelerator_partition_profile_config(amdsmi_processor_handle processor_handle,
2860 
2875 amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle,
2876  amdsmi_accelerator_partition_profile_t *profile, uint32_t *partition_id);
2877 
2888 amdsmi_set_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, uint32_t profile_index);
2889  // end of partitioning
2891 
2892 
2926 amdsmi_get_gpu_cper_entries(amdsmi_processor_handle processor_handle, uint32_t severity_mask, char *cper_data,
2927  uint64_t *buf_size, amdsmi_cper_hdr_t** cper_hdrs, uint64_t *entry_count, uint64_t *cursor);
2928 
2952 amdsmi_status_t amdsmi_get_afids_from_cper(char *cper_buffer, uint32_t buf_size, uint64_t *afids, uint32_t *num_afids);
2953 
2968 amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle);
2969 
2970 
2971 #endif // __AMDSMI_H__
#define AMDSMI_MAX_DATE_LENGTH
YYYY-MM-DD:HH:MM:SS.MSC.
Definition: amdsmi.h:69
amdsmi_accelerator_partition_type_t
Definition: amdsmi.h:1093
@ AMDSMI_ACCELERATOR_PARTITION_DPX
together with shared memory
Definition: amdsmi.h:1097
@ AMDSMI_ACCELERATOR_PARTITION_QPX
work together with shared memory
Definition: amdsmi.h:1101
@ AMDSMI_ACCELERATOR_PARTITION_SPX
together with shared memory
Definition: amdsmi.h:1095
@ AMDSMI_ACCELERATOR_PARTITION_TPX
work together with shared memory
Definition: amdsmi.h:1099
@ AMDSMI_ACCELERATOR_PARTITION_CPX
shared memory
Definition: amdsmi.h:1103
amdsmi_clk_type_t
Clock types.
Definition: amdsmi.h:316
@ AMDSMI_CLK_TYPE_SYS
System clock.
Definition: amdsmi.h:317
@ AMDSMI_CLK_TYPE_DCEF
Display Controller Engine clock.
Definition: amdsmi.h:322
@ AMDSMI_CLK_TYPE_DF
running on a separate clock)
Definition: amdsmi.h:320
amdsmi_status_t amdsmi_status_code_to_string(amdsmi_status_t status, const char **status_string)
Get a description of a provided AMDSMI error status.
amdsmi_profile_capability_type_t
Definition: amdsmi.h:883
@ AMDSMI_PROFILE_CAPABILITY_DECODE
decode engine
Definition: amdsmi.h:886
@ AMDSMI_PROFILE_CAPABILITY_MEMORY
memory
Definition: amdsmi.h:884
@ AMDSMI_PROFILE_CAPABILITY_ENCODE
encode engine
Definition: amdsmi.h:885
@ AMDSMI_PROFILE_CAPABILITY_COMPUTE
compute engine
Definition: amdsmi.h:887
amdsmi_init_flags_t
Initialization flags.
Definition: amdsmi.h:43
@ AMDSMI_INIT_ALL_PROCESSORS
Initialize all processors.
Definition: amdsmi.h:44
amdsmi_metric_type_t
Definition: amdsmi.h:1065
@ AMDSMI_METRIC_TYPE_COUNTER
counter metric
Definition: amdsmi.h:1066
@ AMDSMI_METRIC_TYPE_CHIPLET
chiplet metric
Definition: amdsmi.h:1067
@ AMDSMI_METRIC_TYPE_ACC
accumulated metric
Definition: amdsmi.h:1069
@ AMDSMI_METRIC_TYPE_INST
instantaneous metric
Definition: amdsmi.h:1068
amdsmi_fw_block_t
Definition: amdsmi.h:218
@ AMDSMI_FW_ID_RLX6
FW_ID_MES_THREAD1_STACK = MES_KIQ_STACK.
Definition: amdsmi.h:269
@ AMDSMI_FW_ID_DMCU_ISR
ISR.
Definition: amdsmi.h:242
@ AMDSMI_FW_ID_MES_THREAD1
FW_ID_MES_THREAD1 = CP_MES_KIQ.
Definition: amdsmi.h:267
@ AMDSMI_FW_ID_DMCU_ERAM
eRAM
Definition: amdsmi.h:241
amdsmi_mm_ip_t
GPU Capability info.
Definition: amdsmi.h:306
amdsmi_guest_fw_engine_id_t
The values of this enum are used to identify the various firmware blocks.
Definition: amdsmi.h:768
amdsmi_status_t amdsmi_reset_gpu(amdsmi_processor_handle processor_handle)
Reset the gpu associated with the device with provided processor handle. It is not supported on virtu...
amdsmi_ecc_correction_schema_support_t
The values of this enum are used to identify supported ecc correction schema.
Definition: amdsmi.h:757
amdsmi_memory_partition_type_t
Memory Partitions. This enum is used to identify various memory partition types.
Definition: amdsmi.h:1076
@ AMDSMI_MEMORY_PARTITION_NPS8
Definition: amdsmi.h:1086
@ AMDSMI_MEMORY_PARTITION_NPS1
across all 8 HBM stacks (all stacks/1).
Definition: amdsmi.h:1078
@ AMDSMI_MEMORY_PARTITION_NPS2
Definition: amdsmi.h:1080
@ AMDSMI_MEMORY_PARTITION_NPS4
Definition: amdsmi.h:1083
amdsmi_event_gpu_t
Below are the error subcodes of each category.
Definition: amdsmi.h:423
amdsmi_cache_property_type_t
cache properties
Definition: amdsmi.h:210
amdsmi_status_t amdsmi_get_afids_from_cper(char *cper_buffer, uint32_t buf_size, uint64_t *afids, uint32_t *num_afids)
Get the AFIDs from CPER buffer.
#define AMDSMI_MAX_DEVICES
Maximum size definitions AMDSMI.
Definition: amdsmi.h:55
#define AMDSMI_EVENT_MSG_SIZE
256 BYTES
Definition: amdsmi.h:83
amdsmi_status_t
ENUMERATORS.
Definition: amdsmi.h:154
@ AMDSMI_STATUS_NOT_INIT
Processor not initialized.
Definition: amdsmi.h:180
@ AMDSMI_STATUS_NON_AMD_CPU
System has different cpu than AMD.
Definition: amdsmi.h:189
@ AMDSMI_STATUS_INVAL
Invalid parameters.
Definition: amdsmi.h:157
@ AMDSMI_STATUS_BUSY
Processor busy.
Definition: amdsmi.h:178
@ AMDSMI_STATUS_UNKNOWN_ERROR
An unknown error occurred.
Definition: amdsmi.h:204
@ AMDSMI_STATUS_DRIVER_NOT_LOADED
Processor driver not loaded.
Definition: amdsmi.h:182
@ AMDSMI_STATUS_FILE_ERROR
Problem accessing a file.
Definition: amdsmi.h:170
@ AMDSMI_STATUS_DRM_ERROR
Error when call libdrm.
Definition: amdsmi.h:162
@ AMDSMI_STATUS_ARG_PTR_NULL
Parsed argument is invalid.
Definition: amdsmi.h:198
@ AMDSMI_STATUS_IO
I/O Error.
Definition: amdsmi.h:168
@ AMDSMI_STATUS_NO_HSMP_DRV
HSMP driver not found.
Definition: amdsmi.h:192
@ AMDSMI_STATUS_HSMP_TIMEOUT
HSMP message is timedout.
Definition: amdsmi.h:195
@ AMDSMI_STATUS_NO_DATA
No data was found for a given input.
Definition: amdsmi.h:184
@ AMDSMI_STATUS_RETRY
Retry operation.
Definition: amdsmi.h:165
@ AMDSMI_STATUS_UNEXPECTED_SIZE
An unexpected amount of data was read.
Definition: amdsmi.h:186
@ AMDSMI_STATUS_SETTING_UNAVAILABLE
Setting is not available.
Definition: amdsmi.h:200
@ AMDSMI_STATUS_FILE_NOT_FOUND
file or directory not found
Definition: amdsmi.h:197
@ AMDSMI_STATUS_INTERNAL_EXCEPTION
An internal exception was caught.
Definition: amdsmi.h:172
@ AMDSMI_STATUS_NO_HSMP_SUP
HSMP not supported.
Definition: amdsmi.h:193
@ AMDSMI_STATUS_MAP_ERROR
The internal library error did not map to a status code.
Definition: amdsmi.h:203
@ AMDSMI_STATUS_FAIL_LOAD_SYMBOL
Fail to load symbol.
Definition: amdsmi.h:161
@ AMDSMI_STATUS_INSUFFICIENT_SIZE
Not enough resources were available for the operation.
Definition: amdsmi.h:185
@ AMDSMI_STATUS_INIT_ERROR
An error occurred when initializing internal data structures.
Definition: amdsmi.h:174
@ AMDSMI_STATUS_OUT_OF_RESOURCES
Not enough memory.
Definition: amdsmi.h:171
@ AMDSMI_STATUS_NO_SLOT
No more free slot.
Definition: amdsmi.h:181
@ AMDSMI_STATUS_NO_MSR_DRV
MSR driver not found.
Definition: amdsmi.h:191
@ AMDSMI_STATUS_INTERRUPT
An interrupt occurred during execution of function.
Definition: amdsmi.h:167
@ AMDSMI_STATUS_SUCCESS
Call succeeded.
Definition: amdsmi.h:155
@ AMDSMI_STATUS_NO_ENERGY_DRV
Energy driver not found.
Definition: amdsmi.h:190
@ AMDSMI_STATUS_ADDRESS_FAULT
Bad address.
Definition: amdsmi.h:169
@ AMDSMI_STATUS_NOT_YET_IMPLEMENTED
Not implemented yet.
Definition: amdsmi.h:159
@ AMDSMI_STATUS_NO_DRV
No Energy and HSMP driver present.
Definition: amdsmi.h:196
@ AMDSMI_STATUS_NO_PERM
Permission Denied.
Definition: amdsmi.h:166
@ AMDSMI_STATUS_NOT_FOUND
Processor not found.
Definition: amdsmi.h:179
@ AMDSMI_STATUS_FAIL_LOAD_MODULE
Fail to load lib.
Definition: amdsmi.h:160
@ AMDSMI_STATUS_AMDGPU_RESTART_ERR
AMDGPU restart failed.
Definition: amdsmi.h:199
@ AMDSMI_STATUS_NOT_SUPPORTED
Command not supported.
Definition: amdsmi.h:158
@ AMDSMI_STATUS_UNEXPECTED_DATA
The data read or provided to function is not what was expected.
Definition: amdsmi.h:187
@ AMDSMI_STATUS_API_FAILED
API call failed.
Definition: amdsmi.h:163
@ AMDSMI_STATUS_TIMEOUT
Timeout in API call.
Definition: amdsmi.h:164
@ AMDSMI_STATUS_NO_HSMP_MSG_SUP
HSMP message/feature not supported.
Definition: amdsmi.h:194
@ AMDSMI_STATUS_INPUT_OUT_OF_BOUNDS
The provided input is out of allowable or safe range.
Definition: amdsmi.h:173
@ AMDSMI_STATUS_REFCOUNT_OVERFLOW
An internal reference counter exceeded INT32_MAX.
Definition: amdsmi.h:175
amdsmi_temperature_metric_t
Temperature Metrics. This enum is used to identify various temperature metrics. Corresponding values ...
Definition: amdsmi.h:353
@ AMDSMI_TEMP_CRITICAL_HYST
Definition: amdsmi.h:366
@ AMDSMI_TEMP_CRITICAL
greater than corresponding temp_max values.
Definition: amdsmi.h:364
@ AMDSMI_TEMP_OFFSET
Definition: amdsmi.h:382
@ AMDSMI_TEMP_EMERGENCY
Definition: amdsmi.h:369
@ AMDSMI_TEMP_LOWEST
temperature reading by the chip.
Definition: amdsmi.h:384
@ AMDSMI_TEMP_CRIT_MIN
Definition: amdsmi.h:376
@ AMDSMI_TEMP_SHUTDOWN
Shutdown temperature.
Definition: amdsmi.h:386
@ AMDSMI_TEMP_EMERGENCY_HYST
Definition: amdsmi.h:373
@ AMDSMI_TEMP_CURRENT
Temperature current value.
Definition: amdsmi.h:354
@ AMDSMI_TEMP_MIN
Temperature min value.
Definition: amdsmi.h:357
@ AMDSMI_TEMP_HIGHEST
Historical maximum temperature.
Definition: amdsmi.h:385
@ AMDSMI_TEMP_CRIT_MIN_HYST
Definition: amdsmi.h:379
@ AMDSMI_TEMP_MIN_HYST
Definition: amdsmi.h:361
@ AMDSMI_TEMP_MAX_HYST
Definition: amdsmi.h:358
@ AMDSMI_TEMP_MAX
Temperature max value.
Definition: amdsmi.h:356
amdsmi_gpu_block_t
Definition: amdsmi.h:926
@ AMDSMI_GPU_BLOCK_XGMI_WAFL
XGMI block.
Definition: amdsmi.h:938
@ AMDSMI_GPU_BLOCK_GFX
GFX block.
Definition: amdsmi.h:933
@ AMDSMI_GPU_BLOCK_IH
IH block.
Definition: amdsmi.h:948
@ AMDSMI_GPU_BLOCK_VCN
VCN block.
Definition: amdsmi.h:946
@ AMDSMI_GPU_BLOCK_INVALID
invalid block
Definition: amdsmi.h:927
@ AMDSMI_GPU_BLOCK_MP0
MP0 block.
Definition: amdsmi.h:942
@ AMDSMI_GPU_BLOCK_HDP
HDP block.
Definition: amdsmi.h:937
@ AMDSMI_GPU_BLOCK_MPIO
MPIO block.
Definition: amdsmi.h:949
@ AMDSMI_GPU_BLOCK_ATHUB
ATHUB block.
Definition: amdsmi.h:935
@ AMDSMI_GPU_BLOCK_MP1
MP1 block.
Definition: amdsmi.h:943
@ AMDSMI_GPU_BLOCK_PCIE_BIF
PCIE_BIF block.
Definition: amdsmi.h:936
@ AMDSMI_GPU_BLOCK_SDMA
SDMA block.
Definition: amdsmi.h:932
@ AMDSMI_GPU_BLOCK_JPEG
JPEG block.
Definition: amdsmi.h:947
@ AMDSMI_GPU_BLOCK_UMC
UMC block.
Definition: amdsmi.h:931
@ AMDSMI_GPU_BLOCK_FUSE
Fuse block.
Definition: amdsmi.h:944
@ AMDSMI_GPU_BLOCK_DF
DF block.
Definition: amdsmi.h:939
@ AMDSMI_GPU_BLOCK_MMHUB
MMHUB block.
Definition: amdsmi.h:934
@ AMDSMI_GPU_BLOCK_SMN
SMN block.
Definition: amdsmi.h:940
@ AMDSMI_GPU_BLOCK_SEM
SEM block.
Definition: amdsmi.h:941
@ AMDSMI_GPU_BLOCK_MCA
MCA block.
Definition: amdsmi.h:945
amdsmi_status_t amdsmi_get_gpu_cper_entries(amdsmi_processor_handle processor_handle, uint32_t severity_mask, char *cper_data, uint64_t *buf_size, amdsmi_cper_hdr_t **cper_hdrs, uint64_t *entry_count, uint64_t *cursor)
Retrieve CPER entries cached in the driver.
amdsmi_temperature_type_t
This enumeration is used to indicate from which part of the processor a temperature reading should be...
Definition: amdsmi.h:336
void * amdsmi_socket_handle
opaque handler point to underlying implementation
Definition: amdsmi.h:147
amdsmi_status_t amdsmi_set_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, uint32_t profile_index)
Sets accelerator partition setting based on profile_index from amdsmi_get_gpu_accelerator_partition_p...
amdsmi_status_t amdsmi_get_gpu_memory_partition_config(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_config_t *config)
Returns current gpu memory partition config and mode capabilities.
amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile_config(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_config_t *profile_config)
Returns gpu accelerator partition caps as currently configured in the system.
amdsmi_status_t amdsmi_set_gpu_memory_partition_mode(amdsmi_processor_handle processor_handle, amdsmi_memory_partition_type_t mode)
Sets memory partition mode.
amdsmi_status_t amdsmi_get_gpu_accelerator_partition_profile(amdsmi_processor_handle processor_handle, amdsmi_accelerator_partition_profile_t *profile, uint32_t *partition_id)
Returns current gpu accelerator partition cap.
amdsmi_status_t amdsmi_get_fb_layout(amdsmi_processor_handle processor_handle, amdsmi_pf_fb_info_t *info)
Returns the framebuffer info for the ASIC.
amdsmi_status_t amdsmi_get_power_cap_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, amdsmi_power_cap_info_t *info)
Returns the power caps as currently configured in the system.
amdsmi_status_t amdsmi_get_pcie_info(amdsmi_processor_handle processor_handle, amdsmi_pcie_info_t *info)
Returns the PCIe info for the GPU.
amdsmi_status_t amdsmi_get_gpu_vram_info(amdsmi_processor_handle processor_handle, amdsmi_vram_info_t *info)
Returns vram info.
amdsmi_status_t amdsmi_get_gpu_asic_info(amdsmi_processor_handle processor_handle, amdsmi_asic_info_t *info)
Returns the ASIC information for the processor.
amdsmi_status_t amdsmi_get_processor_handles(amdsmi_socket_handle socket_handle, uint32_t *processor_count, amdsmi_processor_handle *processor_handles)
Returns a list of AMD GPU devices in the system.
amdsmi_status_t amdsmi_get_index_from_processor_handle(amdsmi_processor_handle processor_handle, uint32_t *processor_index)
Returns the index of the given processor handle.
amdsmi_status_t amdsmi_get_gpu_device_uuid(amdsmi_processor_handle processor_handle, unsigned int *uuid_length, char *uuid)
Returns the UUID of the processor.
amdsmi_status_t amdsmi_get_processor_type(amdsmi_processor_handle processor_handle, processor_type_t *processor_type)
Get the processor type.
amdsmi_status_t amdsmi_get_socket_info(amdsmi_socket_handle socket_handle, size_t len, char *name)
Returns socket information about given socket handle NOT SUPPORTED YET, CURRENTLY HARDCODED TO RETURN...
amdsmi_status_t amdsmi_get_gpu_virtualization_mode(amdsmi_processor_handle processor_handle, amdsmi_virtualization_mode_t *mode)
Returns the virtualization mode for the target device.
amdsmi_status_t amdsmi_get_processor_handle_from_uuid(const char *uuid, amdsmi_processor_handle *processor_handle)
Returns the processor handle from the given UUID.
amdsmi_status_t amdsmi_get_socket_handles(uint32_t *socket_count, amdsmi_socket_handle *socket_handles)
Returns a list of socket handles in the system. NOT SUPPORTED YET, CURRENTLY HARDCODED TO RETURN EMPT...
amdsmi_status_t amdsmi_get_vf_bdf(amdsmi_vf_handle_t vf_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given device (VF).
amdsmi_status_t amdsmi_get_vf_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_vf_handle_t *vf_handle)
Returns VF handle from the given BDF.
amdsmi_status_t amdsmi_get_processor_handle_from_bdf(amdsmi_bdf_t bdf, amdsmi_processor_handle *processor_handle)
Returns processor handle (PF) from the given BDF.
amdsmi_status_t amdsmi_get_vf_handle_from_vf_index(amdsmi_processor_handle processor_handle, uint32_t fcn_idx, amdsmi_vf_handle_t *vf_handle)
Returns the handle of a virtual function given its index.
amdsmi_status_t amdsmi_get_vf_uuid(amdsmi_vf_handle_t processor_handle, unsigned int *uuid_length, char *uuid)
Returns the UUID of the VF.
amdsmi_status_t amdsmi_get_gpu_device_bdf(amdsmi_processor_handle processor_handle, amdsmi_bdf_t *bdf)
Returns BDF of the given processor (PF or VF).
amdsmi_status_t amdsmi_get_vf_handle_from_uuid(const char *uuid, amdsmi_vf_handle_t *vf_handle)
Returns the handle of a virtual function from the given UUID.
amdsmi_status_t amdsmi_get_processor_handle_from_index(uint32_t processor_index, amdsmi_processor_handle *processor_handle)
Returns the processor handle from the given processor index.
amdsmi_status_t amdsmi_get_gpu_total_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_error_count_t *ec)
Returns the number of ECC errors (correctable, uncorrectable and deferred) in the given GPU.
amdsmi_status_t amdsmi_get_gpu_ecc_count(amdsmi_processor_handle processor_handle, amdsmi_gpu_block_t block, amdsmi_error_count_t *ec)
Returns the number of ECC errors (correctable, uncorrectable and deferred) for the given GPU block.
amdsmi_status_t amdsmi_get_gpu_ecc_enabled(amdsmi_processor_handle processor_handle, uint64_t *enabled_blocks)
Returns the enabled ECC bitmask.
amdsmi_status_t amdsmi_get_bad_page_threshold(amdsmi_processor_handle processor_handle, uint32_t *threshold)
Get the bad page threshold for a device.
amdsmi_status_t amdsmi_get_gpu_ras_feature_info(amdsmi_processor_handle processor_handle, amdsmi_ras_feature_t *ras_feature)
Returns RAS features info.
amdsmi_status_t amdsmi_get_gpu_bad_page_info(amdsmi_processor_handle processor_handle, uint32_t *bad_page_size, amdsmi_eeprom_table_record_t *bad_pages)
Returns the bad page info.
amdsmi_status_t amdsmi_event_destroy(amdsmi_event_set set)
Destroys and frees an event set.
amdsmi_status_t amdsmi_event_read(amdsmi_event_set set, int64_t timeout_usec, amdsmi_event_entry_t *event)
The call blocks till timeout is expired to copy one event specified by the event set into the user pr...
amdsmi_status_t amdsmi_event_create(amdsmi_processor_handle *processor_list, uint32_t num_devices, uint64_t event_types, amdsmi_event_set *set)
Allocate a new event set notifier to monitor different types of issues with the GPU running virtualiz...
amdsmi_status_t amdsmi_get_vf_partition_info(amdsmi_processor_handle processor_handle, unsigned int vf_buffer_num, amdsmi_partition_info_t *info)
Returns the current framebuffer partitioning structure as currently configured by the driver.
amdsmi_status_t amdsmi_get_num_vf(amdsmi_processor_handle processor_handle, uint32_t *num_vf_enabled, uint32_t *num_vf_supported)
Returns the number of VFs enabled by gpuv in the ASIC.
amdsmi_status_t amdsmi_set_num_vf(amdsmi_processor_handle processor_handle, uint32_t num_vf)
Enable a given number of VF.
amdsmi_status_t amdsmi_get_gpu_vbios_info(amdsmi_processor_handle processor_handle, amdsmi_vbios_info_t *info)
Returns the static information for the vBIOS on the processor.
amdsmi_status_t amdsmi_get_fw_info(amdsmi_processor_handle processor_handle, amdsmi_fw_info_t *info)
Returns the firmware versions running on PF of the processor.
amdsmi_status_t amdsmi_get_gpu_board_info(amdsmi_processor_handle processor_handle, amdsmi_board_info_t *info)
Returns the board part number and board information for the requested processor.
amdsmi_status_t amdsmi_get_dfc_fw_table(amdsmi_processor_handle processor_handle, amdsmi_dfc_fw_t *info)
Returns the DFC fw table.
amdsmi_status_t amdsmi_get_fw_error_records(amdsmi_processor_handle processor_handle, amdsmi_fw_error_record_t *records)
Gets firmware error records.
amdsmi_status_t amdsmi_get_gpu_metrics(amdsmi_processor_handle processor_handle, uint32_t *metrics_size, amdsmi_metric_t *metrics)
Returns metrics information.
amdsmi_status_t amdsmi_get_power_info(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, amdsmi_power_info_t *info)
Returns the current power and voltage of the GPU.
amdsmi_status_t amdsmi_get_temp_metric(amdsmi_processor_handle processor_handle, amdsmi_temperature_type_t sensor_type, amdsmi_temperature_metric_t metric, int64_t *temperature)
Returns temperature measurements of the GPU. The results are in °C.
amdsmi_status_t amdsmi_get_gpu_activity(amdsmi_processor_handle processor_handle, amdsmi_engine_usage_t *info)
Returns the current usage of the GPU engines (GFX, MM and MEM). Each usage is reported as a percentag...
amdsmi_status_t amdsmi_get_clock_info(amdsmi_processor_handle processor_handle, amdsmi_clk_type_t clk_type, amdsmi_clk_info_t *info)
Returns the measurements of the clocks in the GPU for the GFX and multimedia engines and Memory....
amdsmi_status_t amdsmi_set_power_cap(amdsmi_processor_handle processor_handle, uint32_t sensor_ind, uint64_t cap)
Sets GPU power cap.
amdsmi_status_t amdsmi_get_soc_pstate(amdsmi_processor_handle processor_handle, amdsmi_dpm_policy_t *policy)
Returns the soc pstate policy for the processor.
amdsmi_status_t amdsmi_set_soc_pstate(amdsmi_processor_handle processor_handle, uint32_t policy_id)
Set the soc pstate policy for the processor.
amdsmi_status_t amdsmi_get_gpu_cache_info(amdsmi_processor_handle processor_handle, amdsmi_gpu_cache_info_t *info)
Returns gpu cache info.
amdsmi_status_t amdsmi_is_gpu_power_management_enabled(amdsmi_processor_handle processor_handle, bool *enabled)
Returns is power management enabled.
amdsmi_status_t amdsmi_get_guest_data(amdsmi_vf_handle_t vf_handle, amdsmi_guest_data_t *info)
Returns guest OS information of the queried VF. The fw_info field from the amdsmi_guest_data structur...
amdsmi_status_t amdsmi_get_partition_profile_info(amdsmi_processor_handle processor_handle, amdsmi_profile_info_t *profile_info)
Return the list of supported profiles on the given GPU device.
amdsmi_status_t amdsmi_get_vf_fw_info(amdsmi_vf_handle_t vf_handle, amdsmi_fw_info_t *info)
Returns the firmware versions running on a VF. In case the VM is not started on the VF,...
amdsmi_status_t amdsmi_shut_down(void)
The library frees all associated with the library on the current process.
amdsmi_status_t amdsmi_init(uint64_t init_flags)
Initializes the library and the internal software structures.
amdsmi_status_t amdsmi_get_gpu_driver_info(amdsmi_processor_handle processor_handle, amdsmi_driver_info_t *info)
Returns the driver version information.
amdsmi_status_t amdsmi_get_gpu_driver_model(amdsmi_processor_handle processor_handle, amdsmi_driver_model_type_t *model)
Returns the driver model information.
amdsmi_status_t amdsmi_get_lib_version(amdsmi_version_t *version)
Get the build version information for the currently running build of AMDSMI.
amdsmi_status_t amdsmi_get_vf_info(amdsmi_vf_handle_t vf_handle, amdsmi_vf_info_t *config)
Returns the configuration structure for a VF.
amdsmi_status_t amdsmi_get_vf_data(amdsmi_vf_handle_t vf_handle, amdsmi_vf_data_t *info)
Returns the data structure for a VF.
amdsmi_status_t amdsmi_clear_vf_fb(amdsmi_vf_handle_t vf_handle)
Clear the framebuffer of a VF. If trying to clear the framebuffer of an active function,...
uint32_t default_profile_index
The index of the default profile in the profiles array.
Definition: amdsmi.h:1569
uint32_t num_profiles
The length of profiles array.
Definition: amdsmi.h:1566
uint32_t profile_index
The index in the profiles array in amdsmi_accelerator_partition_profile_t.
Definition: amdsmi.h:1551
uint32_t num_partitions
On MI300X, SPX: 1, DPX: 2, QPX: 4, CPX: 8.
Definition: amdsmi.h:1549
amdsmi_nps_caps_t memory_caps
Memory capabilities of the profile.
Definition: amdsmi.h:1550
amdsmi_accelerator_partition_type_t profile_type
SPX, DPX, QPX, CPX and so on.
Definition: amdsmi.h:1548
uint32_t num_resources
length of array resources
Definition: amdsmi.h:1552
uint32_t partition_resource
The resources a partition can be used, which may be shared.
Definition: amdsmi.h:1560
uint32_t num_partitions_share_resource
If it is greater than 1, then resource is shared.
Definition: amdsmi.h:1561
Definition: amdsmi.h:1212
uint32_t vendor_id
Use 32 bit to be compatible with other platform.
Definition: amdsmi.h:1217
uint64_t device_id
The unique id of a GPU.
Definition: amdsmi.h:1219
uint32_t subvendor_id
The subsystem vendor id.
Definition: amdsmi.h:1218
uint32_t subsystem_id
The subsystem device id.
Definition: amdsmi.h:1224
Definition: amdsmi.h:1138
Definition: amdsmi.h:1289
Definition: amdsmi.h:1250
Definition: amdsmi.h:1601
Definition: amdsmi.h:1635
Definition: amdsmi.h:1614
Definition: amdsmi.h:1626
Definition: amdsmi.h:1409
Definition: amdsmi.h:1392
Definition: amdsmi.h:1421
Definition: amdsmi.h:1405
Definition: amdsmi.h:1400
Definition: amdsmi.h:1574
Definition: amdsmi.h:1580
uint32_t cur
Definition: amdsmi.h:1589
uint32_t num_supported
Definition: amdsmi.h:1584
Definition: amdsmi.h:1228
Definition: amdsmi.h:1426
uint64_t retired_page
Bad page frame address.
Definition: amdsmi.h:1427
Definition: amdsmi.h:1243
Definition: amdsmi.h:1259
uint64_t uncorrectable_count
Accumulated uncorrectable errors.
Definition: amdsmi.h:1261
uint64_t correctable_count
Accumulated correctable errors.
Definition: amdsmi.h:1260
uint64_t deferred_count
Accumulated deferred errors.
Definition: amdsmi.h:1262
Definition: amdsmi.h:1276
uint64_t timestamp
UTC microseconds.
Definition: amdsmi.h:1279
Definition: amdsmi.h:1447
Definition: amdsmi.h:1202
Definition: amdsmi.h:1439
uint64_t timestamp
UTC microseconds.
Definition: amdsmi.h:1440
uint16_t status
Definition: amdsmi.h:1443
Definition: amdsmi.h:1191
Definition: amdsmi.h:1189
Definition: amdsmi.h:1320
Definition: amdsmi.h:1386
uint32_t fb_usage
Definition: amdsmi.h:1388
Definition: amdsmi.h:1535
Definition: amdsmi.h:1502
uint32_t flags
used to determine type of the metric (amdsmi_metric_type_t)
Definition: amdsmi.h:1506
uint32_t vf_mask
Mask of all active VFs + PF that this metric applies to.
Definition: amdsmi.h:1507
Definition: amdsmi.h:1525
Definition: amdsmi.h:1671
uint8_t is_iolink_coherent
1 = true, 0 = false, UINT8_MAX = Not defined.
Definition: amdsmi.h:1672
Definition: amdsmi.h:1314
Definition: amdsmi.h:1156
uint64_t pcie_nak_received_count
total number of NAKs issued on the PCIe link by the receiver
Definition: amdsmi.h:1164
uint64_t pcie_replay_count
total number of the replays issued on the PCIe link
Definition: amdsmi.h:1160
uint16_t pcie_width
current PCIe width
Definition: amdsmi.h:1157
uint32_t pcie_speed
current PCIe speed in MT/s
Definition: amdsmi.h:1158
uint32_t pcie_bandwidth
current PCIe bandwidth in Mb/s
Definition: amdsmi.h:1159
uint64_t pcie_l0_to_recovery_count
total number of times the PCIe link transitioned from L0 to the recovery state
Definition: amdsmi.h:1161
uint64_t pcie_nak_sent_count
total number of NAKs issued on the PCIe link by the device
Definition: amdsmi.h:1163
uint64_t pcie_replay_roll_over_count
total number of replay rollovers issued on the PCIe link
Definition: amdsmi.h:1162
uint32_t pcie_lc_perf_other_end_recovery_count
PCIe other end recovery counter.
Definition: amdsmi.h:1165
Definition: amdsmi.h:1148
uint16_t max_pcie_width
maximum number of PCIe lanes
Definition: amdsmi.h:1149
uint32_t max_pcie_interface_version
maximum PCIe link generation
Definition: amdsmi.h:1153
amdsmi_card_form_factor_t slot_type
card form factor
Definition: amdsmi.h:1152
uint32_t max_pcie_speed
maximum PCIe speed
Definition: amdsmi.h:1150
uint32_t pcie_interface_version
PCIe interface version.
Definition: amdsmi.h:1151
Definition: amdsmi.h:1147
Definition: amdsmi.h:1298
uint32_t pf_fb_reserved
Definition: amdsmi.h:1300
uint32_t min_vf_fb_usable
Definition: amdsmi.h:1304
uint32_t fb_alignment
Definition: amdsmi.h:1302
uint32_t total_fb_size
Definition: amdsmi.h:1299
uint32_t max_vf_fb_usable
Definition: amdsmi.h:1303
uint32_t pf_fb_offset
Definition: amdsmi.h:1301
Definition: amdsmi.h:1172
Definition: amdsmi.h:1235
uint64_t soc_voltage
SOC voltage measurement in mV.
Definition: amdsmi.h:1238
uint64_t mem_voltage
MEM voltage measurement in mV.
Definition: amdsmi.h:1239
uint64_t gfx_voltage
GFX voltage measurement in mV.
Definition: amdsmi.h:1237
Definition: amdsmi.h:1367
Definition: amdsmi.h:1376
Definition: amdsmi.h:1266
uint32_t supported_ecc_correction_schema
ecc_correction_schema mask used with amdsmi_ecc_correction_schema_support_t flags
Definition: amdsmi.h:1268
Definition: amdsmi.h:1342
uint64_t boot_up_time
in microseconds
Definition: amdsmi.h:1344
Definition: amdsmi.h:1476
Definition: amdsmi.h:1181
This structure holds version information.
Definition: amdsmi.h:1515
uint32_t minor
Minor version.
Definition: amdsmi.h:1517
uint32_t major
Major version.
Definition: amdsmi.h:1516
uint32_t release
Patch, build or stepping version.
Definition: amdsmi.h:1518
Definition: amdsmi.h:1361
Definition: amdsmi.h:1308
uint32_t fb_size
Definition: amdsmi.h:1310
uint32_t fb_offset
Definition: amdsmi.h:1309
Definition: amdsmi.h:1272
Definition: amdsmi.h:1336
uint32_t gfx_timeslice
Definition: amdsmi.h:1338
Definition: amdsmi.h:1494
uint32_t vram_size
vram size in MB
Definition: amdsmi.h:1497
Definition: amdsmi.h:1483
AUX STRUCTURES.
Definition: amdsmi.h:1137
Definition: amdsmi.h:1625
This union holds memory partition bitmask.
Definition: amdsmi.h:1524
Definition: amdsmi.h:1482